From f69814397e7efaf0b2bfa3c83425c906ce6b50f4 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 25 Mar 2013 07:40:07 +0000 Subject: powerpc/chassis2: Change core numbering scheme To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/include/asm/config_mpc85xx.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/powerpc/include/asm/config_mpc85xx.h') diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 08e1238..dd68335 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -517,6 +517,7 @@ #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #ifdef CONFIG_PPC_T4240 #define CONFIG_MAX_CPUS 12 @@ -559,6 +560,7 @@ #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 @@ -581,6 +583,7 @@ #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 @@ -607,6 +610,7 @@ #define CONFIG_E5500 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 @@ -637,4 +641,10 @@ #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." #endif +#ifdef CONFIG_E6500 +#define CONFIG_SYS_FSL_THREADS_PER_CORE 2 +#else +#define CONFIG_SYS_FSL_THREADS_PER_CORE 1 +#endif + #endif /* _ASM_MPC85xx_CONFIG_H_ */ -- cgit v1.1