From df8af0b4a63b6375e7abbaffe1f93cc01c34529c Mon Sep 17 00:00:00 2001 From: Emil Medve Date: Tue, 31 Aug 2010 22:57:38 -0500 Subject: p4080/serdes: Implement the XAUI workaround for SERDES9 erratum Signed-off-by: Emil Medve Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala --- arch/powerpc/include/asm/config_mpc85xx.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/powerpc/include/asm/config_mpc85xx.h') diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 41fd86c..88bc030 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -304,6 +304,7 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC136 #define CONFIG_SYS_P4080_ERRATUM_CPU22 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 +#define CONFIG_SYS_P4080_ERRATUM_SERDES9 /* P5010 is single core version of P5020 */ #elif defined(CONFIG_PPC_P5010) -- cgit v1.1 From 86221f09fb99d37ce5bfceb3ac66ca78f034cb71 Mon Sep 17 00:00:00 2001 From: Roy Zang Date: Wed, 13 Apr 2011 00:08:51 -0500 Subject: powerpc/85xx: Enable Internal USB PHY for p2040, p3041, p5010 and p5020 The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we need to enable for them to function. Signed-off-by: Roy Zang Signed-off-by: Kumar Gala --- arch/powerpc/include/asm/config_mpc85xx.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/powerpc/include/asm/config_mpc85xx.h') diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 88bc030..d93586a 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -264,6 +264,8 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 @@ -275,6 +277,8 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE #elif defined(CONFIG_PPC_P4040) #define CONFIG_MAX_CPUS 4 @@ -317,6 +321,8 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE #elif defined(CONFIG_PPC_P5020) #define CONFIG_MAX_CPUS 2 @@ -328,6 +334,8 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE #else #error Processor type not defined for this platform -- cgit v1.1 From 300097669c705da06e812e517e3b2895814b0310 Mon Sep 17 00:00:00 2001 From: Lei Xu Date: Tue, 19 Apr 2011 15:28:41 +0800 Subject: powerpc/85xx: Enable ESDHC111 erratum on P2040/P3041/P5010/P5020 SoCs The workaround for ESDHC111 should also be applied on P2040/P3041/P5010/P5020 SoCs. Signed-off-by: Lei Xu Signed-off-by: Roy Zang Signed-off-by: Kumar Gala --- arch/powerpc/include/asm/config_mpc85xx.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/powerpc/include/asm/config_mpc85xx.h') diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index d93586a..da2e998 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -266,6 +266,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 @@ -279,6 +280,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_PPC_P4040) #define CONFIG_MAX_CPUS 4 @@ -323,6 +325,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_PPC_P5020) #define CONFIG_MAX_CPUS 2 @@ -336,6 +339,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #else #error Processor type not defined for this platform -- cgit v1.1 From da30b9fd97f031a6b6863359f3d4c6633e5c7035 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Fri, 1 Apr 2011 13:19:36 -0500 Subject: powerpc/85xx: Implement work-around for P4080 erratum SERDES-A005 SerDes PLL bandwidth default setting is incorrect when no lanes are configured as PCI Express. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala --- arch/powerpc/include/asm/config_mpc85xx.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/powerpc/include/asm/config_mpc85xx.h') diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index da2e998..b8b8914 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -311,6 +311,7 @@ #define CONFIG_SYS_P4080_ERRATUM_CPU22 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 +#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 /* P5010 is single core version of P5020 */ #elif defined(CONFIG_PPC_P5010) -- cgit v1.1 From d90fdba6ca0b08c77cced6e914609e3696dd5909 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Mon, 18 Apr 2011 17:16:00 -0500 Subject: powerpc/85xx: Implement work-around for P4080 erratum SERDES-A001 Bank powerdown through RCW[SRDS_LPD_Bn] for XAUI on FM2 and SGMII on FM1 are swapped. Erratum SERDES-A001 says that if bank two is kept disabled and after bank three is enabled, then the PLL for bank three won't lock properly. The work-around is to enable and then disable bank two after bank three is enabled. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala --- arch/powerpc/include/asm/config_mpc85xx.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/powerpc/include/asm/config_mpc85xx.h') diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index b8b8914..ccf703b 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -311,6 +311,7 @@ #define CONFIG_SYS_P4080_ERRATUM_CPU22 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 +#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 /* P5010 is single core version of P5020 */ -- cgit v1.1 From 66412c6371cfd6e056679abedea7d6fafe6a0422 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 18 Feb 2011 05:40:54 -0600 Subject: powerpc/85xx: Change timebase divisor to be defined per processor Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because different SoCs have different divisor amounts. All the PQ3 parts are /8, the P4080/P4080 is /16, and P2040/P3041/P5020 are /32. Signed-off-by: Kumar Gala --- arch/powerpc/include/asm/config_mpc85xx.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/powerpc/include/asm/config_mpc85xx.h') diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index ccf703b..41c2d20 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -264,6 +264,7 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -278,6 +279,7 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -288,6 +290,7 @@ #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 16 #elif defined(CONFIG_PPC_P4080) #define CONFIG_MAX_CPUS 8 @@ -301,6 +304,7 @@ #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 @@ -325,6 +329,7 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -339,6 +344,7 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 -- cgit v1.1