From 7cb7272365983e3a1eedf18a9f688c825e1cf95e Mon Sep 17 00:00:00 2001 From: Tang Yuantian Date: Fri, 4 Jul 2014 17:39:26 +0800 Subject: mpc85xx/t104x: Enable L2 and CPC cache when resume When resume from deep sleep, uboot needs to enable L2 and CPC cache, or they would be keeping unusable in kernel because kernel didn't enble or initialized them. This patch didn't change the existing L2 cache enabling code, just put them in a function. Signed-off-by: Tang Yuantian Reviewed-by: York Sun --- arch/powerpc/include/asm/cache.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/powerpc/include/asm/cache.h') diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h index cdc1f10..d3a8391 100644 --- a/arch/powerpc/include/asm/cache.h +++ b/arch/powerpc/include/asm/cache.h @@ -57,6 +57,12 @@ extern void unlock_ram_in_cache(void); #endif /* CONFIG_SYS_INIT_RAM_LOCK */ #endif /* __ASSEMBLY__ */ +#if defined(__KERNEL__) && !defined(__ASSEMBLY__) +int l2cache_init(void); +void enable_cpc(void); +void disable_cpc_sram(void); +#endif + /* prep registers for L2 */ #define CACHECRBA 0x80000823 /* Cache configuration register address */ #define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */ -- cgit v1.1