From 954a1a4776d135f2c6ee5276a96c0da71744cd6d Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 20 Aug 2013 15:09:43 -0700 Subject: powerpc/mpc85xx: Add workaround for erratum A-005125 In a very rare condition, a system hang is possible when the e500 core initiates a guarded load to PCI / PCIe /SRIO performs a coherent write to memory. Please refer to errata document for more details. This erratum applies to the following SoCs and their variants, if any. BSC9132 BSC9131 MPC8536 MPC8544 MPC8548 MPC8569 MPC8572 P1010 P1020 P1021 P1022 P1023 P2020 C29x Signed-off-by: York Sun CC: Scott Wood --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ arch/powerpc/cpu/mpc85xx/start.S | 8 ++++++++ 2 files changed, 11 insertions(+) (limited to 'arch/powerpc/cpu') diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index eea264b..c441bd2 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -252,6 +252,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 puts("Work-around for Erratum A-005812 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005125 + puts("Work-around for Erratum A005125 enabled\n"); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) || (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV)) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index ad57a9c..be4f4ae 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -108,6 +108,14 @@ _start_e500: isync 2: #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005125 + msync + isync + mfspr r3, SPRN_HDBCR0 + oris r3, r3, 0x0080 + mtspr SPRN_HDBCR0, r3 +#endif + #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) /* ISBC uses L2 as stack. -- cgit v1.1