From e1dbdd81523c7c7de1ac5dee03dd9e4587e808af Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Sun, 23 Dec 2012 19:24:16 +0000 Subject: powerpc/mpc85xx:Add support of B4420 SoC B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420 ---------------------------------------- B4420 has: 1. Fewer e6500 cores: 1 cluster with 2 e6500 cores 2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster. 3. Single DDRC 4. 2X 4 lane serdes 5. 3 SGMII interfaces 6. no sRIO 7. no 10G Signed-off-by: Prabhakar Kushwaha Signed-off-by: Poonam Aggrwal Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/Makefile | 3 +++ arch/powerpc/cpu/mpc85xx/b4860_ids.c | 6 +++++ arch/powerpc/cpu/mpc85xx/b4860_serdes.c | 45 +++++++++++++++++++++++++++++++++ 3 files changed, 54 insertions(+) (limited to 'arch/powerpc/cpu/mpc85xx') diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 4c2b104..95994d3 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -83,6 +83,7 @@ COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o COBJS-$(CONFIG_PPC_P5040) += ddr-gen3.o COBJS-$(CONFIG_PPC_T4240) += ddr-gen3.o +COBJS-$(CONFIG_PPC_B4420) += ddr-gen3.o COBJS-$(CONFIG_PPC_B4860) += ddr-gen3.o COBJS-$(CONFIG_BSC9131) += ddr-gen3.o @@ -100,6 +101,7 @@ COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o COBJS-$(CONFIG_PPC_T4240) += t4240_ids.o +COBJS-$(CONFIG_PPC_B4420) += b4860_ids.o COBJS-$(CONFIG_PPC_B4860) += b4860_ids.o COBJS-$(CONFIG_QE) += qe_io.o @@ -134,6 +136,7 @@ COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o +COBJS-$(CONFIG_PPC_B4420) += b4860_serdes.o COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o COBJS-y += cpu.o diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c index 7d33731..0f4e82e 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c @@ -55,11 +55,13 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { }; #endif +#ifdef CONFIG_SYS_SRIO struct srio_liodn_id_table srio_liodn_tbl[] = { SET_SRIO_LIODN_1(1, 307), SET_SRIO_LIODN_1(2, 387), }; int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); +#endif struct liodn_id_table liodn_tbl[] = { #ifdef CONFIG_SYS_DPAA_QBMAN @@ -76,10 +78,12 @@ struct liodn_id_table liodn_tbl[] = { SET_DMA_LIODN(1, 147), SET_DMA_LIODN(2, 227), +#ifndef CONFIG_PPC_B4420 SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), +#endif /* SET_NEXUS_LIODN(557), -- not yet implemented */ }; @@ -93,8 +97,10 @@ struct liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 3, 91), SET_FMAN_RX_1G_LIODN(1, 4, 92), SET_FMAN_RX_1G_LIODN(1, 5, 93), +#ifndef CONFIG_PPC_B4420 SET_FMAN_RX_10G_LIODN(1, 0, 94), SET_FMAN_RX_10G_LIODN(1, 1, 95), +#endif }; int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); #endif diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c index 0028280..bd32342 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c @@ -31,6 +31,7 @@ struct serdes_config { u8 lanes[SRDS_MAX_LANES]; }; +#ifdef CONFIG_PPC_B4860 static struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ {0x0D, {CPRI8, CPRI7, CPRI6, CPRI5, @@ -128,6 +129,50 @@ static struct serdes_config serdes2_cfg_tbl[] = { XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, {} }; +#endif + +#ifdef CONFIG_PPC_B4420 +static struct serdes_config serdes1_cfg_tbl[] = { + {0x0D, {NONE, NONE, CPRI6, CPRI5, + CPRI4, CPRI3, NONE, NONE} }, + {0x0E, {NONE, NONE, CPRI8, CPRI5, + CPRI4, CPRI3, NONE, NONE} }, + {0x0F, {NONE, NONE, CPRI6, CPRI5, + CPRI4, CPRI3, NONE, NONE} }, + {0x18, {NONE, NONE, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + NONE, NONE, NONE, NONE} }, + {0x1B, {NONE, NONE, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + NONE, NONE, NONE, NONE} }, + {0x1E, {NONE, NONE, AURORA, AURORA, + NONE, NONE, NONE, NONE} }, + {0x21, {NONE, NONE, AURORA, AURORA, + NONE, NONE, NONE, NONE} }, + {0x3E, {NONE, NONE, CPRI6, CPRI5, + CPRI4, CPRI3, NONE, NONE} }, + {} +}; +static struct serdes_config serdes2_cfg_tbl[] = { + {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + NONE, NONE, NONE, NONE} }, + {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + NONE, NONE, NONE, NONE} }, + {0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + AURORA, AURORA, NONE, NONE, NONE, NONE} }, + {0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + AURORA, AURORA, NONE, NONE, NONE, NONE} }, + {0x9A, {PCIE1, PCIE1, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + NONE, NONE, NONE, NONE} }, + {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1, + NONE, NONE, NONE, NONE} }, + {} +}; +#endif + static struct serdes_config *serdes_cfg_tbl[] = { serdes1_cfg_tbl, serdes2_cfg_tbl, -- cgit v1.1