From 0b2e13d9ccbe56e32dc674cf896b2fb55684368c Mon Sep 17 00:00:00 2001 From: Chunhe Lan Date: Mon, 14 Apr 2014 18:42:06 +0800 Subject: powerpc/85xx: Add T4240RDB board support T4240RDB board Specification ---------------------------- Memory subsystem: 6GB DDR3 128MB NOR flash 2GB NAND flash Ethernet: Eight 1G SGMII ports Four 10Gbps SFP+ ports PCIe: Two PCIe slots USB: Two USB2.0 Type A ports SDHC: One SD-card port SATA: One SATA port UART: Dual RJ45 ports Signed-off-by: Chunhe Lan [York Sun: fix CONFIG_SYS_QE_FMAN_FW_ADDR in T4240RDB.h] --- arch/powerpc/cpu/mpc85xx/t4240_ids.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/powerpc/cpu/mpc85xx') diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c index f181315..1a3cb33 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c @@ -64,11 +64,13 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { }; #endif +#ifdef CONFIG_SYS_SRIO struct srio_liodn_id_table srio_liodn_tbl[] = { SET_SRIO_LIODN_BASE(1, 307), SET_SRIO_LIODN_BASE(2, 387), }; int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); +#endif struct liodn_id_table liodn_tbl[] = { #ifdef CONFIG_SYS_DPAA_QBMAN -- cgit v1.1 From 5122dfae5d3cd68e0b6e5e08597df91ba79770aa Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 25 Apr 2014 16:31:22 +0800 Subject: powerpc/85xx: add T4080 SoC support The T4080 SoC is a low-power version of the T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: Shengzhou Liu --- arch/powerpc/cpu/mpc85xx/Makefile | 2 ++ arch/powerpc/cpu/mpc85xx/cpu.c | 24 ++++++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 9 ++++++++- arch/powerpc/cpu/mpc85xx/speed.c | 3 ++- arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 2 +- 5 files changed, 37 insertions(+), 3 deletions(-) (limited to 'arch/powerpc/cpu/mpc85xx') diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 4094785..ad26b43 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_PPC_P5020) += p5020_ids.o obj-$(CONFIG_PPC_P5040) += p5040_ids.o obj-$(CONFIG_PPC_T4240) += t4240_ids.o obj-$(CONFIG_PPC_T4160) += t4240_ids.o +obj-$(CONFIG_PPC_T4080) += t4240_ids.o obj-$(CONFIG_PPC_B4420) += b4860_ids.o obj-$(CONFIG_PPC_B4860) += b4860_ids.o obj-$(CONFIG_PPC_T1040) += t1040_ids.o @@ -88,6 +89,7 @@ obj-$(CONFIG_PPC_P5020) += p5020_serdes.o obj-$(CONFIG_PPC_P5040) += p5040_serdes.o obj-$(CONFIG_PPC_T4240) += t4240_serdes.o obj-$(CONFIG_PPC_T4160) += t4240_serdes.o +obj-$(CONFIG_PPC_T4080) += t4240_serdes.o obj-$(CONFIG_PPC_B4420) += b4860_serdes.o obj-$(CONFIG_PPC_B4860) += b4860_serdes.o obj-$(CONFIG_BSC9132) += bsc9132_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 12e8e10..684d400 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -77,6 +77,30 @@ int checkcpu (void) major = SVR_MAJ(svr); minor = SVR_MIN(svr); +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) + if (SVR_SOC_VER(svr) == SVR_T4080) { + ccsr_rcpm_t *rcpm = + (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); + + setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 || + FSL_CORENET_DEVDISR2_DTSEC1_9); + setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3); + setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3); + + /* It needs SW to disable core4~7 as HW design sake on T4080 */ + for (i = 4; i < 8; i++) + cpu_disable(i); + + /* request core4~7 into PH20 state, prior to entering PCL10 + * state, all cores in cluster should be placed in PH20 state. + */ + setbits_be32(&rcpm->pcph20setr, 0xf0); + + /* put the 2nd cluster into PCL10 state */ + setbits_be32(&rcpm->clpcl10setr, 1 << 1); + } +#endif + if (cpu_numcores() > 1) { #ifndef CONFIG_MP puts("Unicore software on multiprocessor system!!\n" diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 36ef232..7e27464 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -462,10 +462,17 @@ __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); int enable_cluster_l2(void) { int i = 0; - u32 cluster; + u32 cluster, svr = get_svr(); ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); struct ccsr_cluster_l2 __iomem *l2cache; + /* only the L2 of first cluster should be enabled as expected on T4080, + * but there is no EOC in the first cluster as HW sake, so return here + * to skip enabling L2 cache of the 2nd cluster. + */ + if (SVR_SOC_VER(svr) == SVR_T4080) + return 0; + cluster = in_be32(&gur->tp_cluster[i].lower); if (cluster & TP_CLUSTER_EOC) return 0; diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index d516d4e..3236f6a 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -123,7 +123,8 @@ void get_sys_info(sys_info_t *sys_info) * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 * it uses 6. */ -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ + defined(CONFIG_PPC_T4080) if (SVR_MAJ(get_svr()) >= 2) mem_pll_rat *= 2; #endif diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c index ff55e3c..1f99a0a 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c @@ -172,7 +172,7 @@ static const struct serdes_config serdes4_cfg_tbl[] = { {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}}, {} }; -#elif defined(CONFIG_PPC_T4160) +#elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080) static const struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, -- cgit v1.1 From a6c46b994d90f892b608b1b233a04f1fc54f7ab7 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Wed, 30 Apr 2014 19:21:11 +0200 Subject: PPC 85xx QEMU: Don't use HID1 For the QEMU machine type, we can plug in either e500v2, e500mc, e5500 or e6500 style cores into the system. U-boot has to work with all of them. So avoid using HID1 which is not available on e500mc systems to make sure we don't trap on it. Signed-off-by: Alexander Graf --- arch/powerpc/cpu/mpc85xx/start.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/powerpc/cpu/mpc85xx') diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 0e3c86a..0149146 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -314,7 +314,7 @@ l2_disabled: #endif mtspr HID0,r0 -#ifndef CONFIG_E500MC +#if !defined(CONFIG_E500MC) && !defined(CONFIG_QEMU_E500) li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ mfspr r3,PVR andi. r3,r3, 0xff -- cgit v1.1 From f13c9156a9b790fa1991ce41a7f9b7261ff85c33 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Wed, 30 Apr 2014 19:21:12 +0200 Subject: powerpc/mpc85xx: Update TLB CAMs in relocated mode We want to use the TLB mapping helpers in relocated mode as well. These helpers need to have awareness of already occupied TLB entries. We already had them in sync in non-relocated mode, but need to resync them when we move into relocated. Signed-off-by: Alexander Graf --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/powerpc/cpu/mpc85xx') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 7e27464..2656b79 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -895,6 +895,7 @@ skip_l2: } #endif + init_used_tlb_cams(); return 0; } -- cgit v1.1 From 73a56b6e9f3f1cc2412b5b8a75a3c71f48586c94 Mon Sep 17 00:00:00 2001 From: York Sun Date: Wed, 30 Apr 2014 14:43:45 -0700 Subject: powerpc/mpc85xx: Ignore FDT pointer for non-QEMU in cpu_init_early_f() The pointer of device tree comes from r3 for QEMU. This is not the case for normal SoCs out of reset. Having gd->fdt_blob as 0 is important for other functions to detect the non-existence of device tree. Signed-off-by: York Sun CC: Alexander Graf --- arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/powerpc/cpu/mpc85xx') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 998781b..47b712d 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -102,11 +102,13 @@ void cpu_init_early_f(void *fdt) for (i = 0; i < sizeof(gd_t); i++) ((char *)gd)[i] = 0; +#ifdef CONFIG_QEMU_E500 /* * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems, * so we need to populate it before it accesses it. */ gd->fdt_blob = fdt; +#endif mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13); mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M); -- cgit v1.1 From 701e640145474131161de53a407d95d0d2f77082 Mon Sep 17 00:00:00 2001 From: York Sun Date: Wed, 30 Apr 2014 14:43:47 -0700 Subject: powerpc/mpc85xx: Fix boot_flag for calling board_init_f() baord_init_f takes one argument, boot_flag. It has not been used for powerpc, until recently changing to use generic board architecture. The boot flag is added as a return value from cpu_init_f(). Signed-off-by: York Sun CC: Alexander Graf --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 7 ++++--- arch/powerpc/cpu/mpc85xx/spl_minimal.c | 4 +++- arch/powerpc/cpu/mpc85xx/start.S | 2 +- 3 files changed, 8 insertions(+), 5 deletions(-) (limited to 'arch/powerpc/cpu/mpc85xx') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 2656b79..d6cf885 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -368,12 +368,12 @@ void fsl_erratum_a007212_workaround(void) } #endif -void cpu_init_f (void) +ulong cpu_init_f(void) { + ulong flag = 0; extern void m8560_cpm_reset (void); #ifdef CONFIG_SYS_DCSRBAR_PHYS ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); #endif #if defined(CONFIG_SECURE_BOOT) struct law_entry law; @@ -442,13 +442,14 @@ void cpu_init_f (void) #ifdef CONFIG_DEEP_SLEEP /* disable the console if boot from deep sleep */ if (in_be32(&gur->scrtsr[0]) & (1 << 3)) - gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; + flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; #endif #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 fsl_erratum_a007212_workaround(); #endif + return flag; } /* Implement a dummy function for those platforms w/o SERDES */ diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c index 9e4c6c9..cc45f71 100644 --- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c @@ -12,7 +12,7 @@ DECLARE_GLOBAL_DATA_PTR; -void cpu_init_f(void) +ulong cpu_init_f(void) { #ifdef CONFIG_SYS_INIT_L2_ADDR ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; @@ -27,6 +27,8 @@ void cpu_init_f(void) out_be32(&l2cache->l2ctl, (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); #endif + + return 0; } #ifndef CONFIG_SYS_FSL_TBCLK_DIV diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 0149146..d8c9fb6 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1158,7 +1158,7 @@ _start_cont: mtmsr r3 isync - bl cpu_init_f + bl cpu_init_f /* return boot_flag for calling board_init_f */ bl board_init_f isync -- cgit v1.1