From 9e758758491b0d7a71bdf1db8cd860b599d7e657 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:19 +0000 Subject: powerpc/mpc85xx: Add T4240 SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for Freescale T4240 SoC. Feature of T4240 are (incomplete list): 12 dual-threaded e6500 cores built on Power Architecture® technology Arranged as clusters of four cores sharing a 2 MB L2 cache. Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture v2.06-compliant) Three levels of instruction: user, supervisor, and hypervisor 1.5 MB CoreNet Platform Cache (CPC) Hierarchical interconnect fabric CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet end-points 1.6 Tbps coherent read bandwidth Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Memory prefetch engine (PMan) Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: Packet parsing, classification, and distribution (Frame Manager 1.1) Queue management for scheduling, packet sequencing, and congestion management (Queue Manager 1.1) Hardware buffer management for buffer allocation and de-allocation (BMan 1.1) Cryptography acceleration (SEC 5.0) at up to 40 Gbps RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0) 32 SerDes lanes at up to 10.3125 GHz Ethernet interfaces Up to four 10 Gbps Ethernet MACs Up to sixteen 1 Gbps Ethernet MACs Maximum configuration of 4 x 10 GE + 8 x 1 GE High-speed peripheral interfaces Four PCI Express 2.0/3.0 controllers Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support Interlaken look-aside interface for serial TCAM connection Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Four I2C controllers Four 2-pin or two 4-pin UARTs Integrated Flash controller supporting NAND and NOR flash Two eight-channel DMA engines Support for hardware virtualization and partitioning enforcement QorIQ Platform's Trust Architecture 1.1 Signed-off-by: York Sun Signed-off-by: Kumar Gala Signed-off-by: Andy Fleming Signed-off-by: Roy Zang Signed-off-by: Prabhakar Kushwaha Signed-off-by: Shengzhou Liu Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 237 ++++++++++++++++++++++++++++++++ 1 file changed, 237 insertions(+) create mode 100644 arch/powerpc/cpu/mpc85xx/t4240_serdes.c (limited to 'arch/powerpc/cpu/mpc85xx/t4240_serdes.c') diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c new file mode 100644 index 0000000..102defa --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c @@ -0,0 +1,237 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include "fsl_corenet2_serdes.h" + +struct serdes_config { + u32 protocol; + u8 lanes[SRDS_MAX_LANES]; +}; + +static struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, + XAUI_FM1_MAC9, XAUI_FM1_MAC9, + XAUI_FM1_MAC10, XAUI_FM1_MAC10, + XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, + {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, + HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}}, + {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC10, HIGIG_FM1_MAC10, + HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}}, + {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}}, + {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}}, + {38, {NONE, NONE, QSGMII_FM1_B, NONE, + NONE, NONE, QSGMII_FM1_A, NONE}}, + {40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + NONE, NONE, QSGMII_FM1_A, NONE}}, + {46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + NONE, NONE, QSGMII_FM1_A, NONE}}, + {48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9, + NONE, NONE, QSGMII_FM1_A, NONE}}, + {} +}; +static struct serdes_config serdes2_cfg_tbl[] = { + /* SerDes 2 */ + {1, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC10, XAUI_FM2_MAC10, + XAUI_FM2_MAC10, XAUI_FM2_MAC10}}, + {2, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC10, HIGIG_FM2_MAC10, + HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}}, + {4, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC10, HIGIG_FM2_MAC10, + HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}}, + {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {14, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {23, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {38, {NONE, NONE, QSGMII_FM2_B, NONE, + NONE, NONE, QSGMII_FM1_A, NONE}}, + {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, NONE, QSGMII_FM1_A, NONE}}, + {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, NONE, QSGMII_FM1_A, NONE}}, + {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, + NONE, NONE, QSGMII_FM1_A, NONE}}, + {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, + XAUI_FM2_MAC9, XAUI_FM2_MAC9, + NONE, NONE, QSGMII_FM1_A, NONE}}, + {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + NONE, NONE, QSGMII_FM1_A, NONE}}, + {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, + NONE, NONE, QSGMII_FM1_A, NONE}}, + {56, {XFI_FM1_MAC9, XFI_FM1_MAC10, + XFI_FM2_MAC10, XFI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {57, {XFI_FM1_MAC9, XFI_FM1_MAC10, + XFI_FM2_MAC10, XFI_FM2_MAC9, + SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}}, + {} +}; +static struct serdes_config serdes3_cfg_tbl[] = { + /* SerDes 3 */ + {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}}, + {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}}, + {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}}, + {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}}, + {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}}, + {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}}, + {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + PCIE2, PCIE2, PCIE2, PCIE2}}, + {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + PCIE2, PCIE2, PCIE2, PCIE2}}, + {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {} +}; +static struct serdes_config serdes4_cfg_tbl[] = { + /* SerDes 4 */ + {2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}}, + {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}}, + {6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}}, + {8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}}, + {10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA1}}, + {12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA1}}, + {14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}}, + {16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}}, + {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}}, + {} +}; +static struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, + serdes2_cfg_tbl, + serdes3_cfg_tbl, + serdes4_cfg_tbl, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} -- cgit v1.1