From f77329cfcf65e142ffbe930594c4d411c5d66429 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:09 +0000 Subject: powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2 Chassis generation 2 has different mask and shift. Use macro instead of magic numbers. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/speed.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/powerpc/cpu/mpc85xx/speed.c') diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 203f53d..6c2bc34 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -85,7 +85,9 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqDDRBus = sysclk; sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; - mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f; + mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> + FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) + & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; if (mem_pll_rat > 2) sysInfo->freqDDRBus *= mem_pll_rat; else -- cgit v1.1