From 2a44efeb217f1516052555bb66d7de962862bb51 Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Fri, 21 Mar 2014 16:21:45 +0800 Subject: QE/U-QE: Add U-QE support Modify code to adapt to both u-qe and qe. U_QE is a kind of cutted QE. the differences between U_QE and QE 1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs. 2. IMMR: have different immr base addr. 3. iopin: U_QE doesn't need to config iopin. Signed-off-by: Zhao Qiang Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/speed.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/powerpc/cpu/mpc85xx/speed.c') diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index adf09ef..488fd5e 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -336,6 +336,10 @@ void get_sys_info(sys_info_t *sys_info) #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ +#ifdef CONFIG_U_QE + sys_info->freq_qe = sys_info->freq_systembus / 2; +#endif + #else /* CONFIG_FSL_CORENET */ uint plat_ratio, e500_ratio, half_freq_systembus; int i; -- cgit v1.1 From c3678b0937a0543280067fd8e08e6e2d278d90e2 Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 28 Mar 2014 15:07:27 -0700 Subject: powerpc/mpc85xx: Add workaround for erratum A007212 Erratum A007212 for DDR is about a runaway condition for DDR PLL oscilliator. Please refer to erratum document for detail. For this workaround to work, DDR PLL needs to be disabled in RCW. However, u-boot needs to know the expected PLL ratio. We put the ratio in a reserved field RCW[18:23]. U-boot will skip this workaround if DDR PLL ratio is set, or the reserved field is not set. Workaround for erratum A007212 applies to selected versions of B4/T4 SoCs. It is safe to apply the workaround to all versions. It is helpful for upgrading SoC without changing u-boot. In case DDR PLL is disabled by RCW (part of the erratum workaround), we need this u-boot workround to bring up DDR clock. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc85xx/speed.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/powerpc/cpu/mpc85xx/speed.c') diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 488fd5e..35dfb0a 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -107,6 +107,13 @@ void get_sys_info(sys_info_t *sys_info) mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; +#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 + if (mem_pll_rat == 0) { + mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> + FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & + FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; + } +#endif /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 * it uses 6. -- cgit v1.1 From 0c12a1592c49c4fccea1df3eac9bf769aa1bd503 Mon Sep 17 00:00:00 2001 From: vijay rai Date: Tue, 15 Apr 2014 11:34:12 +0530 Subject: powerpc/85xx: Enhance get_sys_info() to check clocking mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode. In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock (100MHz) to the following PLLs: • Platform PLL • Core PLLs • USB PLL • DDR PLL, etc The cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or DIFF_SYSCLK (differential) is selected as the clock input to the chip. get_sys_info has been enhanced to add the diff_sysclk so that the various drivers can be made aware of ths diff sysclk configuration and act accordingly. Other changes: -single_src to ddr_refclk_sel, as it is use for checking ddr reference clock -Removed the print of single_src from get_sys_info as this will be -printed whenever somebody calls get_sys_info which is not appropriate. -Add print of single_src in checkcpu as it is called only once during initialization Signed-off-by: Poonam Aggrwal Signed-off-by: Priyanka Jain Signed-off-by: Vijay Rai Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/speed.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) (limited to 'arch/powerpc/cpu/mpc85xx/speed.c') diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 35dfb0a..2d6c668 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -74,28 +74,33 @@ void get_sys_info(sys_info_t *sys_info) uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; unsigned long sysclk = CONFIG_SYS_CLK_FREQ; uint mem_pll_rat; -#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK - uint single_src; -#endif sys_info->freq_systembus = sysclk; #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK + uint ddr_refclk_sel; + unsigned int porsr1_sys_clk; + porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT + & FSL_DCFG_PORSR1_SYSCLK_MASK; + if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF) + sys_info->diff_sysclk = 1; + else + sys_info->diff_sysclk = 0; + /* * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS * are driven by separate DDR Refclock or single source * differential clock. */ - single_src = (in_be32(&gur->rcwsr[5]) >> + ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >> FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) & FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK; /* - * For single source clocking, both ddrclock and syclock + * For single source clocking, both ddrclock and sysclock * are driven by differential sysclock. */ - if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) { - printf("Single Source Clock Configuration\n"); + if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ; - } else + else #endif #ifdef CONFIG_DDR_CLK_FREQ sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; -- cgit v1.1 From b33bd8cd4b7627f64698c6f26739e0c4597bdfbc Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Mon, 21 Apr 2014 10:47:41 +0530 Subject: powerpc/mpc85xx:Update FM1 clock select and shift for B4420 B4420 is a personality of B4860. It should have same FM1_CLK_SEK and FM1_CLK_SHIFT as B4860 Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/speed.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/powerpc/cpu/mpc85xx/speed.c') diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 2d6c668..d516d4e 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -163,8 +163,8 @@ void get_sys_info(sys_info_t *sys_info) sys_info->freq_processor[cpu] = freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; } -#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080) || \ - defined(CONFIG_PPC_T2081) +#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \ + defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define FM1_CLK_SEL 0xe0000000 #define FM1_CLK_SHIFT 29 #else -- cgit v1.1