From 5e23ab0a31f19f894fe46bfab6f68b8bcfa10cf6 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 7 May 2012 07:26:47 +0000 Subject: powerpc/mpc85xx: Workaround for erratum CPU_A011 Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0. It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the same workaround as erratum CPU22. Rearrange registers usage in assembly code to avoid accidental overwriting. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'arch/powerpc/cpu/mpc85xx/cpu_init.c') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index d7e80fc..fc6c287 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -308,8 +308,14 @@ int cpu_init_r(void) volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; #endif -#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) - if (SVR_MAJ(svr) < 3) { +#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ + defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) + /* + * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1 + */ + if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3) { flush_dcache(); mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); sync(); -- cgit v1.1