From 133fbfa9e6a81a59ab2d6848f0b111ebb2567a8a Mon Sep 17 00:00:00 2001
From: York Sun <yorksun@freescale.com>
Date: Mon, 16 Sep 2013 12:49:31 -0700
Subject: powerpc/mpc85xx: Add workaround for erratum A006379

Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default
value after POR. The workaround is to set this field before enabling
CPC to 0x1e.

Erratum A006379 applies to
	T4240 rev 1.0
	B4860 rev 1.0, 2.0

Signed-off-by: York Sun <yorksun@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/cpu_init.c | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'arch/powerpc/cpu/mpc85xx/cpu_init.c')

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index a8107a9..b31efb7 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -19,6 +19,7 @@
 #include <asm/io.h>
 #include <asm/cache.h>
 #include <asm/mmu.h>
+#include <asm/fsl_errata.h>
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_srio.h>
@@ -160,6 +161,12 @@ static void enable_cpc(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
 		setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006379
+		if (has_erratum_a006379()) {
+			setbits_be32(&cpc->cpchdbcr0,
+				     CPC_HDBCR0_SPLRU_LEVEL_EN);
+		}
+#endif
 
 		out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
 		/* Read back to sync write */
-- 
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