From beba93ed05d8cea795bad895b6cc1490004fc242 Mon Sep 17 00:00:00 2001 From: Dipen Dudhat Date: Wed, 19 Jan 2011 12:46:27 +0530 Subject: powerpc/85xx: Protect all LBC code with CONFIG_FSL_LBC Future SoC (like the P1010) replace the LBC controller with the new IFC (Integrated Flash Controller) so ensure we properly protect code that is related to the LBC. Signed-off-by: Dipen Dudhat Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/cpu.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'arch/powerpc/cpu/mpc85xx/cpu.c') diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 4ef9be1..1aad2ba 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2004,2007-2010 Freescale Semiconductor, Inc. + * Copyright 2004,2007-2011 Freescale Semiconductor, Inc. * (C) Copyright 2002, 2003 Motorola Inc. * Xianghua Xiao (X.Xiao@motorola.com) * @@ -166,12 +166,14 @@ int checkcpu (void) } #endif +#if defined(CONFIG_FSL_LBC) if (sysinfo.freqLocalBus > LCRR_CLKDIV) { printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); } else { printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", sysinfo.freqLocalBus); } +#endif #ifdef CONFIG_CPM2 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); @@ -284,7 +286,10 @@ void mpc85xx_reginfo(void) { print_tlbcam(); print_laws(); +#if defined(CONFIG_FSL_LBC) print_lbc_regs(); +#endif + } /* Common ddr init for non-corenet fsl 85xx platforms */ @@ -330,8 +335,10 @@ phys_size_t initdram(int board_type) ddr_enable_ecc(dram_size); #endif +#if defined(CONFIG_FSL_LBC) /* Some boards also have sdram on the lbc */ lbc_sdram_init(); +#endif puts("DDR: "); return dram_size; -- cgit v1.1