From 2b8bcc5a2fca54648ece966902b8230de971b609 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Thu, 29 Jan 2015 01:27:56 +0000 Subject: MIPS: avoid .set ISA for cache operations As a step towards unifying the cache maintenance code for mips32 & mips64 CPUs, stop using ".set " directives in the more developed mips32 version of the code. Instead, when present make use of the GCC builtin for emitting a cache instruction. When not present, simply don't bother with the .set directives since U-boot always builds with -march=mips32 or higher anyway. Signed-off-by: Paul Burton Cc: Daniel Schwierzeck --- arch/mips/include/asm/cacheops.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/mips/include/asm') diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h index 6464250..75ec380 100644 --- a/arch/mips/include/asm/cacheops.h +++ b/arch/mips/include/asm/cacheops.h @@ -11,6 +11,19 @@ #ifndef __ASM_CACHEOPS_H #define __ASM_CACHEOPS_H +#ifndef __ASSEMBLY__ + +static inline void mips_cache(int op, const volatile void *addr) +{ +#ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE + __builtin_mips_cache(op, addr); +#else + __asm__ __volatile__("cache %0, %1" : : "i"(op), "R"(addr)) +#endif +} + +#endif /* !__ASSEMBLY__ */ + /* * Cache Operations available on all MIPS processors with R4000-style caches */ -- cgit v1.1 From ba21a453a58fc02b890f4064b293b1cb09fe7484 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Thu, 29 Jan 2015 10:38:20 +0000 Subject: malta: IDE support This patch adds IDE support to the MIPS Malta board. The IDE controller is enabled after probing the PCI bus and otherwise just makes use of U-boot generic IDE support. Signed-off-by: Paul Burton Cc: Daniel Schwierzeck --- arch/mips/include/asm/malta.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/mips/include/asm') diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h index 9e7c045..d9ffc15 100644 --- a/arch/mips/include/asm/malta.h +++ b/arch/mips/include/asm/malta.h @@ -64,4 +64,9 @@ #define PCI_CFG_PIIX4_GENCFG_SERIRQ (1 << 16) +#define PCI_CFG_PIIX4_IDETIM_PRI 0x40 +#define PCI_CFG_PIIX4_IDETIM_SEC 0x42 + +#define PCI_CFG_PIIX4_IDETIM_IDE (1 << 15) + #endif /* _MIPS_ASM_MALTA_H */ -- cgit v1.1