From ee8b1e29597bcf18bfebd6fd8eccc8e245046352 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Thu, 13 Jun 2013 12:59:35 +0200 Subject: MIPS: mips32/cache.S: store cache line size in t8 register Synchronize the code with mips64/cache.S, in order to allow further unifications. Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck --- arch/mips/cpu/mips32/cache.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/mips/cpu') diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index fc13d3f..d3f156e 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -128,7 +128,7 @@ NESTED(mips_cache_reset, 0, ra) move RA, ra li t2, CONFIG_SYS_ICACHE_SIZE li t3, CONFIG_SYS_DCACHE_SIZE - li t4, CONFIG_SYS_CACHELINE_SIZE + li t8, CONFIG_SYS_CACHELINE_SIZE li v0, MIPS_MAX_CACHE_SIZE @@ -155,7 +155,7 @@ NESTED(mips_cache_reset, 0, ra) * Initialize the I-cache first, */ move a1, t2 - move a2, t4 + move a2, t8 PTR_LA t7, mips_init_icache jalr t7 @@ -163,7 +163,7 @@ NESTED(mips_cache_reset, 0, ra) * then initialize D-cache. */ move a1, t3 - move a2, t4 + move a2, t8 PTR_LA t7, mips_init_dcache jalr t7 -- cgit v1.1