From af3971f81ac0fc344461cf86af682ecf1ebe18a8 Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Sun, 14 Feb 2016 18:52:57 +0100 Subject: MIPS: make inclusion of ROM exception vectors configurable This adds a compile time option to include code for static exception vectors. Static exception vectors are only needed, when the U-Boot entry point is equal to the CPU reset exception vector address. For instance this is the case when U-Boot is used as ROM in Qemu or booted from parallel NOR flash. When U-Boot is booted from RAM (e.g. loaded there by SPL), the exception vectors need to be setup dynamically, which is done in follow-up commits. Signed-off-by: Daniel Schwierzeck --- arch/mips/cpu/start.S | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'arch/mips/cpu') diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index 3f0fc12..108d2df 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -57,7 +57,6 @@ ENTRY(_start) b reset nop - .org 0x10 #if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG) /* * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to @@ -66,16 +65,20 @@ ENTRY(_start) * initial configuration for that EBU in order to access the flash * device with correct parameters. This config option is board-specific. */ + .org 0x10 .word CONFIG_SYS_XWAY_EBU_BOOTCFG .word 0x0 -#elif defined(CONFIG_MALTA) +#endif +#if defined(CONFIG_MALTA) /* * Linux expects the Board ID here. */ + .org 0x10 .word 0x00000420 # 0x420 (Malta Board with CoreLV) .word 0x00000000 #endif +#if defined(CONFIG_ROM_EXCEPTION_VECTORS) .org 0x200 /* TLB refill, 32 bit task */ 1: b 1b @@ -106,7 +109,9 @@ ENTRY(_start) 1: b 1b nop - .align 4 + .org 0x500 +#endif + reset: #if __mips_isa_rev >= 6 mfc0 t0, CP0_CONFIG, 5 -- cgit v1.1