From 8cb4817d0f076605c5126f0925f6c7fdb0461bf6 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Wed, 21 Sep 2016 11:18:48 +0100 Subject: MIPS: Probe cache line sizes once during boot Rather than probing the cache line sizes on every call of any cache maintenance function, probe them once during boot & store the values in the global data structure for later use. This will reduce the overhead of the cache maintenance functions, which isn't a big deal yet but becomes more important once L2 caches which may expose their properties via coprocessor 2 or the CM are supported. Signed-off-by: Paul Burton --- arch/mips/cpu/cpu.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/mips/cpu/cpu.c') diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/cpu.c index 391feb3..1b919ed 100644 --- a/arch/mips/cpu/cpu.c +++ b/arch/mips/cpu/cpu.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -35,3 +36,9 @@ void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) write_c0_index(index); tlb_write_indexed(); } + +int arch_cpu_init(void) +{ + mips_cache_probe(); + return 0; +} -- cgit v1.1