From fce3f6e59f6ae5a171bbb6581420712c4aaa14c3 Mon Sep 17 00:00:00 2001
From: Ye Li <ye.li@nxp.com>
Date: Wed, 15 Feb 2017 17:38:55 +0800
Subject: MLK-13929-5 mx7ulp: Update clock and SoC functions for video

Add the clocks functions for enabling LCDIF and DSI clocks.
Also add the arch_preboot_os to disable the video before enter into
the kernel.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit a783799017a929f9918c9c5981fe3a7a25cd8125)
---
 arch/arm/cpu/armv7/mx7ulp/clock.c        | 77 ++++++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/mx7ulp/soc.c          |  8 ++++
 arch/arm/include/asm/arch-mx7ulp/clock.h |  3 ++
 3 files changed, 88 insertions(+)

(limited to 'arch/arm')

diff --git a/arch/arm/cpu/armv7/mx7ulp/clock.c b/arch/arm/cpu/armv7/mx7ulp/clock.c
index 88896dc..d0453d3 100644
--- a/arch/arm/cpu/armv7/mx7ulp/clock.c
+++ b/arch/arm/cpu/armv7/mx7ulp/clock.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -323,6 +324,82 @@ void hab_caam_clock_enable(unsigned char enable)
 }
 #endif
 
+void enable_mipi_dsi_clk(unsigned char enable)
+{
+	if (enable) {
+		pcc_clock_enable(PER_CLK_DSI, false);
+
+		/* mipi dsi escape clock range is 40-80Mhz, we expect to set it to about 60 Mhz
+		 * To avoid PCD issue, we select parent clock with lowest frequency
+		 * NIC1_CLK = 1584000khz, frac = 1, div = 5,  output = 63.360Mhz
+		 */
+		pcc_clock_sel(PER_CLK_DSI, SCG_NIC1_CLK);
+		pcc_clock_div_config(PER_CLK_DSI, 1, 5);
+
+		pcc_clock_enable(PER_CLK_DSI, true);
+	} else {
+		pcc_clock_enable(PER_CLK_DSI, false);
+	}
+}
+
+void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq_in_khz)
+{
+	/* Scan the parent clock to find best fit clock, which should generate actual frequence >= freq */
+	u8 pcd, best_pcd = 0;
+	u32 parent, frac, rate, parent_rate;
+	u32 best_parent = 0, best_frac = 0, best = 0;
+
+	static enum scg_clk clksrc_plat[] = {
+		SCG_NIC1_BUS_CLK,
+		SCG_NIC1_CLK,
+		SCG_DDR_CLK,
+		SCG_APLL_PFD2_CLK,
+		SCG_APLL_PFD1_CLK,
+		SCG_APLL_PFD0_CLK,
+		USB_PLL_OUT,
+	};
+
+	pcc_clock_enable(PER_CLK_LCDIF, false);
+
+	for (parent = 0; parent < ARRAY_SIZE(clksrc_plat); parent++) {
+		parent_rate = scg_clk_get_rate(clksrc_plat[parent]);
+		if (!parent_rate)
+			continue;
+
+		parent_rate = parent_rate / 1000; /* Change to khz*/
+
+		for (pcd = 0; pcd < 8; pcd++) {
+			for (frac = 0; frac < 2; frac++) {
+				if (pcd == 0 && frac == 1)
+					continue;
+
+				rate = parent_rate * (frac + 1) / (pcd + 1);
+				if (rate < freq_in_khz)
+					continue;
+
+				if (best == 0 || rate < best) {
+					best = rate;
+					best_parent = parent;
+					best_frac = frac;
+					best_pcd = pcd;
+				}
+			}
+		}
+	}
+
+	if (best == 0) {
+		printf("Can't find parent clock for LCDIF, target freq: %u\n", freq_in_khz);
+		return;
+	}
+
+	debug("LCD target rate %ukhz, best rate %ukhz, frac %u, pcd %u, best_parent %u\n",
+	      freq_in_khz, best, best_frac, best_pcd, best_parent);
+
+	pcc_clock_sel(PER_CLK_LCDIF, clksrc_plat[best_parent]);
+	pcc_clock_div_config(PER_CLK_LCDIF, best_frac, best_pcd + 1);
+	pcc_clock_enable(PER_CLK_LCDIF, true);
+}
+
 /*
  * Dump some core clockes.
  */
diff --git a/arch/arm/cpu/armv7/mx7ulp/soc.c b/arch/arm/cpu/armv7/mx7ulp/soc.c
index cba65b5..231759c 100644
--- a/arch/arm/cpu/armv7/mx7ulp/soc.c
+++ b/arch/arm/cpu/armv7/mx7ulp/soc.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -271,6 +272,13 @@ static char *get_reset_cause(char *ret)
 	return ret;
 }
 
+void arch_preboot_os(void)
+{
+#if defined(CONFIG_VIDEO_MXS)
+	lcdif_power_down();
+#endif
+}
+
 #ifdef CONFIG_ENV_IS_IN_MMC
 __weak int board_mmc_get_env_dev(int devno)
 {
diff --git a/arch/arm/include/asm/arch-mx7ulp/clock.h b/arch/arm/include/asm/arch-mx7ulp/clock.h
index ddb9d1f..0bebe95 100644
--- a/arch/arm/include/asm/arch-mx7ulp/clock.h
+++ b/arch/arm/include/asm/arch-mx7ulp/clock.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -37,6 +38,8 @@ void enable_ocotp_clk(unsigned char enable);
 #ifdef CONFIG_USB_EHCI
 void enable_usboh3_clk(unsigned char enable);
 #endif
+void enable_mipi_dsi_clk(unsigned char enable);
+void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq_in_khz);
 void init_clk_usdhc(u32 index);
 void clock_init(void);
 void hab_caam_clock_enable(unsigned char enable);
-- 
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