From 0f5141e9c57e96de11642a5baa7ffbb17aecc761 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 12 Jun 2013 22:24:45 -0500 Subject: ARM: move interrupt_init to before relocation interrupt_init also sets up the abort stack, but is not setup before relocation. So any aborts during relocation will hang and not print out any useful information. Fix this by moving the interrupt_init to after the stack setup in board_init_f. Signed-off-by: Rob Herring --- arch/arm/lib/board.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 09ab4ad..c90843e 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -447,6 +447,7 @@ void board_init_f(ulong bootflag) addr_sp += 128; /* leave 32 words for abort-stack */ gd->irq_sp = addr_sp; #endif + interrupt_init(); debug("New Stack Pointer is: %08lx\n", addr_sp); @@ -648,8 +649,6 @@ void board_init_r(gd_t *id, ulong dest_addr) misc_init_r(); #endif - /* set up exceptions */ - interrupt_init(); /* enable exceptions */ enable_interrupts(); -- cgit v1.1 From ec0e413f934fd70968b4ca0daa530cbe8f5cdb4f Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 12 Jun 2013 22:24:48 -0500 Subject: ARM: highbank: fix get_tbclk value to timer rate get_tbclk should return the timer's frequency, not CONFIG_SYS_HZ. Signed-off-by: Rob Herring --- arch/arm/cpu/armv7/highbank/timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/highbank/timer.c b/arch/arm/cpu/armv7/highbank/timer.c index 0f985e2..da33d3c 100644 --- a/arch/arm/cpu/armv7/highbank/timer.c +++ b/arch/arm/cpu/armv7/highbank/timer.c @@ -124,5 +124,5 @@ ulong get_timer_masked(void) ulong get_tbclk(void) { - return CONFIG_SYS_HZ; + return SYSTIMER_RATE; } -- cgit v1.1 From 714d1f5da53101ec44ab9c3d10564462b102bd8f Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 12 Jun 2013 22:24:49 -0500 Subject: ARM: highbank: set timer prescaler to 256 The 150MHz clock rate gives u-boot time functions problems and there's no benefit to a fast clock, so lower the rate. Signed-off-by: Rob Herring --- arch/arm/cpu/armv7/highbank/timer.c | 6 ++++-- arch/arm/include/asm/arch-armv7/systimer.h | 2 ++ 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/highbank/timer.c b/arch/arm/cpu/armv7/highbank/timer.c index da33d3c..d93de1e 100644 --- a/arch/arm/cpu/armv7/highbank/timer.c +++ b/arch/arm/cpu/armv7/highbank/timer.c @@ -26,7 +26,7 @@ #undef SYSTIMER_BASE #define SYSTIMER_BASE 0xFFF34000 /* Timer 0 and 1 base */ -#define SYSTIMER_RATE 150000000 +#define SYSTIMER_RATE (150000000 / 256) static ulong timestamp; static ulong lastinc; @@ -40,9 +40,11 @@ int timer_init(void) /* * Setup timer0 */ + writel(0, &systimer_base->timer0control); writel(SYSTIMER_RELOAD, &systimer_base->timer0load); writel(SYSTIMER_RELOAD, &systimer_base->timer0value); - writel(SYSTIMER_EN | SYSTIMER_32BIT, &systimer_base->timer0control); + writel(SYSTIMER_EN | SYSTIMER_32BIT | SYSTIMER_PRESC_256, + &systimer_base->timer0control); reset_timer_masked(); diff --git a/arch/arm/include/asm/arch-armv7/systimer.h b/arch/arm/include/asm/arch-armv7/systimer.h index e745e37..08125f7 100644 --- a/arch/arm/include/asm/arch-armv7/systimer.h +++ b/arch/arm/include/asm/arch-armv7/systimer.h @@ -30,6 +30,8 @@ #define SYSTIMER_RELOAD 0xFFFFFFFF #define SYSTIMER_EN (1 << 7) #define SYSTIMER_32BIT (1 << 1) +#define SYSTIMER_PRESC_16 (1 << 2) +#define SYSTIMER_PRESC_256 (1 << 3) struct systimer { u32 timer0load; /* 0x00 */ -- cgit v1.1 From 0f7cf3803f59b0c8d94aa52cc8827aab28591eb4 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 12 Jun 2013 22:24:50 -0500 Subject: ARM: highbank: avoid bss write in timer_init The timer_init function is called before relocation and writes to bss data were corrupting relocation data. Fix this by removing the call to reset_timer_masked. The initial timer count should be 0 or near 0 anyway, so initializing the variables are not needed. Signed-off-by: Rob Herring --- arch/arm/cpu/armv7/highbank/timer.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/highbank/timer.c b/arch/arm/cpu/armv7/highbank/timer.c index d93de1e..832c012 100644 --- a/arch/arm/cpu/armv7/highbank/timer.c +++ b/arch/arm/cpu/armv7/highbank/timer.c @@ -46,8 +46,6 @@ int timer_init(void) writel(SYSTIMER_EN | SYSTIMER_32BIT | SYSTIMER_PRESC_256, &systimer_base->timer0control); - reset_timer_masked(); - return 0; } -- cgit v1.1 From bf0e86606df37e3344b14d12e58aa8799a15fe37 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 14 Jun 2013 10:55:00 +0200 Subject: arm: omap3: spl: Fix problem with 8bit NAND devices Currently in OMAP3 SPL, the GPMC for NAND is configured for 16bit access. This patch adds support for 8bit NAND devices as well. Signed-off-by: Stefan Roese Cc: Tom Rini --- arch/arm/cpu/armv7/omap3/mem.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c index 1832aff..e649409 100644 --- a/arch/arm/cpu/armv7/omap3/mem.c +++ b/arch/arm/cpu/armv7/omap3/mem.c @@ -21,6 +21,17 @@ struct gpmc *gpmc_cfg; #if defined(CONFIG_CMD_NAND) +#if defined(GPMC_NAND_ECC_SP_x8_LAYOUT) || defined(GPMC_NAND_ECC_LP_x8_LAYOUT) +static const u32 gpmc_m_nand[GPMC_MAX_REG] = { + SMNAND_GPMC_CONFIG1, + SMNAND_GPMC_CONFIG2, + SMNAND_GPMC_CONFIG3, + SMNAND_GPMC_CONFIG4, + SMNAND_GPMC_CONFIG5, + SMNAND_GPMC_CONFIG6, + 0, +}; +#else static const u32 gpmc_m_nand[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, M_NAND_GPMC_CONFIG2, @@ -29,6 +40,7 @@ static const u32 gpmc_m_nand[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG5, M_NAND_GPMC_CONFIG6, 0 }; +#endif #endif /* CONFIG_CMD_NAND */ #if defined(CONFIG_CMD_ONENAND) -- cgit v1.1 From c4ec281822562de4ac5850d3b623412be8b721a7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Mon, 8 Jul 2013 15:21:34 +0200 Subject: omap3/sys_info: fix printout of OMAP36XX L3 freqency MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The OMAP36xx/OMAP37xx family uses L3 frequency of 200MHz instead of 165MHz used by OMAP34xx/OMAP35xx. Also fix checkpatch warning about alignment. Signed-off-by: Andreas Bießmann --- arch/arm/cpu/armv7/omap3/sys_info.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c index 9a3303f..258786b 100644 --- a/arch/arm/cpu/armv7/omap3/sys_info.c +++ b/arch/arm/cpu/armv7/omap3/sys_info.c @@ -342,9 +342,9 @@ int print_cpuinfo (void) } if (CPU_OMAP36XX == get_cpu_family()) - printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n", - cpu_family_s, cpu_s, sec_s, - rev_s_37xx[get_cpu_rev()], max_clk); + printf("%s%s-%s ES%s, CPU-OPP2, L3-200MHz, Max CPU Clock %s\n", + cpu_family_s, cpu_s, sec_s, + rev_s_37xx[get_cpu_rev()], max_clk); else printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n", cpu_family_s, cpu_s, sec_s, -- cgit v1.1 From 65e9d56fb9ce9cfd7ffff7afaa6b7de50e400e06 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Mon, 8 Jul 2013 16:04:39 +0530 Subject: ARM: DRA7xx: Lock DPLL_GMAC Locking DPLL_GMAC [mugunthanvnm@ti.com:Configure only if CPSW is selected] Signed-off-by: Lokesh Vutla Signed-off-by: Mugunthan V N --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 18 ++++++++++++++++++ arch/arm/cpu/armv7/omap5/hw_data.c | 11 +++++++++++ arch/arm/cpu/armv7/omap5/prcm-regs.c | 1 + arch/arm/include/asm/omap_common.h | 2 ++ 4 files changed, 32 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 20fa678..7580594 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -196,6 +196,18 @@ static const struct dpll_params *get_ddr_dpll_params return &dpll_data->ddr[sysclk_ind]; } +#ifdef CONFIG_DRIVER_TI_CPSW +static const struct dpll_params *get_gmac_dpll_params + (struct dplls const *dpll_data) +{ + u32 sysclk_ind = get_sys_clk_index(); + + if (!dpll_data->gmac) + return NULL; + return &dpll_data->gmac[sysclk_ind]; +} +#endif + static void do_setup_dpll(u32 const base, const struct dpll_params *params, u8 lock, char *dpll) { @@ -398,6 +410,12 @@ static void setup_dplls(void) params = get_ddr_dpll_params(*dplls_data); do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy, params, DPLL_LOCK, "ddr"); + +#ifdef CONFIG_DRIVER_TI_CPSW + params = get_gmac_dpll_params(*dplls_data); + do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params, + DPLL_LOCK, "gmac"); +#endif } #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index ea3554d..c21674a 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -247,6 +247,16 @@ static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = { {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ }; +static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = { + {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */ + {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */ + {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */ +}; + struct dplls omap5_dplls_es1 = { .mpu = mpu_dpll_params_800mhz, .core = core_dpll_params_2128mhz_ddr532, @@ -283,6 +293,7 @@ struct dplls dra7xx_dplls = { .iva = iva_dpll_params_2330mhz_dra7xx, .usb = usb_dpll_params_1920mhz, .ddr = ddr_dpll_params_2128mhz, + .gmac = gmac_dpll_params_2000mhz, }; struct pmic_data palmas = { diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 54d8c2b..b0416ad 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -798,6 +798,7 @@ struct prcm_regs const dra7xx_prcm = { .cm_ssc_deltamstep_dpll_ddrphy = 0x4a00522c, .cm_clkmode_dpll_dsp = 0x4a005234, .cm_shadow_freq_config1 = 0x4a005260, + .cm_clkmode_dpll_gmac = 0x4a0052a8, /* cm1.mpu */ .cm_mpu_mpu_clkctrl = 0x4a005320, diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index b56e949..ad27db2 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -73,6 +73,7 @@ struct prcm_regs { u32 cm_ssc_deltamstep_dpll_ddrphy; u32 cm_clkmode_dpll_dsp; u32 cm_shadow_freq_config1; + u32 cm_clkmode_dpll_gmac; u32 cm_mpu_mpu_clkctrl; /* cm1.dsp */ @@ -483,6 +484,7 @@ struct dplls { const struct dpll_params *iva; const struct dpll_params *usb; const struct dpll_params *ddr; + const struct dpll_params *gmac; }; struct pmic_data { -- cgit v1.1 From f986d9720836433ded29f06c8f5aed462bd20924 Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Mon, 8 Jul 2013 16:04:40 +0530 Subject: ARM: DRA7xx: Enable GMAC clock control Enabling CPSW module by enabling GMAC clock control Signed-off-by: Mugunthan V N --- arch/arm/cpu/armv7/omap5/hw_data.c | 7 ++++++- arch/arm/cpu/armv7/omap5/prcm-regs.c | 2 ++ arch/arm/include/asm/omap_common.h | 4 ++++ 3 files changed, 12 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index c21674a..fbbc486 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -393,6 +393,9 @@ void enable_basic_clocks(void) (*prcm)->cm_l3init_clkstctrl, (*prcm)->cm_memif_clkstctrl, (*prcm)->cm_l4cfg_clkstctrl, +#ifdef CONFIG_DRIVER_TI_CPSW + (*prcm)->cm_gmac_clkstctrl, +#endif 0 }; @@ -420,6 +423,9 @@ void enable_basic_clocks(void) (*prcm)->cm_wkup_wdtimer2_clkctrl, (*prcm)->cm_l4per_uart3_clkctrl, (*prcm)->cm_l4per_i2c1_clkctrl, +#ifdef CONFIG_DRIVER_TI_CPSW + (*prcm)->cm_gmac_gmac_clkctrl, +#endif 0 }; @@ -476,7 +482,6 @@ void enable_basic_uboot_clocks(void) (*prcm)->cm_l3init_fsusb_clkctrl, 0 }; - do_enable_clocks(clk_domains_essential, clk_modules_hw_auto_essential, clk_modules_explicit_en_essential, diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index b0416ad..9dfeff9 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -896,6 +896,8 @@ struct prcm_regs const dra7xx_prcm = { .cm_l3init_hsusbhost_clkctrl = 0x4a009340, .cm_l3init_hsusbotg_clkctrl = 0x4a009348, .cm_l3init_hsusbtll_clkctrl = 0x4a009350, + .cm_gmac_clkstctrl = 0x4a0093c0, + .cm_gmac_gmac_clkctrl = 0x4a0093d0, .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, /* cm2.l4per */ diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index ad27db2..2c5bd1a 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -340,6 +340,10 @@ struct prcm_regs { /* SCRM stuff, used by some boards */ u32 scrm_auxclk0; u32 scrm_auxclk1; + + /* GMAC Clk Ctrl */ + u32 cm_gmac_gmac_clkctrl; + u32 cm_gmac_clkstctrl; }; struct omap_sys_ctrl_regs { -- cgit v1.1 From b1e26e3bfb1d53d4fd713a2a5f11b7ddf2bcaeec Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Mon, 8 Jul 2013 16:04:41 +0530 Subject: ARM: DRA7xx: Add CPSW support to DRA7xx EVM Adding support for CPSW Ethernet support found in DRA7xx EVM Signed-off-by: Mugunthan V N --- arch/arm/cpu/armv7/omap5/prcm-regs.c | 4 ++++ arch/arm/include/asm/arch-omap5/cpu.h | 6 ++++++ arch/arm/include/asm/arch-omap5/omap.h | 26 ++++++++++++++++++++++++++ arch/arm/include/asm/omap_common.h | 4 ++++ 4 files changed, 40 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 9dfeff9..579818d 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -378,6 +378,10 @@ struct omap_sys_ctrl_regs const omap5_ctrl = { struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_status = 0x4A002134, + .control_core_mac_id_0_lo = 0x4A002514, + .control_core_mac_id_0_hi = 0x4A002518, + .control_core_mac_id_1_lo = 0x4A00251C, + .control_core_mac_id_1_hi = 0x4A002520, .control_core_mmr_lock1 = 0x4A002540, .control_core_mmr_lock2 = 0x4A002544, .control_core_mmr_lock3 = 0x4A002548, diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h index 3de5984..fb5a568 100644 --- a/arch/arm/include/asm/arch-omap5/cpu.h +++ b/arch/arm/include/asm/arch-omap5/cpu.h @@ -99,6 +99,8 @@ struct watchdog { #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ +#define BIT(x) (1 << (x)) + #define WD_UNLOCK1 0xAAAA #define WD_UNLOCK2 0x5555 @@ -158,4 +160,8 @@ struct watchdog { #define PRM_RSTST (PRM_DEVICE_BASE + 0x4) #define PRM_RSTST_WARM_RESET_MASK 0x7FEA +/* DRA7XX CPSW Config space */ +#define CPSW_BASE 0x48484000 +#define CPSW_MDIO_BASE 0x48485000 + #endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index d08fcff..597c692 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -192,6 +192,27 @@ struct s32ktimer { #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10) #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0) +/* IO Delay module defines */ +#define CFG_IO_DELAY_BASE 0x4844A000 +#define CFG_IO_DELAY_LOCK (CFG_IO_DELAY_BASE + 0x02C) + +/* CPSW IO Delay registers*/ +#define CFG_RGMII0_TXCTL (CFG_IO_DELAY_BASE + 0x74C) +#define CFG_RGMII0_TXD0 (CFG_IO_DELAY_BASE + 0x758) +#define CFG_RGMII0_TXD1 (CFG_IO_DELAY_BASE + 0x764) +#define CFG_RGMII0_TXD2 (CFG_IO_DELAY_BASE + 0x770) +#define CFG_RGMII0_TXD3 (CFG_IO_DELAY_BASE + 0x77C) +#define CFG_VIN2A_D13 (CFG_IO_DELAY_BASE + 0xA7C) +#define CFG_VIN2A_D17 (CFG_IO_DELAY_BASE + 0xAAC) +#define CFG_VIN2A_D16 (CFG_IO_DELAY_BASE + 0xAA0) +#define CFG_VIN2A_D15 (CFG_IO_DELAY_BASE + 0xA94) +#define CFG_VIN2A_D14 (CFG_IO_DELAY_BASE + 0xA88) + +#define CFG_IO_DELAY_UNLOCK_KEY 0x0000AAAA +#define CFG_IO_DELAY_LOCK_KEY 0x0000AAAB +#define CFG_IO_DELAY_ACCESS_PATTERN 0x00029000 +#define CFG_IO_DELAY_LOCK_MASK 0x400 + #ifndef __ASSEMBLY__ struct srcomp_params { s8 divide_factor; @@ -208,5 +229,10 @@ struct ctrl_ioregs { u32 ctrl_emif_sdram_config_ext; u32 ctrl_ddr_ctrl_ext_0; }; + +struct io_delay { + u32 addr; + u32 dly; +}; #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 2c5bd1a..66f416f 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -348,6 +348,10 @@ struct prcm_regs { struct omap_sys_ctrl_regs { u32 control_status; + u32 control_core_mac_id_0_lo; + u32 control_core_mac_id_0_hi; + u32 control_core_mac_id_1_lo; + u32 control_core_mac_id_1_hi; u32 control_std_fuse_opp_vdd_mpu_2; u32 control_core_mmr_lock1; u32 control_core_mmr_lock2; -- cgit v1.1 From 5ea7f0e328c19542ce96d8242125b51b3dbca86b Mon Sep 17 00:00:00 2001 From: Pardeep Kumar Singla Date: Thu, 25 Jul 2013 12:12:13 -0500 Subject: mx6: Factor out common HDMI setup code Instead of duplicating HDMI setup code for every mx6 board, factor out the common code Signed-off-by: Pardeep Kumar Singla Acked-By: Eric Nelson --- arch/arm/cpu/armv7/mx6/clock.c | 8 ++++++ arch/arm/cpu/armv7/mx6/soc.c | 43 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/clock.h | 2 +- arch/arm/include/asm/arch-mx6/mxc_hdmi.h | 5 ++++ 4 files changed, 57 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 3c0d908..ce063ae 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -468,6 +468,14 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +void enable_ipu_clock(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int reg; + reg = readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET; + writel(reg, &mxc_ccm->CCGR3); +} /***************************************************/ U_BOOT_CMD( diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index fc436fb..a79369f 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -32,6 +32,8 @@ #include #include #include +#include +#include struct scu_regs { u32 ctrl; @@ -228,3 +230,44 @@ const struct boot_mode soc_boot_modes[] = { void s_init(void) { } + +#ifdef CONFIG_IMX_HDMI +void imx_enable_hdmi_phy(void) +{ + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + u8 reg; + reg = readb(&hdmi->phy_conf0); + reg |= HDMI_PHY_CONF0_PDZ_MASK; + writeb(reg, &hdmi->phy_conf0); + udelay(3000); + reg |= HDMI_PHY_CONF0_ENTMDS_MASK; + writeb(reg, &hdmi->phy_conf0); + udelay(3000); + reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; + writeb(reg, &hdmi->phy_conf0); + writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); +} + +void imx_setup_hdmi(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + int reg; + + /* Turn on HDMI PHY clock */ + reg = readl(&mxc_ccm->CCGR2); + reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK| + MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; + writel(reg, &mxc_ccm->CCGR2); + writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); + reg = readl(&mxc_ccm->chsccdr); + reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK| + MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK| + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); + reg |= (CHSCCDR_PODF_DIVIDE_BY_3 + << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) + |(CHSCCDR_IPU_PRE_CLK_540M_PFD + << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->chsccdr); +} +#endif diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index cfd4edc..d03d24a 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -65,5 +65,5 @@ void enable_ocotp_clk(unsigned char enable); void enable_usboh3_clk(unsigned char enable); int enable_sata_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); - +void enable_ipu_clock(void); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h index 9dccb3f..5cd6aa6 100644 --- a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h +++ b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h @@ -21,6 +21,11 @@ #ifndef __MXC_HDMI_H__ #define __MXC_HDMI_H__ +#ifdef CONFIG_IMX_HDMI +void imx_enable_hdmi_phy(void); +void imx_setup_hdmi(void); +#endif + /* * Hdmi controller registers */ -- cgit v1.1 From 10f779da54b8a8c85df6d58592c40836d8e7ed49 Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Tue, 23 Jul 2013 15:07:56 -0700 Subject: imx: nitrogen6x: mx6qsabrelite: Add support for DVI monitors A little background is probably appropriate for this patch. Since "the beginning" of usage of the SABRE Lite and Nitrogen6x boards, DVI detection has been somewhat broken. Some (most) DVI monitors don't produce the "HPD" bit in the PHY_STAT0 register, but do show proper toggling of the RX_SENSE0..3 bits. Creating a new the bit-mask to include all five bits and modifying the 'hdmidet' command and internal detection routines allows these monitors to function properly in U-Boot. A related patch to our kernels allows things to work under Linux: https://github.com/boundarydevices/linux-imx6/commit/7d8752905c118af9063738a533227de0b2f6ecd4 Signed-off-by: Robert Winkler Acked-by: Stefano Babic --- arch/arm/imx-common/cmd_hdmidet.c | 3 +-- arch/arm/include/asm/arch-mx6/mxc_hdmi.h | 3 +++ 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/imx-common/cmd_hdmidet.c b/arch/arm/imx-common/cmd_hdmidet.c index 794bf50..ce0b26e 100644 --- a/arch/arm/imx-common/cmd_hdmidet.c +++ b/arch/arm/imx-common/cmd_hdmidet.c @@ -27,8 +27,7 @@ static int do_hdmidet(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; - u8 reg = readb(&hdmi->phy_stat0) & HDMI_PHY_HPD; - return (reg&HDMI_PHY_HPD) ? 0 : 1; + return (readb(&hdmi->phy_stat0) & HDMI_DVI_STAT) ? 0 : 1; } U_BOOT_CMD(hdmidet, 1, 1, do_hdmidet, diff --git a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h index 5cd6aa6..2d93658 100644 --- a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h +++ b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h @@ -901,6 +901,9 @@ enum { HDMI_PHY_HPD = 0x02, HDMI_PHY_TX_PHY_LOCK = 0x01, +/* Convenience macro RX_SENSE | HPD */ + HDMI_DVI_STAT = 0xF2, + /* PHY_I2CM_SLAVE_ADDR field values */ HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69, HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49, -- cgit v1.1 From 392bba4ad0049832f50eb368a04992f9719744b0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 18 Jul 2013 15:13:02 -0400 Subject: am33xx: Correct gpmc_cfg->irqstatus/enable Based on our usage of the GPMC, either with NOR or NAND we do not need to be setting the irqstatus or irqenable bits and should clear them like we have historically. Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/am33xx/mem.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c index f81c9a8..03e8c66 100644 --- a/arch/arm/cpu/armv7/am33xx/mem.c +++ b/arch/arm/cpu/armv7/am33xx/mem.c @@ -69,8 +69,8 @@ void gpmc_init(void) #endif /* global settings */ writel(0x00000008, &gpmc_cfg->sysconfig); - writel(0x00000100, &gpmc_cfg->irqstatus); - writel(0x00000100, &gpmc_cfg->irqenable); + writel(0x00000000, &gpmc_cfg->irqstatus); + writel(0x00000000, &gpmc_cfg->irqenable); writel(0x00000012, &gpmc_cfg->config); /* * Disable the GPMC0 config set by ROM code -- cgit v1.1 From cd8845d7a49687e9e7f727c9d821accf22854dd3 Mon Sep 17 00:00:00 2001 From: Steve Kipisz Date: Thu, 18 Jul 2013 15:13:03 -0400 Subject: am335x_evm: Add support for the NOR module on the memory cape This patch adds support for the NOR module that attaches to the memory cape for a Beaglebone board. This does not add booting support; only support so that you can boot from SD/MMC and see the NOR module so that it can be programmed. Signed-off-by: Steve Kipisz [trini: Clean up config changes slightly] Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/am33xx/mem.c | 4 ++++ arch/arm/include/asm/arch-am33xx/mem.h | 9 +++++++++ 2 files changed, 13 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c index 03e8c66..b6eb466 100644 --- a/arch/arm/cpu/armv7/am33xx/mem.c +++ b/arch/arm/cpu/armv7/am33xx/mem.c @@ -71,7 +71,11 @@ void gpmc_init(void) writel(0x00000008, &gpmc_cfg->sysconfig); writel(0x00000000, &gpmc_cfg->irqstatus); writel(0x00000000, &gpmc_cfg->irqenable); +#ifdef CONFIG_NOR + writel(0x00000200, &gpmc_cfg->config); +#else writel(0x00000012, &gpmc_cfg->config); +#endif /* * Disable the GPMC0 config set by ROM code */ diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h index aef4e82..983ea28 100644 --- a/arch/arm/include/asm/arch-am33xx/mem.h +++ b/arch/arm/include/asm/arch-am33xx/mem.h @@ -30,6 +30,7 @@ * * Currently valid part Names are (PART): * M_NAND - Micron NAND + * STNOR - STMicrolelctronics M29W128GL */ #define GPMC_SIZE_256M 0x0 #define GPMC_SIZE_128M 0x8 @@ -45,6 +46,14 @@ #define M_NAND_GPMC_CONFIG6 0x16000f80 #define M_NAND_GPMC_CONFIG7 0x00000008 +#define STNOR_GPMC_CONFIG1 0x00001200 +#define STNOR_GPMC_CONFIG2 0x00101000 +#define STNOR_GPMC_CONFIG3 0x00030301 +#define STNOR_GPMC_CONFIG4 0x10041004 +#define STNOR_GPMC_CONFIG5 0x000C1010 +#define STNOR_GPMC_CONFIG6 0x08070280 +#define STNOR_GPMC_CONFIG7 0x00000F48 + /* max number of GPMC Chip Selects */ #define GPMC_MAX_CS 8 /* max number of GPMC regs */ -- cgit v1.1 From c5c7a7c32d552592ac49749e5c184c89bd50c098 Mon Sep 17 00:00:00 2001 From: Steve Kipisz Date: Thu, 18 Jul 2013 15:13:04 -0400 Subject: am335x_evm: Add support to boot from NOR. NOR requires that s_init be within the first 4KiB of the image so that we can perform the rest of the required pinmuxing to talk with the rest of NOR that we are found on. When NOR_BOOT is set we save our environment in NOR at 512KiB and a redundant copy at 768KiB. We avoid using SPL for this case and u-boot.bin is written directly to the start of NOR. We enclose the DMM-related parts of arch/arm/cpu/armv7/am33xx/emif4.c with TI81xx checks as at this time U-Boot does not discard unused sections in the main build and this code relies on functions specific to (and only provided in) ti81xx-related code. Cc: Albert ARIBAUD Signed-off-by: Steve Kipisz Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/am33xx/board.c | 2 +- arch/arm/cpu/armv7/am33xx/emif4.c | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 07ab91c..f1623db 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -142,7 +142,7 @@ int arch_misc_init(void) return 0; } -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) void rtc32k_enable(void) { struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE; diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index ad7b70f..55dc321 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -35,9 +35,11 @@ void dram_init_banksize(void) } -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) +#ifdef CONFIG_TI81XX static struct dmm_lisa_map_regs *hw_lisa_map_regs = (struct dmm_lisa_map_regs *)DMM_BASE; +#endif static struct vtp_reg *vtpreg[2] = { (struct vtp_reg *)VTP0_CTRL_ADDR, (struct vtp_reg *)VTP1_CTRL_ADDR}; @@ -45,6 +47,7 @@ static struct vtp_reg *vtpreg[2] = { static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; #endif +#ifdef CONFIG_TI81XX void config_dmm(const struct dmm_lisa_map_regs *regs) { enable_dmm_clocks(); @@ -59,6 +62,7 @@ void config_dmm(const struct dmm_lisa_map_regs *regs) writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1); writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0); } +#endif static void config_vtp(int nr) { -- cgit v1.1 From 94d77fb656d49f2b0efe2de5605a52c5145d2c3b Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 30 Jul 2013 10:48:52 +0530 Subject: ARM: AM33xx: Cleanup dplls data Locking sequence for all the dplls is same. In the current code same sequence is done repeatedly for each dpll. Instead have a generic function for locking dplls and pass dpll data to that function. This is derived from OMAP4 boards. Signed-off-by: Lokesh Vutla Tested-by: Heiko Schocher Acked-by: Heiko Schocher --- arch/arm/cpu/armv7/am33xx/Makefile | 1 + arch/arm/cpu/armv7/am33xx/clock.c | 111 ++++++++++++++ arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 220 +++++---------------------- arch/arm/cpu/armv7/am33xx/emif4.c | 4 + arch/arm/include/asm/arch-am33xx/clock.h | 70 +++++++++ arch/arm/include/asm/arch-am33xx/ddr_defs.h | 2 + arch/arm/include/asm/arch-am33xx/sys_proto.h | 1 + 7 files changed, 227 insertions(+), 182 deletions(-) create mode 100644 arch/arm/cpu/armv7/am33xx/clock.c (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile index dbd1ec3..7fd21af 100644 --- a/arch/arm/cpu/armv7/am33xx/Makefile +++ b/arch/arm/cpu/armv7/am33xx/Makefile @@ -10,6 +10,7 @@ LIB = $(obj)lib$(SOC).o COBJS-$(CONFIG_AM33XX) += clock_am33xx.o COBJS-$(CONFIG_TI814X) += clock_ti814x.o +COBJS-$(CONFIG_AM33XX) += clock.o COBJS += sys_info.o COBJS += mem.o COBJS += ddr.o diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c new file mode 100644 index 0000000..15f4a2c --- /dev/null +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -0,0 +1,111 @@ +/* + * clock.c + * + * Clock initialization for AM33XX boards. + * Derived from OMAP4 boards + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include + +static void setup_post_dividers(const struct dpll_regs *dpll_regs, + const struct dpll_params *params) +{ + /* Setup post-dividers */ + if (params->m2 >= 0) + writel(params->m2, dpll_regs->cm_div_m2_dpll); + if (params->m3 >= 0) + writel(params->m3, dpll_regs->cm_div_m3_dpll); + if (params->m4 >= 0) + writel(params->m4, dpll_regs->cm_div_m4_dpll); + if (params->m5 >= 0) + writel(params->m5, dpll_regs->cm_div_m5_dpll); + if (params->m6 >= 0) + writel(params->m6, dpll_regs->cm_div_m6_dpll); +} + +static inline void do_lock_dpll(const struct dpll_regs *dpll_regs) +{ + clrsetbits_le32(dpll_regs->cm_clkmode_dpll, + CM_CLKMODE_DPLL_DPLL_EN_MASK, + DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT); +} + +static inline void wait_for_lock(const struct dpll_regs *dpll_regs) +{ + if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK, + (void *)dpll_regs->cm_idlest_dpll, LDELAY)) { + printf("DPLL locking failed for 0x%x\n", + dpll_regs->cm_clkmode_dpll); + hang(); + } +} + +static inline void do_bypass_dpll(const struct dpll_regs *dpll_regs) +{ + clrsetbits_le32(dpll_regs->cm_clkmode_dpll, + CM_CLKMODE_DPLL_DPLL_EN_MASK, + DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT); +} + +static inline void wait_for_bypass(const struct dpll_regs *dpll_regs) +{ + if (!wait_on_value(ST_DPLL_CLK_MASK, 0, + (void *)dpll_regs->cm_idlest_dpll, LDELAY)) { + printf("Bypassing DPLL failed 0x%x\n", + dpll_regs->cm_clkmode_dpll); + } +} + +static void bypass_dpll(const struct dpll_regs *dpll_regs) +{ + do_bypass_dpll(dpll_regs); + wait_for_bypass(dpll_regs); +} + +void do_setup_dpll(const struct dpll_regs *dpll_regs, + const struct dpll_params *params) +{ + u32 temp; + + if (!params) + return; + + temp = readl(dpll_regs->cm_clksel_dpll); + + bypass_dpll(dpll_regs); + + /* Set M & N */ + temp &= ~CM_CLKSEL_DPLL_M_MASK; + temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK; + + temp &= ~CM_CLKSEL_DPLL_N_MASK; + temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK; + + writel(temp, dpll_regs->cm_clksel_dpll); + + setup_post_dividers(dpll_regs, params); + + /* Wait till the DPLL locks */ + do_lock_dpll(dpll_regs); + wait_for_lock(dpll_regs); +} + +void setup_dplls(void) +{ + const struct dpll_params *params; + do_setup_dpll(&dpll_core_regs, &dpll_core); + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu); + do_setup_dpll(&dpll_per_regs, &dpll_per); + writel(0x300, &cmwkup->clkdcoldodpllper); + + params = get_dpll_ddr_params(); + do_setup_dpll(&dpll_ddr_regs, params); +} diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c index fb3fb43..d5d47ad 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c @@ -18,56 +18,51 @@ #define PRCM_FORCE_WAKEUP 0x2 #define PRCM_FUNCTL 0x0 -#define PRCM_EMIF_CLK_ACTIVITY BIT(2) -#define PRCM_L3_GCLK_ACTIVITY BIT(4) - -#define PLL_BYPASS_MODE 0x4 -#define ST_MN_BYPASS 0x00000100 -#define ST_DPLL_CLK 0x00000001 -#define CLK_SEL_MASK 0x7ffff -#define CLK_DIV_MASK 0x1f -#define CLK_DIV2_MASK 0x7f -#define CLK_SEL_SHIFT 0x8 -#define CLK_MODE_SEL 0x7 -#define CLK_MODE_MASK 0xfffffff8 -#define CLK_DIV_SEL 0xFFFFFFE0 #define CPGMAC0_IDLE 0x30000 -#define DPLL_CLKDCOLDO_GATE_CTRL 0x300 - #define OSC (V_OSCK/1000000) -#define MPUPLL_M CONFIG_SYS_MPUCLK -#define MPUPLL_N (OSC-1) -#define MPUPLL_M2 1 - -/* Core PLL Fdll = 1 GHZ, */ -#define COREPLL_M 1000 -#define COREPLL_N (OSC-1) - -#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */ -#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */ -#define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */ - -/* - * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll - * frequency needs to be set to 960 MHZ. Hence, - * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below - */ -#define PERPLL_M 960 -#define PERPLL_N (OSC-1) -#define PERPLL_M2 5 - -/* DDR Freq is 266 MHZ for now */ -/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */ -#define DDRPLL_M 266 -#define DDRPLL_N (OSC-1) -#define DDRPLL_M2 1 - const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP; const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL; const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC; +const struct dpll_regs dpll_mpu_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x88, + .cm_idlest_dpll = CM_WKUP + 0x20, + .cm_clksel_dpll = CM_WKUP + 0x2C, + .cm_div_m2_dpll = CM_WKUP + 0xA8, +}; + +const struct dpll_regs dpll_core_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x90, + .cm_idlest_dpll = CM_WKUP + 0x5C, + .cm_clksel_dpll = CM_WKUP + 0x68, + .cm_div_m4_dpll = CM_WKUP + 0x80, + .cm_div_m5_dpll = CM_WKUP + 0x84, + .cm_div_m6_dpll = CM_WKUP + 0xD8, +}; + +const struct dpll_regs dpll_per_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x8C, + .cm_idlest_dpll = CM_WKUP + 0x70, + .cm_clksel_dpll = CM_WKUP + 0x9C, + .cm_div_m2_dpll = CM_WKUP + 0xAC, +}; + +const struct dpll_regs dpll_ddr_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x94, + .cm_idlest_dpll = CM_WKUP + 0x34, + .cm_clksel_dpll = CM_WKUP + 0x40, + .cm_div_m2_dpll = CM_WKUP + 0xA0, +}; + +const struct dpll_params dpll_mpu = { + CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_core = { + 1000, OSC-1, -1, -1, 10, 8, 4}; +const struct dpll_params dpll_per = { + 960, OSC-1, 5, -1, -1, -1, -1}; + static void enable_interface_clocks(void) { /* Enable all the Interconnect Modules */ @@ -238,142 +233,6 @@ static void enable_per_clocks(void) ; } -void mpu_pll_config_val(int mpull_m) -{ - u32 clkmode, clksel, div_m2; - - clkmode = readl(&cmwkup->clkmoddpllmpu); - clksel = readl(&cmwkup->clkseldpllmpu); - div_m2 = readl(&cmwkup->divm2dpllmpu); - - /* Set the PLL to bypass Mode */ - writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu); - while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS) - ; - - clksel = clksel & (~CLK_SEL_MASK); - clksel = clksel | ((mpull_m << CLK_SEL_SHIFT) | MPUPLL_N); - writel(clksel, &cmwkup->clkseldpllmpu); - - div_m2 = div_m2 & ~CLK_DIV_MASK; - div_m2 = div_m2 | MPUPLL_M2; - writel(div_m2, &cmwkup->divm2dpllmpu); - - clkmode = clkmode | CLK_MODE_SEL; - writel(clkmode, &cmwkup->clkmoddpllmpu); - - while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK) - ; -} - -static void mpu_pll_config(void) -{ - mpu_pll_config_val(CONFIG_SYS_MPUCLK); -} - -static void core_pll_config(void) -{ - u32 clkmode, clksel, div_m4, div_m5, div_m6; - - clkmode = readl(&cmwkup->clkmoddpllcore); - clksel = readl(&cmwkup->clkseldpllcore); - div_m4 = readl(&cmwkup->divm4dpllcore); - div_m5 = readl(&cmwkup->divm5dpllcore); - div_m6 = readl(&cmwkup->divm6dpllcore); - - /* Set the PLL to bypass Mode */ - writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore); - - while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS) - ; - - clksel = clksel & (~CLK_SEL_MASK); - clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N); - writel(clksel, &cmwkup->clkseldpllcore); - - div_m4 = div_m4 & ~CLK_DIV_MASK; - div_m4 = div_m4 | COREPLL_M4; - writel(div_m4, &cmwkup->divm4dpllcore); - - div_m5 = div_m5 & ~CLK_DIV_MASK; - div_m5 = div_m5 | COREPLL_M5; - writel(div_m5, &cmwkup->divm5dpllcore); - - div_m6 = div_m6 & ~CLK_DIV_MASK; - div_m6 = div_m6 | COREPLL_M6; - writel(div_m6, &cmwkup->divm6dpllcore); - - clkmode = clkmode | CLK_MODE_SEL; - writel(clkmode, &cmwkup->clkmoddpllcore); - - while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK) - ; -} - -static void per_pll_config(void) -{ - u32 clkmode, clksel, div_m2; - - clkmode = readl(&cmwkup->clkmoddpllper); - clksel = readl(&cmwkup->clkseldpllper); - div_m2 = readl(&cmwkup->divm2dpllper); - - /* Set the PLL to bypass Mode */ - writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper); - - while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS) - ; - - clksel = clksel & (~CLK_SEL_MASK); - clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N); - writel(clksel, &cmwkup->clkseldpllper); - - div_m2 = div_m2 & ~CLK_DIV2_MASK; - div_m2 = div_m2 | PERPLL_M2; - writel(div_m2, &cmwkup->divm2dpllper); - - clkmode = clkmode | CLK_MODE_SEL; - writel(clkmode, &cmwkup->clkmoddpllper); - - while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK) - ; - - writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper); -} - -void ddr_pll_config(unsigned int ddrpll_m) -{ - u32 clkmode, clksel, div_m2; - - clkmode = readl(&cmwkup->clkmoddpllddr); - clksel = readl(&cmwkup->clkseldpllddr); - div_m2 = readl(&cmwkup->divm2dpllddr); - - /* Set the PLL to bypass Mode */ - clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE; - writel(clkmode, &cmwkup->clkmoddpllddr); - - /* Wait till bypass mode is enabled */ - while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS) - != ST_MN_BYPASS) - ; - - clksel = clksel & (~CLK_SEL_MASK); - clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N); - writel(clksel, &cmwkup->clkseldpllddr); - - div_m2 = div_m2 & CLK_DIV_SEL; - div_m2 = div_m2 | DDRPLL_M2; - writel(div_m2, &cmwkup->divm2dpllddr); - - clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL; - writel(clkmode, &cmwkup->clkmoddpllddr); - - /* Wait till dpll is locked */ - while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK) - ; -} - void enable_emif_clocks(void) { /* Enable the EMIF_FW Functional clock */ @@ -390,10 +249,7 @@ void enable_emif_clocks(void) */ void pll_init() { - mpu_pll_config(); - core_pll_config(); - per_pll_config(); - + setup_dplls(); /* Enable the required interconnect clocks */ enable_interface_clocks(); diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index 55dc321..15c4734 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -79,6 +79,10 @@ static void config_vtp(int nr) ; } +void __weak ddr_pll_config(unsigned int ddrpll_m) +{ +} + void config_ddr(unsigned int pll, unsigned int ioctrl, const struct ddr_data *data, const struct cmd_control *ctrl, const struct emif_regs *regs, int nr) diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 44c1e5d..703b80e 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -13,4 +13,74 @@ #include +#define LDELAY 1000000 + +/* CM_CLKMODE_DPLL */ +#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 +#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) +#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 +#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) +#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 +#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) +#define CM_CLKMODE_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) + +#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 + +#define DPLL_EN_STOP 1 +#define DPLL_EN_MN_BYPASS 4 +#define DPLL_EN_LOW_POWER_BYPASS 5 +#define DPLL_EN_LOCK 7 + +/* CM_IDLEST_DPLL fields */ +#define ST_DPLL_CLK_MASK 1 + +/* CM_CLKSEL_DPLL */ +#define CM_CLKSEL_DPLL_M_SHIFT 8 +#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) +#define CM_CLKSEL_DPLL_N_SHIFT 0 +#define CM_CLKSEL_DPLL_N_MASK 0x7F + +struct dpll_params { + u32 m; + u32 n; + s8 m2; + s8 m3; + s8 m4; + s8 m5; + s8 m6; +}; + +struct dpll_regs { + u32 cm_clkmode_dpll; + u32 cm_idlest_dpll; + u32 cm_autoidle_dpll; + u32 cm_clksel_dpll; + u32 cm_div_m2_dpll; + u32 cm_div_m3_dpll; + u32 cm_div_m4_dpll; + u32 cm_div_m5_dpll; + u32 cm_div_m6_dpll; +}; + +extern const struct dpll_regs dpll_mpu_regs; +extern const struct dpll_regs dpll_core_regs; +extern const struct dpll_regs dpll_per_regs; +extern const struct dpll_regs dpll_ddr_regs; +extern const struct dpll_params dpll_mpu; +extern const struct dpll_params dpll_core; +extern const struct dpll_params dpll_per; +extern const struct dpll_params dpll_ddr; + +extern const struct cm_wkuppll *cmwkup; + +void setup_dplls(void); +const struct dpll_params *get_dpll_ddr_params(void); +void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *); + #endif diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 18d7d99..683ba8e 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -146,6 +146,8 @@ void set_sdram_timings(const struct emif_regs *regs, int nr); */ void config_ddr_phy(const struct emif_regs *regs, int nr); +void ddr_pll_config(unsigned int ddrpll_m); + struct ddr_cmd_regs { unsigned int resv0[7]; unsigned int cm0csratio; /* offset 0x01C */ diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 1424f90..dbcede0 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -37,4 +37,5 @@ void omap_nand_switch_ecc(uint32_t, uint32_t); void rtc32k_enable(void); void uart_soft_reset(void); +u32 wait_on_value(u32, u32, void *, u32); #endif -- cgit v1.1 From 95cb69faeb45f6396a1336bff201a50ea1677d85 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 30 Jul 2013 10:48:53 +0530 Subject: ARM: AM33xx: Cleanup clocks layer Cleaning up the clocks layer. This helps in addition of new Soc with minimal changes. This is derived from OMAP4 boards. Signed-off-by: Lokesh Vutla Tested-by: Heiko Schocher Acked-by: Heiko Schocher --- arch/arm/cpu/armv7/am33xx/board.c | 6 - arch/arm/cpu/armv7/am33xx/clock.c | 62 ++++++- arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 275 ++++++++-------------------- arch/arm/cpu/armv7/am33xx/clock_ti814x.c | 19 +- arch/arm/cpu/armv7/am33xx/emif4.c | 1 - arch/arm/include/asm/arch-am33xx/clock.h | 28 ++- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 2 - 7 files changed, 174 insertions(+), 219 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index f1623db..64a3af7 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -56,12 +56,6 @@ int cpu_mmc_init(bd_t *bis) } #endif -void setup_clocks_for_console(void) -{ - /* Not yet implemented */ - return; -} - /* AM33XX has two MUSB controllers which can be host or gadget */ #if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \ (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c index 15f4a2c..8e5f3c6 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -98,7 +98,7 @@ void do_setup_dpll(const struct dpll_regs *dpll_regs, wait_for_lock(dpll_regs); } -void setup_dplls(void) +static void setup_dplls(void) { const struct dpll_params *params; do_setup_dpll(&dpll_core_regs, &dpll_core); @@ -109,3 +109,63 @@ void setup_dplls(void) params = get_dpll_ddr_params(); do_setup_dpll(&dpll_ddr_regs, params); } + +static inline void wait_for_clk_enable(u32 *clkctrl_addr) +{ + u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED; + u32 bound = LDELAY; + + while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) || + (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) { + clkctrl = readl(clkctrl_addr); + idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> + MODULE_CLKCTRL_IDLEST_SHIFT; + if (--bound == 0) { + printf("Clock enable failed for 0x%p idlest 0x%x\n", + clkctrl_addr, clkctrl); + return; + } + } +} + +static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode, + u32 wait_for_enable) +{ + clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, + enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT); + debug("Enable clock module - %p\n", clkctrl_addr); + if (wait_for_enable) + wait_for_clk_enable(clkctrl_addr); +} + +static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode) +{ + clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, + enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT); + debug("Enable clock domain - %p\n", clkctrl_reg); +} + +void do_enable_clocks(u32 *const *clk_domains, + u32 *const *clk_modules_explicit_en, u8 wait_for_enable) +{ + u32 i, max = 100; + + /* Put the clock domains in SW_WKUP mode */ + for (i = 0; (i < max) && clk_domains[i]; i++) { + enable_clock_domain(clk_domains[i], + CD_CLKCTRL_CLKTRCTRL_SW_WKUP); + } + + /* Clock modules that need to be put in SW_EXPLICIT_EN mode */ + for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) { + enable_clock_module(clk_modules_explicit_en[i], + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN, + wait_for_enable); + }; +} + +void prcm_init() +{ + enable_basic_clocks(); + setup_dplls(); +} diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c index d5d47ad..e5f287b 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c @@ -14,17 +14,12 @@ #include #include -#define PRCM_MOD_EN 0x2 -#define PRCM_FORCE_WAKEUP 0x2 -#define PRCM_FUNCTL 0x0 - -#define CPGMAC0_IDLE 0x30000 #define OSC (V_OSCK/1000000) -const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; -const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP; -const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL; -const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC; +struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; +struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP; +struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL; +struct cm_rtc *const cmrtc = (struct cm_rtc *)CM_RTC; const struct dpll_regs dpll_mpu_regs = { .cm_clkmode_dpll = CM_WKUP + 0x88, @@ -63,199 +58,85 @@ const struct dpll_params dpll_core = { const struct dpll_params dpll_per = { 960, OSC-1, 5, -1, -1, -1, -1}; -static void enable_interface_clocks(void) -{ - /* Enable all the Interconnect Modules */ - writel(PRCM_MOD_EN, &cmper->l3clkctrl); - while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN) - ; - - writel(PRCM_MOD_EN, &cmper->l4lsclkctrl); - while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN) - ; - - writel(PRCM_MOD_EN, &cmper->l4fwclkctrl); - while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN) - ; - - writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl); - while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN) - ; - - writel(PRCM_MOD_EN, &cmper->l3instrclkctrl); - while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN) - ; - - writel(PRCM_MOD_EN, &cmper->l4hsclkctrl); - while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN) - ; - - writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl); - while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN) - ; -} - -/* - * Force power domain wake up transition - * Ensure that the corresponding interface clock is active before - * using the peripheral - */ -static void power_domain_wkup_transition(void) +void setup_clocks_for_console(void) { - writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl); - writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl); - writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl); - writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl); - writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl); + clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, + CD_CLKCTRL_CLKTRCTRL_SW_WKUP << + CD_CLKCTRL_CLKTRCTRL_SHIFT); + + clrsetbits_le32(&cmper->l4hsclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, + CD_CLKCTRL_CLKTRCTRL_SW_WKUP << + CD_CLKCTRL_CLKTRCTRL_SHIFT); + + clrsetbits_le32(&cmwkup->wkup_uart0ctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + clrsetbits_le32(&cmper->uart1clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + clrsetbits_le32(&cmper->uart2clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + clrsetbits_le32(&cmper->uart3clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + clrsetbits_le32(&cmper->uart4clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + clrsetbits_le32(&cmper->uart5clkctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); } -/* - * Enable the peripheral clock for required peripherals - */ -static void enable_per_clocks(void) +void enable_basic_clocks(void) { - /* Enable the control module though RBL would have done it*/ - writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl); - while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN) - ; - - /* Enable the module clock */ - writel(PRCM_MOD_EN, &cmper->timer2clkctrl); - while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN) - ; + u32 *const clk_domains[] = { + &cmper->l3clkstctrl, + &cmper->l4fwclkstctrl, + &cmper->l3sclkstctrl, + &cmper->l4lsclkstctrl, + &cmwkup->wkclkstctrl, + &cmper->emiffwclkctrl, + &cmrtc->clkstctrl, + 0 + }; + + u32 *const clk_modules_explicit_en[] = { + &cmper->l3clkctrl, + &cmper->l4lsclkctrl, + &cmper->l4fwclkctrl, + &cmwkup->wkl4wkclkctrl, + &cmper->l3instrclkctrl, + &cmper->l4hsclkctrl, + &cmwkup->wkgpio0clkctrl, + &cmwkup->wkctrlclkctrl, + &cmper->timer2clkctrl, + &cmper->gpmcclkctrl, + &cmper->elmclkctrl, + &cmper->mmc0clkctrl, + &cmper->mmc1clkctrl, + &cmwkup->wkup_i2c0ctrl, + &cmper->gpio1clkctrl, + &cmper->gpio2clkctrl, + &cmper->gpio3clkctrl, + &cmper->i2c1clkctrl, + &cmper->cpgmac0clkctrl, + &cmper->spi0clkctrl, + &cmrtc->rtcclkctrl, + &cmper->usb0clkctrl, + &cmper->emiffwclkctrl, + &cmper->emifclkctrl, + 0 + }; + + do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); /* Select the Master osc 24 MHZ as Timer2 clock source */ writel(0x1, &cmdpll->clktimer2clk); - - /* UART0 */ - writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl); - while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN) - ; - - /* UART1 */ -#ifdef CONFIG_SERIAL2 - writel(PRCM_MOD_EN, &cmper->uart1clkctrl); - while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN) - ; -#endif /* CONFIG_SERIAL2 */ - - /* UART2 */ -#ifdef CONFIG_SERIAL3 - writel(PRCM_MOD_EN, &cmper->uart2clkctrl); - while (readl(&cmper->uart2clkctrl) != PRCM_MOD_EN) - ; -#endif /* CONFIG_SERIAL3 */ - - /* UART3 */ -#ifdef CONFIG_SERIAL4 - writel(PRCM_MOD_EN, &cmper->uart3clkctrl); - while (readl(&cmper->uart3clkctrl) != PRCM_MOD_EN) - ; -#endif /* CONFIG_SERIAL4 */ - - /* UART4 */ -#ifdef CONFIG_SERIAL5 - writel(PRCM_MOD_EN, &cmper->uart4clkctrl); - while (readl(&cmper->uart4clkctrl) != PRCM_MOD_EN) - ; -#endif /* CONFIG_SERIAL5 */ - - /* UART5 */ -#ifdef CONFIG_SERIAL6 - writel(PRCM_MOD_EN, &cmper->uart5clkctrl); - while (readl(&cmper->uart5clkctrl) != PRCM_MOD_EN) - ; -#endif /* CONFIG_SERIAL6 */ - - /* GPMC */ - writel(PRCM_MOD_EN, &cmper->gpmcclkctrl); - while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN) - ; - - /* ELM */ - writel(PRCM_MOD_EN, &cmper->elmclkctrl); - while (readl(&cmper->elmclkctrl) != PRCM_MOD_EN) - ; - - /* MMC0*/ - writel(PRCM_MOD_EN, &cmper->mmc0clkctrl); - while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN) - ; - - /* MMC1 */ - writel(PRCM_MOD_EN, &cmper->mmc1clkctrl); - while (readl(&cmper->mmc1clkctrl) != PRCM_MOD_EN) - ; - - /* i2c0 */ - writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl); - while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN) - ; - - /* gpio1 module */ - writel(PRCM_MOD_EN, &cmper->gpio1clkctrl); - while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN) - ; - - /* gpio2 module */ - writel(PRCM_MOD_EN, &cmper->gpio2clkctrl); - while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN) - ; - - /* gpio3 module */ - writel(PRCM_MOD_EN, &cmper->gpio3clkctrl); - while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN) - ; - - /* i2c1 */ - writel(PRCM_MOD_EN, &cmper->i2c1clkctrl); - while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN) - ; - - /* Ethernet */ - writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl); - while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL) - ; - - /* spi0 */ - writel(PRCM_MOD_EN, &cmper->spi0clkctrl); - while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN) - ; - - /* RTC */ - writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl); - while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN) - ; - - /* MUSB */ - writel(PRCM_MOD_EN, &cmper->usb0clkctrl); - while (readl(&cmper->usb0clkctrl) != PRCM_MOD_EN) - ; -} - -void enable_emif_clocks(void) -{ - /* Enable the EMIF_FW Functional clock */ - writel(PRCM_MOD_EN, &cmper->emiffwclkctrl); - /* Enable EMIF0 Clock */ - writel(PRCM_MOD_EN, &cmper->emifclkctrl); - /* Poll if module is functional */ - while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN) - ; -} - -/* - * Configure the PLL/PRCM for necessary peripherals - */ -void pll_init() -{ - setup_dplls(); - /* Enable the required interconnect clocks */ - enable_interface_clocks(); - - /* Power domain wake up transition */ - power_domain_wkup_transition(); - - /* Enable the required peripherals */ - enable_per_clocks(); } diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c index 658772b..965e875 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c +++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c @@ -264,11 +264,6 @@ const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE; */ static void enable_per_clocks(void) { - /* UART0 */ - writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl); - while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN) - ; - /* HSMMC1 */ writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl); while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN) @@ -455,8 +450,6 @@ void sata_pll_config(void) ; } -void enable_emif_clocks(void) {}; - void enable_dmm_clocks(void) { writel(PRCM_MOD_EN, &cmdef->fwclkctrl); @@ -477,13 +470,19 @@ void enable_dmm_clocks(void) ; } +void setup_clocks_for_console(void) +{ + unlock_pll_control_mmr(); + /* UART0 */ + writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl); + while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN) + ; +} /* * Configure the PLL/PRCM for necessary peripherals */ -void pll_init() +void prcm_init(void) { - unlock_pll_control_mmr(); - /* Enable the control module */ writel(PRCM_MOD_EN, &cmalwon->controlclkctrl); diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index 15c4734..21cefd4 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -87,7 +87,6 @@ void config_ddr(unsigned int pll, unsigned int ioctrl, const struct ddr_data *data, const struct cmd_control *ctrl, const struct emif_regs *regs, int nr) { - enable_emif_clocks(); ddr_pll_config(pll); config_vtp(nr); config_cmd_ctrl(ctrl, nr); diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 703b80e..0d4b9ae 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -15,6 +15,28 @@ #define LDELAY 1000000 +/*CM___CLKCTRL */ +#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 +#define CD_CLKCTRL_CLKTRCTRL_MASK 3 + +#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 +#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 +#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 + +/* CM___CLKCTRL */ +#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 +#define MODULE_CLKCTRL_MODULEMODE_MASK 3 +#define MODULE_CLKCTRL_IDLEST_SHIFT 16 +#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) + +#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 +#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 + +#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 +#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 +#define MODULE_CLKCTRL_IDLEST_IDLE 2 +#define MODULE_CLKCTRL_IDLEST_DISABLED 3 + /* CM_CLKMODE_DPLL */ #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) @@ -77,10 +99,12 @@ extern const struct dpll_params dpll_core; extern const struct dpll_params dpll_per; extern const struct dpll_params dpll_ddr; -extern const struct cm_wkuppll *cmwkup; +extern struct cm_wkuppll *const cmwkup; -void setup_dplls(void); const struct dpll_params *get_dpll_ddr_params(void); void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *); +void prcm_init(void); +void enable_basic_clocks(void); +void do_enable_clocks(u32 *const *, u32 *const *, u8); #endif diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 683ba8e..18d7d99 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -146,8 +146,6 @@ void set_sdram_timings(const struct emif_regs *regs, int nr); */ void config_ddr_phy(const struct emif_regs *regs, int nr); -void ddr_pll_config(unsigned int ddrpll_m); - struct ddr_cmd_regs { unsigned int resv0[7]; unsigned int cm0csratio; /* offset 0x01C */ -- cgit v1.1 From 0660481a59cccd324fc2dfcad9734318a8c25a90 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 30 Jul 2013 10:48:54 +0530 Subject: ARM: AM33xx: Move s_init to a common place s_init has the same outline for all the AM33xx based board. So making it generic. This also helps in addition of new Soc with minimal changes. Signed-off-by: Lokesh Vutla Signed-off-by: Heiko Schocher Signed-off-by: Tom Rini Tested-by: Heiko Schocher Acked-by: Heiko Schocher --- arch/arm/cpu/armv7/am33xx/board.c | 62 +++++++++++++++++++++--- arch/arm/cpu/armv7/am33xx/clock_ti814x.c | 6 +++ arch/arm/include/asm/arch-am33xx/clocks_am33xx.h | 6 ++- arch/arm/include/asm/arch-am33xx/sys_proto.h | 8 ++- 4 files changed, 72 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 64a3af7..2ea3d69 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -137,7 +137,7 @@ int arch_misc_init(void) } #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) -void rtc32k_enable(void) +static void rtc32k_enable(void) { struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE; @@ -153,11 +153,7 @@ void rtc32k_enable(void) writel((1 << 3) | (1 << 6), &rtc->osc); } -#define UART_RESET (0x1 << 1) -#define UART_CLK_RUNNING_MASK 0x1 -#define UART_SMART_IDLE_EN (0x1 << 0x3) - -void uart_soft_reset(void) +static void uart_soft_reset(void) { struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; u32 regval; @@ -174,4 +170,58 @@ void uart_soft_reset(void) regval |= UART_SMART_IDLE_EN; writel(regval, &uart_base->uartsyscfg); } + +static void watchdog_disable(void) +{ + struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; + + writel(0xAAAA, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; + writel(0x5555, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; +} #endif + +void s_init(void) +{ + /* + * The ROM will only have set up sufficient pinmux to allow for the + * first 4KiB NOR to be read, we must finish doing what we know of + * the NOR mux in this space in order to continue. + */ +#ifdef CONFIG_NOR_BOOT + enable_norboot_pin_mux(); +#endif + /* + * Save the boot parameters passed from romcode. + * We cannot delay the saving further than this, + * to prevent overwrites. + */ +#ifdef CONFIG_SPL_BUILD + save_omap_boot_params(); +#endif +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) + watchdog_disable(); + timer_init(); + set_uart_mux_conf(); + setup_clocks_for_console(); + uart_soft_reset(); +#endif +#ifdef CONFIG_NOR_BOOT + gd->baudrate = CONFIG_BAUDRATE; + serial_init(); + gd->have_console = 1; +#else + gd = &gdata; + preloader_console_init(); +#endif +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) + prcm_init(); + set_mux_conf_regs(); + /* Enable RTC32K clock */ + rtc32k_enable(); + sdram_init(); +#endif +} diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c index 965e875..93c7f7b 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c +++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c @@ -277,6 +277,12 @@ static void enable_per_clocks(void) writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl); while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0) ; + + /* RTC clocks */ + writel(PRCM_MOD_EN, &cmalwon->rtcclkstctrl); + writel(PRCM_MOD_EN, &cmalwon->rtcclkctrl); + while (readl(&cmalwon->rtcclkctrl) != PRCM_MOD_EN) + ; } /* diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index 80e1899..140379f 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -16,8 +16,10 @@ #define CONFIG_SYS_MPUCLK 550 #endif -extern void pll_init(void); -extern void enable_emif_clocks(void); +#define UART_RESET (0x1 << 1) +#define UART_CLK_RUNNING_MASK 0x1 +#define UART_SMART_IDLE_EN (0x1 << 0x3) + extern void enable_dmm_clocks(void); #endif /* endif _CLOCKS_AM33XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index dbcede0..c6070a3 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -35,7 +35,11 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, u32 size); void omap_nand_switch_ecc(uint32_t, uint32_t); -void rtc32k_enable(void); -void uart_soft_reset(void); +void set_uart_mux_conf(void); +void set_mux_conf_regs(void); +void sdram_init(void); u32 wait_on_value(u32, u32, void *, u32); +#ifdef CONFIG_NOR_BOOT +void enable_norboot_pin_mux(void); +#endif #endif -- cgit v1.1 From c06e498a16eae82eda3a6947c2375990df20bd3a Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 30 Jul 2013 11:36:28 +0530 Subject: ARM: AM43xx: Add header files Adding the following data: -> Prcm structure -> Base addresses -> Pin mux structure. Signed-off-by: Lokesh Vutla --- arch/arm/include/asm/arch-am33xx/cpu.h | 164 ++++++++++++++++++++- arch/arm/include/asm/arch-am33xx/hardware.h | 8 +- arch/arm/include/asm/arch-am33xx/hardware_am33xx.h | 9 ++ arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 51 +++++++ arch/arm/include/asm/arch-am33xx/hardware_ti814x.h | 9 ++ arch/arm/include/asm/arch-am33xx/mux.h | 2 + arch/arm/include/asm/arch-am33xx/mux_am43xx.h | 142 ++++++++++++++++++ arch/arm/include/asm/arch-am33xx/omap.h | 9 +- arch/arm/include/asm/arch-am33xx/spl.h | 4 +- 9 files changed, 378 insertions(+), 20 deletions(-) create mode 100644 arch/arm/include/asm/arch-am33xx/hardware_am43xx.h create mode 100644 arch/arm/include/asm/arch-am33xx/mux_am43xx.h (limited to 'arch/arm') diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index bcb4c50..10b56e0 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -43,13 +43,6 @@ #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\ | BIT(3) | BIT(4)) -/* Reset control */ -#ifdef CONFIG_AM33XX -#define PRM_RSTCTRL (PRCM_BASE + 0x0F00) -#elif defined(CONFIG_TI814X) -#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) -#endif -#define PRM_RSTST (PRM_RSTCTRL + 8) #define PRM_RSTCTRL_RESET 0x01 #define PRM_RSTST_WARM_RESET_MASK 0x232 @@ -108,6 +101,7 @@ struct gpmc { /* Used for board specific gpmc initialization */ extern struct gpmc *gpmc_cfg; +#ifndef CONFIG_AM43XX /* Encapsulating core pll registers */ struct cm_wkuppll { unsigned int wkclkstctrl; /* offset 0x00 */ @@ -211,6 +205,162 @@ struct cm_perpll { unsigned int resv10[8]; unsigned int cpswclkstctrl; /* offset 0x144 */ }; +#else +/* Encapsulating core pll registers */ +struct cm_wkuppll { + unsigned int resv0[136]; + unsigned int wkl4wkclkctrl; /* offset 0x220 */ + unsigned int resv1[55]; + unsigned int wkclkstctrl; /* offset 0x300 */ + unsigned int resv2[15]; + unsigned int wkup_i2c0ctrl; /* offset 0x340 */ + unsigned int resv3; + unsigned int wkup_uart0ctrl; /* offset 0x348 */ + unsigned int resv4[5]; + unsigned int wkctrlclkctrl; /* offset 0x360 */ + unsigned int resv5; + unsigned int wkgpio0clkctrl; /* offset 0x368 */ + + unsigned int resv6[109]; + unsigned int clkmoddpllcore; /* offset 0x520 */ + unsigned int idlestdpllcore; /* offset 0x524 */ + unsigned int resv61; + unsigned int clkseldpllcore; /* offset 0x52C */ + unsigned int resv7[2]; + unsigned int divm4dpllcore; /* offset 0x538 */ + unsigned int divm5dpllcore; /* offset 0x53C */ + unsigned int divm6dpllcore; /* offset 0x540 */ + + unsigned int resv8[7]; + unsigned int clkmoddpllmpu; /* offset 0x560 */ + unsigned int idlestdpllmpu; /* offset 0x564 */ + unsigned int resv9; + unsigned int clkseldpllmpu; /* offset 0x56c */ + unsigned int divm2dpllmpu; /* offset 0x570 */ + + unsigned int resv10[11]; + unsigned int clkmoddpllddr; /* offset 0x5A0 */ + unsigned int idlestdpllddr; /* offset 0x5A4 */ + unsigned int resv11; + unsigned int clkseldpllddr; /* offset 0x5AC */ + unsigned int divm2dpllddr; /* offset 0x5B0 */ + + unsigned int resv12[11]; + unsigned int clkmoddpllper; /* offset 0x5E0 */ + unsigned int idlestdpllper; /* offset 0x5E4 */ + unsigned int resv13; + unsigned int clkseldpllper; /* offset 0x5EC */ + unsigned int divm2dpllper; /* offset 0x5F0 */ + unsigned int resv14[8]; + unsigned int clkdcoldodpllper; /* offset 0x614 */ + + unsigned int resv15[2]; + unsigned int clkmoddplldisp; /* offset 0x620 */ + unsigned int resv16[2]; + unsigned int clkseldplldisp; /* offset 0x62C */ + unsigned int divm2dplldisp; /* offset 0x630 */ +}; + +/* + * Encapsulating peripheral functional clocks + * pll registers + */ +struct cm_perpll { + unsigned int l3clkstctrl; /* offset 0x00 */ + unsigned int resv0[7]; + unsigned int l3clkctrl; /* Offset 0x20 */ + unsigned int resv1[7]; + unsigned int l3instrclkctrl; /* offset 0x40 */ + unsigned int resv2[3]; + unsigned int ocmcramclkctrl; /* offset 0x50 */ + unsigned int resv3[9]; + unsigned int tpccclkctrl; /* offset 0x78 */ + unsigned int resv4; + unsigned int tptc0clkctrl; /* offset 0x80 */ + + unsigned int resv5[7]; + unsigned int l4hsclkctrl; /* offset 0x0A0 */ + unsigned int resv6; + unsigned int l4fwclkctrl; /* offset 0x0A8 */ + unsigned int resv7[85]; + unsigned int l3sclkstctrl; /* offset 0x200 */ + unsigned int resv8[7]; + unsigned int gpmcclkctrl; /* offset 0x220 */ + unsigned int resv9[5]; + unsigned int mcasp0clkctrl; /* offset 0x238 */ + unsigned int resv10; + unsigned int mcasp1clkctrl; /* offset 0x240 */ + unsigned int resv11; + unsigned int mmc2clkctrl; /* offset 0x248 */ + unsigned int resv12[5]; + unsigned int usb0clkctrl; /* offset 0x260 */ + unsigned int resv13[103]; + unsigned int l4lsclkstctrl; /* offset 0x400 */ + unsigned int resv14[7]; + unsigned int l4lsclkctrl; /* offset 0x420 */ + unsigned int resv15; + unsigned int dcan0clkctrl; /* offset 0x428 */ + unsigned int resv16; + unsigned int dcan1clkctrl; /* offset 0x430 */ + unsigned int resv17[13]; + unsigned int elmclkctrl; /* offset 0x468 */ + + unsigned int resv18[3]; + unsigned int gpio1clkctrl; /* offset 0x478 */ + unsigned int resv19; + unsigned int gpio2clkctrl; /* offset 0x480 */ + unsigned int resv20; + unsigned int gpio3clkctrl; /* offset 0x488 */ + unsigned int resv21[7]; + + unsigned int i2c1clkctrl; /* offset 0x4A8 */ + unsigned int resv22; + unsigned int i2c2clkctrl; /* offset 0x4B0 */ + unsigned int resv23[3]; + unsigned int mmc0clkctrl; /* offset 0x4C0 */ + unsigned int resv24; + unsigned int mmc1clkctrl; /* offset 0x4C8 */ + + unsigned int resv25[13]; + unsigned int spi0clkctrl; /* offset 0x500 */ + unsigned int resv26; + unsigned int spi1clkctrl; /* offset 0x508 */ + unsigned int resv27[9]; + unsigned int timer2clkctrl; /* offset 0x530 */ + unsigned int resv28; + unsigned int timer3clkctrl; /* offset 0x538 */ + unsigned int resv29; + unsigned int timer4clkctrl; /* offset 0x540 */ + unsigned int resv30[5]; + unsigned int timer7clkctrl; /* offset 0x558 */ + + unsigned int resv31[9]; + unsigned int uart1clkctrl; /* offset 0x580 */ + unsigned int resv32; + unsigned int uart2clkctrl; /* offset 0x588 */ + unsigned int resv33; + unsigned int uart3clkctrl; /* offset 0x590 */ + unsigned int resv34; + unsigned int uart4clkctrl; /* offset 0x598 */ + unsigned int resv35; + unsigned int uart5clkctrl; /* offset 0x5A0 */ + unsigned int resv36[87]; + + unsigned int emifclkstctrl; /* offset 0x700 */ + unsigned int resv361[7]; + unsigned int emifclkctrl; /* offset 0x720 */ + unsigned int resv37[3]; + unsigned int emiffwclkctrl; /* offset 0x730 */ + unsigned int resv371; + unsigned int otfaemifclkctrl; /* offset 0x738 */ + unsigned int resv38[57]; + unsigned int lcdclkctrl; /* offset 0x820 */ + unsigned int resv39[183]; + unsigned int cpswclkstctrl; /* offset 0xB00 */ + unsigned int resv40[7]; + unsigned int cpgmac0clkctrl; /* offset 0xB20 */ +}; +#endif /* CONFIG_AM43XX */ /* Encapsulating Display pll registers */ struct cm_dpll { diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index 02f5f8a..fa0bbda 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -17,6 +17,8 @@ #include #elif defined(CONFIG_TI814X) #include +#elif defined(CONFIG_AM43XX) +#include #endif /* @@ -45,8 +47,6 @@ #define EMIF4_1_CFG_BASE 0x4D000000 /* PLL related registers */ -#define CM_PER 0x44E00000 -#define CM_WKUP 0x44E00400 #define CM_DPLL 0x44E00500 #define CM_DEVICE 0x44E00700 #define CM_RTC 0x44E00800 @@ -74,8 +74,4 @@ /* CPSW Config space */ #define CPSW_BASE 0x4A100000 -/* OTG */ -#define USB0_OTG_BASE 0x47401000 -#define USB1_OTG_BASE 0x47401800 - #endif /* __AM33XX_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h index 432f0c7..5297c63 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h @@ -28,6 +28,11 @@ /* PRCM Base Address */ #define PRCM_BASE 0x44E00000 +#define CM_PER 0x44E00000 +#define CM_WKUP 0x44E00400 + +#define PRM_RSTCTRL (PRCM_BASE + 0x0F00) +#define PRM_RSTST (PRM_RSTCTRL + 8) /* VTP Base address */ #define VTP0_CTRL_ADDR 0x44E10E0C @@ -43,4 +48,8 @@ /* RTC base address */ #define RTC_BASE 0x44E3E000 +/* OTG */ +#define USB0_OTG_BASE 0x47401000 +#define USB1_OTG_BASE 0x47401800 + #endif /* __AM33XX_HARDWARE_AM33XX_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h new file mode 100644 index 0000000..d4d5c41 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -0,0 +1,51 @@ +/* + * hardware_am43xx.h + * + * AM43xx hardware specific header + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __AM43XX_HARDWARE_AM43XX_H +#define __AM43XX_HARDWARE_AM43XX_H + +/* Module base addresses */ + +/* UART Base Address */ +#define UART0_BASE 0x44E09000 + +/* GPIO Base address */ +#define GPIO2_BASE 0x481AC000 + +/* Watchdog Timer */ +#define WDT_BASE 0x44E35000 + +/* Control Module Base Address */ +#define CTRL_BASE 0x44E10000 +#define CTRL_DEVICE_BASE 0x44E10600 + +/* PRCM Base Address */ +#define PRCM_BASE 0x44DF0000 +#define CM_WKUP 0x44DF2800 +#define CM_PER 0x44DF8800 + +#define PRM_RSTCTRL (PRCM_BASE + 0x4000) +#define PRM_RSTST (PRM_RSTCTRL + 4) + +/* VTP Base address */ +#define VTP0_CTRL_ADDR 0x44E10E0C + +/* DDR Base address */ +#define DDR_PHY_CMD_ADDR 0x44E12000 +#define DDR_PHY_DATA_ADDR 0x44E120C8 +#define DDR_DATA_REGS_NR 2 + +/* CPSW Config space */ +#define CPSW_MDIO_BASE 0x4A101000 + +/* RTC base address */ +#define RTC_BASE 0x44E3E000 + +#endif /* __AM43XX_HARDWARE_AM43XX_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h index 451d935..1ad8cb1 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h @@ -25,6 +25,11 @@ /* PRCM Base Address */ #define PRCM_BASE 0x48180000 +#define CM_PER 0x44E00000 +#define CM_WKUP 0x44E00400 + +#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) +#define PRM_RSTST (PRM_RSTCTRL + 8) /* PLL Subsystem Base Address */ #define PLL_SUBSYS_BASE 0x481C5000 @@ -43,4 +48,8 @@ /* RTC base address */ #define RTC_BASE 0x480C0000 +/* OTG */ +#define USB0_OTG_BASE 0x47401000 +#define USB1_OTG_BASE 0x47401800 + #endif /* __AM33XX_HARDWARE_TI814X_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h index 1c6b65f..f760d84 100644 --- a/arch/arm/include/asm/arch-am33xx/mux.h +++ b/arch/arm/include/asm/arch-am33xx/mux.h @@ -23,6 +23,8 @@ #include #elif defined(CONFIG_TI814X) #include +#elif defined(CONFIG_AM43XX) +#include #endif struct module_pin_mux { diff --git a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h new file mode 100644 index 0000000..0206912 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h @@ -0,0 +1,142 @@ +/* + * mux_am43xx.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MUX_AM43XX_H_ +#define _MUX_AM43XX_H_ + +#include +#include + +#define MUX_CFG(value, offset) \ + __raw_writel(value, (CTRL_BASE + offset)); + +/* PAD Control Fields */ +#define SLEWCTRL (0x1 << 19) +#define RXACTIVE (0x1 << 18) +#define PULLDOWN_EN (0x0 << 17) /* Pull Down Selection */ +#define PULLUP_EN (0x1 << 17) /* Pull Up Selection */ +#define PULLUDEN (0x0 << 16) /* Pull up/down enable */ +#define PULLUDDIS (0x1 << 16) /* Pull up/down disable */ +#define MODE(val) val /* used for Readability */ + +/* + * PAD CONTROL OFFSETS + * Field names corresponds to the pad signal name + */ +struct pad_signals { + int gpmc_ad0; + int gpmc_ad1; + int gpmc_ad2; + int gpmc_ad3; + int gpmc_ad4; + int gpmc_ad5; + int gpmc_ad6; + int gpmc_ad7; + int gpmc_ad8; + int gpmc_ad9; + int gpmc_ad10; + int gpmc_ad11; + int gpmc_ad12; + int gpmc_ad13; + int gpmc_ad14; + int gpmc_ad15; + int gpmc_a0; + int gpmc_a1; + int gpmc_a2; + int gpmc_a3; + int gpmc_a4; + int gpmc_a5; + int gpmc_a6; + int gpmc_a7; + int gpmc_a8; + int gpmc_a9; + int gpmc_a10; + int gpmc_a11; + int gpmc_wait0; + int gpmc_wpn; + int gpmc_be1n; + int gpmc_csn0; + int gpmc_csn1; + int gpmc_csn2; + int gpmc_csn3; + int gpmc_clk; + int gpmc_advn_ale; + int gpmc_oen_ren; + int gpmc_wen; + int gpmc_be0n_cle; + int lcd_data0; + int lcd_data1; + int lcd_data2; + int lcd_data3; + int lcd_data4; + int lcd_data5; + int lcd_data6; + int lcd_data7; + int lcd_data8; + int lcd_data9; + int lcd_data10; + int lcd_data11; + int lcd_data12; + int lcd_data13; + int lcd_data14; + int lcd_data15; + int lcd_vsync; + int lcd_hsync; + int lcd_pclk; + int lcd_ac_bias_en; + int mmc0_dat3; + int mmc0_dat2; + int mmc0_dat1; + int mmc0_dat0; + int mmc0_clk; + int mmc0_cmd; + int mii1_col; + int mii1_crs; + int mii1_rxerr; + int mii1_txen; + int mii1_rxdv; + int mii1_txd3; + int mii1_txd2; + int mii1_txd1; + int mii1_txd0; + int mii1_txclk; + int mii1_rxclk; + int mii1_rxd3; + int mii1_rxd2; + int mii1_rxd1; + int mii1_rxd0; + int rmii1_refclk; + int mdio_data; + int mdio_clk; + int spi0_sclk; + int spi0_d0; + int spi0_d1; + int spi0_cs0; + int spi0_cs1; + int ecap0_in_pwm0_out; + int uart0_ctsn; + int uart0_rtsn; + int uart0_rxd; + int uart0_txd; + int uart1_ctsn; + int uart1_rtsn; + int uart1_rxd; + int uart1_txd; + int i2c0_sda; + int i2c0_scl; + int mcasp0_aclkx; + int mcasp0_fsx; + int mcasp0_axr0; + int mcasp0_ahclkr; + int mcasp0_aclkr; + int mcasp0_fsr; + int mcasp0_axr1; + int mcasp0_ahclkx; +}; + +#endif /* _MUX_AM43XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 66c61e5..d54cf5e 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -15,11 +15,6 @@ #ifndef _OMAP_H_ #define _OMAP_H_ -/* - * Non-secure SRAM Addresses - * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE - * at 0x40304000(EMU base) so that our code works for both EMU and GP - */ #ifdef CONFIG_AM33XX #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40310000 @@ -28,5 +23,9 @@ #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 #define SRAM_SCRATCH_SPACE_ADDR 0x4031B800 +#elif defined(CONFIG_AM43XX) +#define NON_SECURE_SRAM_START 0x402F0400 +#define NON_SECURE_SRAM_END 0x40340000 +#define SRAM_SCRATCH_SPACE_ADDR 0x4033C000 #endif #endif diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index e428512..570f45c 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -9,7 +9,7 @@ #define BOOT_DEVICE_XIP 2 #define BOOT_DEVICE_NAND 5 -#ifdef CONFIG_AM33XX +#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) #define BOOT_DEVICE_MMC1 8 #define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */ #elif defined(CONFIG_TI814X) @@ -22,7 +22,7 @@ #define BOOT_DEVICE_CPGMAC 70 #define BOOT_DEVICE_MMC2_2 0xFF -#ifdef CONFIG_AM33XX +#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 #define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 #elif defined(CONFIG_TI814X) -- cgit v1.1 From 3b34ac13fe1e841e8f4ab00dda6a5a7df0568710 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 30 Jul 2013 11:36:29 +0530 Subject: ARM: AM43xx: clocks: Add dpll and clock data Add dpll and clock data for AM43xx Signed-off-by: Lokesh Vutla --- arch/arm/cpu/armv7/am33xx/Makefile | 7 +- arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 110 +++++++++++++++++++++++++++++++ 2 files changed, 116 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/am33xx/clock_am43xx.c (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile index 7fd21af..bd8e752 100644 --- a/arch/arm/cpu/armv7/am33xx/Makefile +++ b/arch/arm/cpu/armv7/am33xx/Makefile @@ -10,7 +10,12 @@ LIB = $(obj)lib$(SOC).o COBJS-$(CONFIG_AM33XX) += clock_am33xx.o COBJS-$(CONFIG_TI814X) += clock_ti814x.o -COBJS-$(CONFIG_AM33XX) += clock.o +COBJS-$(CONFIG_AM43XX) += clock_am43xx.o + +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),) +COBJS += clock.o +endif + COBJS += sys_info.o COBJS += mem.o COBJS += ddr.o diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c new file mode 100644 index 0000000..c4890f2 --- /dev/null +++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c @@ -0,0 +1,110 @@ +/* + * clock_am43xx.c + * + * clocks for AM43XX based boards + * Derived from AM33XX based boards + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; +struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP; + +const struct dpll_regs dpll_mpu_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x560, + .cm_idlest_dpll = CM_WKUP + 0x564, + .cm_clksel_dpll = CM_WKUP + 0x56c, + .cm_div_m2_dpll = CM_WKUP + 0x570, +}; + +const struct dpll_regs dpll_core_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x520, + .cm_idlest_dpll = CM_WKUP + 0x524, + .cm_clksel_dpll = CM_WKUP + 0x52C, + .cm_div_m4_dpll = CM_WKUP + 0x538, + .cm_div_m5_dpll = CM_WKUP + 0x53C, + .cm_div_m6_dpll = CM_WKUP + 0x540, +}; + +const struct dpll_regs dpll_per_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x5E0, + .cm_idlest_dpll = CM_WKUP + 0x5E4, + .cm_clksel_dpll = CM_WKUP + 0x5EC, + .cm_div_m2_dpll = CM_WKUP + 0x5F0, +}; + +const struct dpll_regs dpll_ddr_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x5A0, + .cm_idlest_dpll = CM_WKUP + 0x5A4, + .cm_clksel_dpll = CM_WKUP + 0x5AC, + .cm_div_m2_dpll = CM_WKUP + 0x5B0, +}; + +const struct dpll_params dpll_mpu = { + -1, -1, -1, -1, -1, -1, -1}; +const struct dpll_params dpll_core = { + -1, -1, -1, -1, -1, -1, -1}; +const struct dpll_params dpll_per = { + -1, -1, -1, -1, -1, -1, -1}; + +void setup_clocks_for_console(void) +{ + /* Do not add any spl_debug prints in this function */ + clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, + CD_CLKCTRL_CLKTRCTRL_SW_WKUP << + CD_CLKCTRL_CLKTRCTRL_SHIFT); + + /* Enable UART0 */ + clrsetbits_le32(&cmwkup->wkup_uart0ctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); +} + +void enable_basic_clocks(void) +{ + u32 *const clk_domains[] = { + &cmper->l3clkstctrl, + &cmper->l3sclkstctrl, + &cmper->l4lsclkstctrl, + &cmwkup->wkclkstctrl, + &cmper->emifclkstctrl, + 0 + }; + + u32 *const clk_modules_explicit_en[] = { + &cmper->l3clkctrl, + &cmper->l4lsclkctrl, + &cmper->l4fwclkctrl, + &cmwkup->wkl4wkclkctrl, + &cmper->l3instrclkctrl, + &cmper->l4hsclkctrl, + &cmwkup->wkgpio0clkctrl, + &cmwkup->wkctrlclkctrl, + &cmper->timer2clkctrl, + &cmper->gpmcclkctrl, + &cmper->elmclkctrl, + &cmper->mmc0clkctrl, + &cmper->mmc1clkctrl, + &cmwkup->wkup_i2c0ctrl, + &cmper->gpio1clkctrl, + &cmper->gpio2clkctrl, + &cmper->gpio3clkctrl, + &cmper->i2c1clkctrl, + &cmper->emiffwclkctrl, + &cmper->emifclkctrl, + &cmper->otfaemifclkctrl, + 0 + }; + + do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); +} -- cgit v1.1 From 806d2792472436a523084775190a11e9d8315275 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 30 Jul 2013 11:36:30 +0530 Subject: ARM: OMAP: Add CONFIG_OMAP_COMMON Adding a new CONFIG_OMAP_COMMON which is included by all boards that needs to build cpu/armv7/omap-common folder. Signed-off-by: Lokesh Vutla --- arch/arm/config.mk | 2 +- arch/arm/cpu/armv7/omap-common/Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 540a119..ce3903b 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -8,7 +8,7 @@ CROSS_COMPILE ?= arm-linux- ifndef CONFIG_STANDALONE_LOAD_ADDR -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) +ifneq ($(CONFIG_OMAP_COMMON),) CONFIG_STANDALONE_LOAD_ADDR = 0x80300000 else CONFIG_STANDALONE_LOAD_ADDR = 0xc100000 diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 98f29d4..75b3753 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -21,7 +21,7 @@ COBJS += vc.o COBJS += abb.o endif -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) +ifeq ($(CONFIG_OMAP34XX),) COBJS += boot-common.o SOBJS += lowlevel_init.o endif -- cgit v1.1 From 571804086fe6c85c302db72b096cd6796a653e49 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 30 Jul 2013 11:36:31 +0530 Subject: ARM: AM43xx: Add build support Add AM43xx support in the required places Signed-off-by: Lokesh Vutla --- arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/omap-common/boot-common.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 2ba88d0..8f27507 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -16,7 +16,7 @@ COBJS += cache_v7.o COBJS += cpu.o COBJS += syslib.o -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI814X),) +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI814X),) SOBJS += lowlevel_init.o endif diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 6b9ce36..6b4772b 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -40,7 +40,8 @@ void save_omap_boot_params(void) if ((boot_device >= MMC_BOOT_DEVICES_START) && (boot_device <= MMC_BOOT_DEVICES_END)) { -#if !defined(CONFIG_AM33XX) && !defined(CONFIG_TI81XX) +#if !defined(CONFIG_AM33XX) && !defined(CONFIG_TI81XX) && \ + !defined(CONFIG_AM43XX) if ((omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) { gd->arch.omap_boot_params.omap_bootmode = -- cgit v1.1 From a704a6d615179a25f556c99d31cbc4ee366ffb54 Mon Sep 17 00:00:00 2001 From: Naumann Andreas Date: Tue, 9 Jul 2013 09:43:17 +0200 Subject: ARM: omap3: Implement dpll5 (HSUSB clk) workaround for OMAP36xx/AM/DM37xx according to errata sprz318e. In chapter 'Advisory 2.1 USB Host Clock Drift Causes USB Spec Non-compliance in Certain Configurations' of the TI Errata it is recommended to use certain div/mult values for the DPLL5 clock setup. So far u-boot used the old 34xx values, so I added the errata recommended values specificly for 36xx init only. Also, the FSEL registers exist no longer, so removed them from init. Tested this on a AM3703 board with 19.2MHz oscillator, which previously couldnt lock the dpll5 (kernel complained). As a consequence the EHCI USB port wasnt usable in U-Boot and kernel. With this patch, kernel panics disappear and USB working fine in u-boot and kernel. Signed-off-by: Andreas Naumann [trini: Add extern to Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/omap3/clock.c | 20 +++++++++++++++++++- arch/arm/cpu/armv7/omap3/lowlevel_init.S | 18 ++++++++++++++++++ arch/arm/include/asm/arch-omap3/clock.h | 1 + arch/arm/include/asm/arch-omap3/clocks_omap3.h | 22 ++++++++++++++++++++++ 4 files changed, 60 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index 3acbc9c..e903ed9 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -478,6 +478,24 @@ static void dpll4_init_36xx(u32 sil_index, u32 clk_index) wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY); } +static void dpll5_init_36xx(u32 sil_index, u32 clk_index) +{ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + dpll_param *ptr = (dpll_param *) get_36x_per2_dpll_param(); + + /* Moving it to the right sysclk base */ + ptr = ptr + clk_index; + + /* PER2 DPLL (DPLL5) */ + sr32(&prcm_base->clken2_pll, 0, 3, PLL_STOP); + wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY); + sr32(&prcm_base->clksel5_pll, 0, 5, ptr->m2); /* set M2 (usbtll_fck) */ + sr32(&prcm_base->clksel4_pll, 8, 11, ptr->m); /* set m (11-bit multiplier) */ + sr32(&prcm_base->clksel4_pll, 0, 7, ptr->n); /* set n (7-bit divider)*/ + sr32(&prcm_base->clken2_pll, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY); +} + static void mpu_init_36xx(u32 sil_index, u32 clk_index) { struct prcm *prcm_base = (struct prcm *)PRCM_BASE; @@ -582,7 +600,7 @@ void prcm_init(void) dpll3_init_36xx(0, clk_index); dpll4_init_36xx(0, clk_index); - dpll5_init_34xx(0, clk_index); + dpll5_init_36xx(0, clk_index); iva_init_36xx(0, clk_index); mpu_init_36xx(0, clk_index); diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index bdf74ea..98c3c03 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -464,6 +464,19 @@ per_36x_dpll_param: .word 26000, 432, 12, 9, 16, 9, 4, 3, 1 .word 38400, 360, 15, 9, 16, 5, 4, 3, 1 +per2_36x_dpll_param: +/* 12MHz */ +.word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12 +/* 13MHz */ +.word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13 +/* 19.2MHz */ +.word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2 +/* 26MHz */ +.word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26 +/* 38.4MHz */ +.word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4 + + ENTRY(get_36x_mpu_dpll_param) adr r0, mpu_36x_dpll_param mov pc, lr @@ -483,3 +496,8 @@ ENTRY(get_36x_per_dpll_param) adr r0, per_36x_dpll_param mov pc, lr ENDPROC(get_36x_per_dpll_param) + +ENTRY(get_36x_per2_dpll_param) + adr r0, per2_36x_dpll_param + mov pc, lr +ENDPROC(get_36x_per2_dpll_param) diff --git a/arch/arm/include/asm/arch-omap3/clock.h b/arch/arm/include/asm/arch-omap3/clock.h index da776cf..514839c 100644 --- a/arch/arm/include/asm/arch-omap3/clock.h +++ b/arch/arm/include/asm/arch-omap3/clock.h @@ -61,6 +61,7 @@ extern dpll_param *get_36x_mpu_dpll_param(void); extern dpll_param *get_36x_iva_dpll_param(void); extern dpll_param *get_36x_core_dpll_param(void); extern dpll_param *get_36x_per_dpll_param(void); +extern dpll_param *get_36x_per2_dpll_param(void); extern void *_end_vect, *_start; diff --git a/arch/arm/include/asm/arch-omap3/clocks_omap3.h b/arch/arm/include/asm/arch-omap3/clocks_omap3.h index bf7fa00..df73c4b 100644 --- a/arch/arm/include/asm/arch-omap3/clocks_omap3.h +++ b/arch/arm/include/asm/arch-omap3/clocks_omap3.h @@ -323,4 +323,26 @@ #define PER_36XX_FSEL_38P4 0x07 #define PER_36XX_M2_38P4 0x09 +/* 36XX PER2 DPLL */ + +#define PER2_36XX_M_12 0x50 +#define PER2_36XX_N_12 0x00 +#define PER2_36XX_M2_12 0x08 + +#define PER2_36XX_M_13 0x1BB +#define PER2_36XX_N_13 0x05 +#define PER2_36XX_M2_13 0x08 + +#define PER2_36XX_M_19P2 0x32 +#define PER2_36XX_N_19P2 0x00 +#define PER2_36XX_M2_19P2 0x08 + +#define PER2_36XX_M_26 0x1BB +#define PER2_36XX_N_26 0x0B +#define PER2_36XX_M2_26 0x08 + +#define PER2_36XX_M_38P4 0x19 +#define PER2_36XX_N_38P4 0x00 +#define PER2_36XX_M2_38P4 0x08 + #endif /* endif _CLOCKS_OMAP3_H_ */ -- cgit v1.1 From 2f6af82719723033b35f2bf97e3fe4f65400781f Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 5 Aug 2013 10:49:42 +0900 Subject: ARM: omap24xx: remove remainders of dead board Since Commit 7f5eef9 removed OMAP2420H4 support, arm1136/omap24xx has not been used at all. Signed-off-by: Masahiro Yamada --- arch/arm/cpu/arm1136/omap24xx/Makefile | 31 -------- arch/arm/cpu/arm1136/omap24xx/reset.S | 26 ------- arch/arm/cpu/arm1136/omap24xx/timer.c | 136 --------------------------------- 3 files changed, 193 deletions(-) delete mode 100644 arch/arm/cpu/arm1136/omap24xx/Makefile delete mode 100644 arch/arm/cpu/arm1136/omap24xx/reset.S delete mode 100644 arch/arm/cpu/arm1136/omap24xx/timer.c (limited to 'arch/arm') diff --git a/arch/arm/cpu/arm1136/omap24xx/Makefile b/arch/arm/cpu/arm1136/omap24xx/Makefile deleted file mode 100644 index 7d76d96..0000000 --- a/arch/arm/cpu/arm1136/omap24xx/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).o - -SOBJS = reset.o - -COBJS = timer.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/arm/cpu/arm1136/omap24xx/reset.S b/arch/arm/cpu/arm1136/omap24xx/reset.S deleted file mode 100644 index dd0752b..0000000 --- a/arch/arm/cpu/arm1136/omap24xx/reset.S +++ /dev/null @@ -1,26 +0,0 @@ -/* - * armboot - Startup Code for OMP2420/ARM1136 CPU-core - * - * Copyright (c) 2004 Texas Instruments - * - * Copyright (c) 2001 Marius Gröger - * Copyright (c) 2002 Alex Züpke - * Copyright (c) 2002 Gary Jennejohn - * Copyright (c) 2003 Richard Woodruff - * Copyright (c) 2003 Kshitij - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -.globl reset_cpu -reset_cpu: - ldr r1, rstctl /* get addr for global reset reg */ - mov r3, #0x2 /* full reset pll+mpu */ - str r3, [r1] /* force reset */ - mov r0, r0 -_loop_forever: - b _loop_forever -rstctl: - .word PM_RSTCTRL_WKUP diff --git a/arch/arm/cpu/arm1136/omap24xx/timer.c b/arch/arm/cpu/arm1136/omap24xx/timer.c deleted file mode 100644 index b1eef27d..0000000 --- a/arch/arm/cpu/arm1136/omap24xx/timer.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments - * Richard Woodruff - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#define TIMER_CLOCK (CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV)) -#define TIMER_LOAD_VAL 0 - -/* macro to read the 32 bit timer */ -#define READ_TIMER readl(CONFIG_SYS_TIMERBASE+TCRR) \ - / (TIMER_CLOCK / CONFIG_SYS_HZ) - -DECLARE_GLOBAL_DATA_PTR; - -int timer_init (void) -{ - int32_t val; - - /* Start the counter ticking up */ - *((int32_t *) (CONFIG_SYS_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow*/ - val = (CONFIG_SYS_PTV << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/ - *((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val; /* start timer */ - - /* reset time */ - gd->arch.lastinc = READ_TIMER; /* capture current incrementer value */ - gd->arch.tbl = 0; /* start "advancing" time stamp */ - - return(0); -} -/* - * timer without interrupts - */ -ulong get_timer (ulong base) -{ - return get_timer_masked () - base; -} - -/* delay x useconds AND preserve advance timestamp value */ -void __udelay (unsigned long usec) -{ - ulong tmo, tmp; - - if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ - tmo /= 1000; /* finish normalize. */ - } else { /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*1000); - } - - tmp = get_timer (0); /* get current timestamp */ - if ((tmo + tmp + 1) < tmp) { /* if setting this forward will roll */ - /* time stamp, then reset time */ - gd->arch.lastinc = READ_TIMER; /* capture incrementer value */ - gd->arch.tbl = 0; /* start time stamp */ - } else { - tmo += tmp; /* else, set advancing stamp wake up time */ - } - while (get_timer_masked () < tmo)/* loop till event */ - /*NOP*/; -} - -ulong get_timer_masked (void) -{ - ulong now = READ_TIMER; /* current tick value */ - - if (now >= gd->arch.lastinc) { /* normal mode (non roll) */ - /* move stamp fordward with absoulte diff ticks */ - gd->arch.tbl += (now - gd->arch.lastinc); - } else { - /* we have rollover of incrementer */ - gd->arch.tbl += ((0xFFFFFFFF / (TIMER_CLOCK / CONFIG_SYS_HZ)) - - gd->arch.lastinc) + now; - } - gd->arch.lastinc = now; - return gd->arch.tbl; -} - -/* waits specified delay value and resets timestamp */ -void udelay_masked (unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ - tmo /= 1000; /* finish normalize. */ - } else { /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*1000); - } - endtime = get_timer_masked () + tmo; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - ulong tbclk; - tbclk = CONFIG_SYS_HZ; - return tbclk; -} -- cgit v1.1 From 0474fb0e2b22a831cf47848b21bdb3e152c108bc Mon Sep 17 00:00:00 2001 From: Taras Kondratiuk Date: Tue, 6 Aug 2013 16:16:50 +0300 Subject: omap: emif: Set initial DDR PHY config first Commit "OMAP5: emif/ddr: Change emif settings as required for ES1.0 silicon" (f40107345cbcd6e0d1747eda45e76c4e2a6df0db) changed sequence to set final DDR PHY config register value at the beginning. Looks like it was made by mistake and should be reverted. Signed-off-by: Taras Kondratiuk --- arch/arm/cpu/armv7/omap-common/emif-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index ece3655..b0e1caa 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -153,7 +153,7 @@ static void lpddr2_init(u32 base, const struct emif_regs *regs) * un-locked frequency & default RL */ writel(regs->sdram_config_init, &emif->emif_sdram_config); - writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); + writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); do_ext_phy_settings(base, regs); -- cgit v1.1 From ec101fdb8d419975c7722c1d23470d9674350c3c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 9 Aug 2013 11:22:15 -0400 Subject: arm: spl: For Falcon Mode, set a default machid of ~0 With device trees, boards do not always set CONFIG_MACH_TYPE now, so we must not rely on this define being set. The kernel uses ~0 to see if we have a valid machine number or not, so set that as the default, invalid machine, id and only fix if CONFIG_MACH_TYPE is set. Acked-by: Dan Murphy Tested-by: Heiko Schocher Cc: Albert ARIBAUD Signed-off-by: Tom Rini --- arch/arm/lib/spl.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c index 583bdb3..26d0be4 100644 --- a/arch/arm/lib/spl.c +++ b/arch/arm/lib/spl.c @@ -45,12 +45,17 @@ void __weak board_init_f(ulong dummy) #ifdef CONFIG_SPL_OS_BOOT void __noreturn jump_to_image_linux(void *arg) { + unsigned long machid = 0xffffffff; +#ifdef CONFIG_MACH_TYPE + machid = CONFIG_MACH_TYPE; +#endif + debug("Entering kernel arg pointer: 0x%p\n", arg); typedef void (*image_entry_arg_t)(int, int, void *) __attribute__ ((noreturn)); image_entry_arg_t image_entry = (image_entry_arg_t) spl_image.entry_point; cleanup_before_linux(); - image_entry(0, CONFIG_MACH_TYPE, arg); + image_entry(0, machid, arg); } #endif -- cgit v1.1 From 78056717e3a3216ff136ac8ce7e7355f593856e8 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 5 Aug 2013 16:00:35 +0200 Subject: arm/davinci/da850: add uart0_pins_rtscts and RMII_MHz_50_CLK in emac_pins_rmii pinmux Signed-off-by: Heiko Schocher Cc: Tom Rini --- arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c | 6 ++++++ arch/arm/include/asm/arch-davinci/pinmux_defs.h | 3 ++- 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c index f603f2f..6105f63 100644 --- a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c +++ b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c @@ -28,6 +28,11 @@ const struct pinmux_config uart0_pins_txrx[] = { { pinmux(3), 2, 5 }, /* UART0_TXD */ }; +const struct pinmux_config uart0_pins_rtscts[] = { + { pinmux(3), 2, 6 }, + { pinmux(3), 2, 7 }, +}; + const struct pinmux_config uart1_pins_txrx[] = { { pinmux(4), 2, 6 }, /* UART1_RXD */ { pinmux(4), 2, 7 }, /* UART1_TXD */ @@ -51,6 +56,7 @@ const struct pinmux_config emac_pins_rmii[] = { { pinmux(14), 8, 5 }, /* RMII_RXD[1] */ { pinmux(14), 8, 6 }, /* RMII_RXD[0] */ { pinmux(14), 8, 7 }, /* RMII_RXER */ + { pinmux(15), 0, 0 }, /* RMII_MHz_50_CLK */ { pinmux(15), 8, 1 }, /* RMII_CRS_DV */ }; diff --git a/arch/arm/include/asm/arch-davinci/pinmux_defs.h b/arch/arm/include/asm/arch-davinci/pinmux_defs.h index 4d45799..2d82af5 100644 --- a/arch/arm/include/asm/arch-davinci/pinmux_defs.h +++ b/arch/arm/include/asm/arch-davinci/pinmux_defs.h @@ -23,12 +23,13 @@ extern const struct pinmux_config spi1_pins_scs0[1]; /* UART pin muxer settings */ extern const struct pinmux_config uart0_pins_txrx[2]; +extern const struct pinmux_config uart0_pins_rtscts[2]; extern const struct pinmux_config uart1_pins_txrx[2]; extern const struct pinmux_config uart2_pins_txrx[2]; extern const struct pinmux_config uart2_pins_rtscts[2]; /* EMAC pin muxer settings*/ -extern const struct pinmux_config emac_pins_rmii[7]; +extern const struct pinmux_config emac_pins_rmii[8]; extern const struct pinmux_config emac_pins_rmii_clk_source[1]; extern const struct pinmux_config emac_pins_mii[15]; extern const struct pinmux_config emac_pins_mdio[2]; -- cgit v1.1 From 9c8deaeeb79523d45d836c730c59c857f53b5f65 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 5 Aug 2013 16:00:37 +0200 Subject: arm, da850: enable the correct uart in arch_cpu_init() in arch_cpu_init() uart2 is fix enabled, without reference the setting from CONFIG_SYS_NS16550_COM1. Use the setting from CONFIG_SYS_NS16550_COM1 for enabling the console. Signed-off-by: Heiko Schocher Cc: Albert ARIBAUD Cc: Tom Rini Cc: Christian Riesch --- arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c index f6bf1ef..a3bbbb8 100644 --- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c +++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c @@ -299,7 +299,11 @@ int arch_cpu_init(void) */ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | DAVINCI_UART_PWREMU_MGMT_UTRST), +#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE) + &davinci_uart0_ctrl_regs->pwremu_mgmt); +#else &davinci_uart2_ctrl_regs->pwremu_mgmt); +#endif #if defined(CONFIG_SYS_DA850_DDR_INIT) da850_ddr_setup(); -- cgit v1.1 From 9ed6e41239e17c97d786219b5ffca4a8a118c71f Mon Sep 17 00:00:00 2001 From: TENART Antoine Date: Tue, 2 Jul 2013 12:05:58 +0200 Subject: Prepare for TI816X : reuse existing code from TI814X Rename some CONFIG_TI814X to a more generic CONFIG_TI81XX Signed-off-by: Antoine Tenart [trini: Adapt for CONFIG_OMAP_COMMON changes, AM43XX] Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/include/asm/arch-am33xx/omap.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 8f27507..b723e22 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -16,7 +16,7 @@ COBJS += cache_v7.o COBJS += cpu.o COBJS += syslib.o -ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI814X),) +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX),) SOBJS += lowlevel_init.o endif diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index d54cf5e..1f84311 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -19,7 +19,7 @@ #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40310000 #define SRAM_SCRATCH_SPACE_ADDR 0x4030C000 -#elif defined(CONFIG_TI814X) +#elif defined(CONFIG_TI81XX) #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 #define SRAM_SCRATCH_SPACE_ADDR 0x4031B800 -- cgit v1.1 From dcf846d5dae75b81eccce46c577fd3957e73d474 Mon Sep 17 00:00:00 2001 From: TENART Antoine Date: Tue, 2 Jul 2013 12:05:59 +0200 Subject: Add TI816X support Signed-off-by: Antoine Tenart [trini: Fix warnings about vtp things in emif4.c, adapt AM43XX] Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/am33xx/Makefile | 1 + arch/arm/cpu/armv7/am33xx/clock_ti814x.c | 95 ----- arch/arm/cpu/armv7/am33xx/clock_ti816x.c | 445 +++++++++++++++++++++ arch/arm/cpu/armv7/am33xx/emif4.c | 6 + arch/arm/include/asm/arch-am33xx/clock.h | 4 + arch/arm/include/asm/arch-am33xx/clock_ti81xx.h | 142 +++++++ arch/arm/include/asm/arch-am33xx/ddr_defs.h | 35 +- arch/arm/include/asm/arch-am33xx/hardware.h | 10 +- arch/arm/include/asm/arch-am33xx/hardware_am33xx.h | 6 + arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 3 + arch/arm/include/asm/arch-am33xx/hardware_ti814x.h | 6 + arch/arm/include/asm/arch-am33xx/hardware_ti816x.h | 61 +++ arch/arm/include/asm/arch-am33xx/mmc_host_def.h | 3 + arch/arm/include/asm/arch-am33xx/mux.h | 2 + arch/arm/include/asm/arch-am33xx/mux_ti816x.h | 363 +++++++++++++++++ arch/arm/include/asm/arch-am33xx/spl.h | 11 +- 16 files changed, 1076 insertions(+), 117 deletions(-) create mode 100644 arch/arm/cpu/armv7/am33xx/clock_ti816x.c create mode 100644 arch/arm/include/asm/arch-am33xx/clock_ti81xx.h create mode 100644 arch/arm/include/asm/arch-am33xx/hardware_ti816x.h create mode 100644 arch/arm/include/asm/arch-am33xx/mux_ti816x.h (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile index bd8e752..f6a297c 100644 --- a/arch/arm/cpu/armv7/am33xx/Makefile +++ b/arch/arm/cpu/armv7/am33xx/Makefile @@ -16,6 +16,7 @@ ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),) COBJS += clock.o endif +COBJS-$(CONFIG_TI816X) += clock_ti816x.o COBJS += sys_info.o COBJS += mem.o COBJS += ddr.o diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c index 93c7f7b..ef14f47 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c +++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c @@ -100,103 +100,8 @@ struct ad_pll { #define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0) -/* PRCM */ #define ENET_CLKCTRL_CMPL 0x30000 -#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500) - -struct cm_def { - unsigned int resv0[2]; - unsigned int l3fastclkstctrl; - unsigned int resv1[1]; - unsigned int pciclkstctrl; - unsigned int resv2[1]; - unsigned int ducaticlkstctrl; - unsigned int resv3[1]; - unsigned int emif0clkctrl; - unsigned int emif1clkctrl; - unsigned int dmmclkctrl; - unsigned int fwclkctrl; - unsigned int resv4[10]; - unsigned int usbclkctrl; - unsigned int resv5[1]; - unsigned int sataclkctrl; - unsigned int resv6[4]; - unsigned int ducaticlkctrl; - unsigned int pciclkctrl; -}; - -#define CM_ALWON_BASE (PRCM_BASE + 0x1400) - -struct cm_alwon { - unsigned int l3slowclkstctrl; - unsigned int ethclkstctrl; - unsigned int l3medclkstctrl; - unsigned int mmu_clkstctrl; - unsigned int mmucfg_clkstctrl; - unsigned int ocmc0clkstctrl; - unsigned int vcpclkstctrl; - unsigned int mpuclkstctrl; - unsigned int sysclk4clkstctrl; - unsigned int sysclk5clkstctrl; - unsigned int sysclk6clkstctrl; - unsigned int rtcclkstctrl; - unsigned int l3fastclkstctrl; - unsigned int resv0[67]; - unsigned int mcasp0clkctrl; - unsigned int mcasp1clkctrl; - unsigned int mcasp2clkctrl; - unsigned int mcbspclkctrl; - unsigned int uart0clkctrl; - unsigned int uart1clkctrl; - unsigned int uart2clkctrl; - unsigned int gpio0clkctrl; - unsigned int gpio1clkctrl; - unsigned int i2c0clkctrl; - unsigned int i2c1clkctrl; - unsigned int mcasp345clkctrl; - unsigned int atlclkctrl; - unsigned int mlbclkctrl; - unsigned int pataclkctrl; - unsigned int resv1[1]; - unsigned int uart3clkctrl; - unsigned int uart4clkctrl; - unsigned int uart5clkctrl; - unsigned int wdtimerclkctrl; - unsigned int spiclkctrl; - unsigned int mailboxclkctrl; - unsigned int spinboxclkctrl; - unsigned int mmudataclkctrl; - unsigned int resv2[2]; - unsigned int mmucfgclkctrl; - unsigned int resv3[2]; - unsigned int ocmc0clkctrl; - unsigned int vcpclkctrl; - unsigned int resv4[2]; - unsigned int controlclkctrl; - unsigned int resv5[2]; - unsigned int gpmcclkctrl; - unsigned int ethernet0clkctrl; - unsigned int ethernet1clkctrl; - unsigned int mpuclkctrl; - unsigned int debugssclkctrl; - unsigned int l3clkctrl; - unsigned int l4hsclkctrl; - unsigned int l4lsclkctrl; - unsigned int rtcclkctrl; - unsigned int tpccclkctrl; - unsigned int tptc0clkctrl; - unsigned int tptc1clkctrl; - unsigned int tptc2clkctrl; - unsigned int tptc3clkctrl; - unsigned int resv7[4]; - unsigned int dcan01clkctrl; - unsigned int mmchs0clkctrl; - unsigned int mmchs1clkctrl; - unsigned int mmchs2clkctrl; - unsigned int custefuseclkctrl; -}; - #define SATA_PLL_BASE (CTRL_BASE + 0x0720) struct sata_pll { diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti816x.c b/arch/arm/cpu/armv7/am33xx/clock_ti816x.c new file mode 100644 index 0000000..ace4a5a --- /dev/null +++ b/arch/arm/cpu/armv7/am33xx/clock_ti816x.c @@ -0,0 +1,445 @@ +/* + * clock_ti816x.c + * + * Clocks for TI816X based boards + * + * Copyright (C) 2013, Adeneo Embedded + * Antoine Tenart, + * + * Based on TI-PSP-04.00.02.14 : + * + * Copyright (C) 2009, Texas Instruments, Incorporated + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define CM_PLL_BASE (CTRL_BASE + 0x0400) + +/* Main PLL */ +#define MAIN_N 64 +#define MAIN_P 0x1 +#define MAIN_INTFREQ1 0x8 +#define MAIN_FRACFREQ1 0x800000 +#define MAIN_MDIV1 0x2 +#define MAIN_INTFREQ2 0xE +#define MAIN_FRACFREQ2 0x0 +#define MAIN_MDIV2 0x1 +#define MAIN_INTFREQ3 0x8 +#define MAIN_FRACFREQ3 0xAAAAB0 +#define MAIN_MDIV3 0x3 +#define MAIN_INTFREQ4 0x9 +#define MAIN_FRACFREQ4 0x55554F +#define MAIN_MDIV4 0x3 +#define MAIN_INTFREQ5 0x9 +#define MAIN_FRACFREQ5 0x374BC6 +#define MAIN_MDIV5 0xC +#define MAIN_MDIV6 0x48 +#define MAIN_MDIV7 0x4 + +/* DDR PLL */ +#if defined(CONFIG_TI816X_DDR_PLL_400) /* 400 MHz */ +#define DDR_N 59 +#define DDR_P 0x1 +#define DDR_MDIV1 0x4 +#define DDR_INTFREQ2 0x8 +#define DDR_FRACFREQ2 0xD99999 +#define DDR_MDIV2 0x1E +#define DDR_INTFREQ3 0x8 +#define DDR_FRACFREQ3 0x0 +#define DDR_MDIV3 0x4 +#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ4 0x0 +#define DDR_MDIV4 0x4 +#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ5 0x0 +#define DDR_MDIV5 0x4 +#elif defined(CONFIG_TI816X_DDR_PLL_531) /* 531 MHz */ +#define DDR_N 59 +#define DDR_P 0x1 +#define DDR_MDIV1 0x3 +#define DDR_INTFREQ2 0x8 +#define DDR_FRACFREQ2 0xD99999 +#define DDR_MDIV2 0x1E +#define DDR_INTFREQ3 0x8 +#define DDR_FRACFREQ3 0x0 +#define DDR_MDIV3 0x4 +#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ4 0x0 +#define DDR_MDIV4 0x4 +#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ5 0x0 +#define DDR_MDIV5 0x4 +#elif defined(CONFIG_TI816X_DDR_PLL_675) /* 675 MHz */ +#define DDR_N 50 +#define DDR_P 0x1 +#define DDR_MDIV1 0x2 +#define DDR_INTFREQ2 0x9 +#define DDR_FRACFREQ2 0x0 +#define DDR_MDIV2 0x19 +#define DDR_INTFREQ3 0x13 +#define DDR_FRACFREQ3 0x800000 +#define DDR_MDIV3 0x2 +#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ4 0x0 +#define DDR_MDIV4 0x4 +#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ5 0x0 +#define DDR_MDIV5 0x4 +#elif defined(CONFIG_TI816X_DDR_PLL_796) /* 796 MHz */ +#define DDR_N 59 +#define DDR_P 0x1 +#define DDR_MDIV1 0x2 +#define DDR_INTFREQ2 0x8 +#define DDR_FRACFREQ2 0xD99999 +#define DDR_MDIV2 0x1E +#define DDR_INTFREQ3 0x8 +#define DDR_FRACFREQ3 0x0 +#define DDR_MDIV3 0x4 +#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ4 0x0 +#define DDR_MDIV4 0x4 +#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ +#define DDR_FRACFREQ5 0x0 +#define DDR_MDIV5 0x4 +#endif + +#define CONTROL_STATUS (CTRL_BASE + 0x40) +#define DDR_RCD (CTRL_BASE + 0x070C) +#define CM_TIMER1_CLKSEL (PRCM_BASE + 0x390) +#define DMM_PAT_BASE_ADDR (DMM_BASE + 0x420) +#define CM_ALWON_CUST_EFUSE_CLKCTRL (PRCM_BASE + 0x1628) + +#define INTCPS_SYSCONFIG 0x48200010 +#define CM_SYSCLK10_CLKSEL 0x48180324 + +struct cm_pll { + unsigned int mainpll_ctrl; /* offset 0x400 */ + unsigned int mainpll_pwd; + unsigned int mainpll_freq1; + unsigned int mainpll_div1; + unsigned int mainpll_freq2; + unsigned int mainpll_div2; + unsigned int mainpll_freq3; + unsigned int mainpll_div3; + unsigned int mainpll_freq4; + unsigned int mainpll_div4; + unsigned int mainpll_freq5; + unsigned int mainpll_div5; + unsigned int resv0[1]; + unsigned int mainpll_div6; + unsigned int resv1[1]; + unsigned int mainpll_div7; + unsigned int ddrpll_ctrl; /* offset 0x440 */ + unsigned int ddrpll_pwd; + unsigned int resv2[1]; + unsigned int ddrpll_div1; + unsigned int ddrpll_freq2; + unsigned int ddrpll_div2; + unsigned int ddrpll_freq3; + unsigned int ddrpll_div3; + unsigned int ddrpll_freq4; + unsigned int ddrpll_div4; + unsigned int ddrpll_freq5; + unsigned int ddrpll_div5; + unsigned int videopll_ctrl; /* offset 0x470 */ + unsigned int videopll_pwd; + unsigned int videopll_freq1; + unsigned int videopll_div1; + unsigned int videopll_freq2; + unsigned int videopll_div2; + unsigned int videopll_freq3; + unsigned int videopll_div3; + unsigned int resv3[4]; + unsigned int audiopll_ctrl; /* offset 0x4A0 */ + unsigned int audiopll_pwd; + unsigned int resv4[2]; + unsigned int audiopll_freq2; + unsigned int audiopll_div2; + unsigned int audiopll_freq3; + unsigned int audiopll_div3; + unsigned int audiopll_freq4; + unsigned int audiopll_div4; + unsigned int audiopll_freq5; + unsigned int audiopll_div5; +}; + +const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE; +const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE; +const struct cm_pll *cmpll = (struct cm_pll *)CM_PLL_BASE; +const struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; + +void enable_dmm_clocks(void) +{ + writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl); + writel(PRCM_MOD_EN, &cmdef->emif0clkctrl); + writel(PRCM_MOD_EN, &cmdef->emif1clkctrl); + + /* Wait for clocks to be active */ + while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300) + ; + /* Wait for emif0 to be fully functional, including OCP */ + while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0) + ; + /* Wait for emif1 to be fully functional, including OCP */ + while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0) + ; + + writel(PRCM_MOD_EN, &cmdef->dmmclkctrl); + /* Wait for dmm to be fully functional, including OCP */ + while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0) + ; + + /* Enable Tiled Access */ + writel(0x80000000, DMM_PAT_BASE_ADDR); +} + +/* assume delay is aprox at least 1us */ +static void ddr_delay(int d) +{ + int i; + + /* + * read a control register. + * this is a bit more delay and cannot be optimized by the compiler + * assuming one read takes 200 cycles and A8 is runing 1 GHz + * somewhat conservative setting + */ + for (i = 0; i < 50*d; i++) + readl(CONTROL_STATUS); +} + +static void main_pll_init_ti816x(void) +{ + u32 main_pll_ctrl = 0; + + /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */ + main_pll_ctrl = readl(&cmpll->mainpll_ctrl); + main_pll_ctrl &= 0xFFFFFFFB; + main_pll_ctrl |= BIT(2); + writel(main_pll_ctrl, &cmpll->mainpll_ctrl); + + /* Enable PLL by setting BIT3 in its ctrl reg */ + main_pll_ctrl = readl(&cmpll->mainpll_ctrl); + main_pll_ctrl &= 0xFFFFFFF7; + main_pll_ctrl |= BIT(3); + writel(main_pll_ctrl, &cmpll->mainpll_ctrl); + + /* Write the values of N,P in the CTRL reg */ + main_pll_ctrl = readl(&cmpll->mainpll_ctrl); + main_pll_ctrl &= 0xFF; + main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8); + writel(main_pll_ctrl, &cmpll->mainpll_ctrl); + + /* Power up clock1-7 */ + writel(0x0, &cmpll->mainpll_pwd); + + /* Program the freq and divider values for clock1-7 */ + writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1), + &cmpll->mainpll_freq1); + writel(((1<<8) | MAIN_MDIV1), &cmpll->mainpll_div1); + + writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2), + &cmpll->mainpll_freq2); + writel(((1<<8) | MAIN_MDIV2), &cmpll->mainpll_div2); + + writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3), + &cmpll->mainpll_freq3); + writel(((1<<8) | MAIN_MDIV3), &cmpll->mainpll_div3); + + writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4), + &cmpll->mainpll_freq4); + writel(((1<<8) | MAIN_MDIV4), &cmpll->mainpll_div4); + + writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5), + &cmpll->mainpll_freq5); + writel(((1<<8) | MAIN_MDIV5), &cmpll->mainpll_div5); + + writel((1<<8 | MAIN_MDIV6), &cmpll->mainpll_div6); + + writel((1<<8 | MAIN_MDIV7), &cmpll->mainpll_div7); + + /* Wait for PLL to lock */ + while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7)) + ; + + /* Put the PLL in normal mode, disable bypass */ + main_pll_ctrl = readl(&cmpll->mainpll_ctrl); + main_pll_ctrl &= 0xFFFFFFFB; + writel(main_pll_ctrl, &cmpll->mainpll_ctrl); +} + +static void ddr_pll_bypass_ti816x(void) +{ + u32 ddr_pll_ctrl = 0; + + /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */ + ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); + ddr_pll_ctrl &= 0xFFFFFFFB; + ddr_pll_ctrl |= BIT(2); + writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); +} + +static void ddr_pll_init_ti816x(void) +{ + u32 ddr_pll_ctrl = 0; + /* Enable PLL by setting BIT3 in its ctrl reg */ + ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); + ddr_pll_ctrl &= 0xFFFFFFF7; + ddr_pll_ctrl |= BIT(3); + writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); + + /* Write the values of N,P in the CTRL reg */ + ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); + ddr_pll_ctrl &= 0xFF; + ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8); + writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); + + ddr_delay(10); + + /* Power up clock1-5 */ + writel(0x0, &cmpll->ddrpll_pwd); + + /* Program the freq and divider values for clock1-3 */ + writel(((0<<8) | DDR_MDIV1), &cmpll->ddrpll_div1); + ddr_delay(1); + writel(((1<<8) | DDR_MDIV1), &cmpll->ddrpll_div1); + writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2), + &cmpll->ddrpll_freq2); + writel(((1<<8) | DDR_MDIV2), &cmpll->ddrpll_div2); + writel(((0<<8) | DDR_MDIV3), &cmpll->ddrpll_div3); + ddr_delay(1); + writel(((1<<8) | DDR_MDIV3), &cmpll->ddrpll_div3); + ddr_delay(1); + writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3), + &cmpll->ddrpll_freq3); + ddr_delay(1); + writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3), + &cmpll->ddrpll_freq3); + + ddr_delay(5); + + /* Wait for PLL to lock */ + while ((readl(&cmpll->ddrpll_ctrl) & BIT(7)) != BIT(7)) + ; + + /* Power up RCD */ + writel(BIT(0), DDR_RCD); +} + +static void peripheral_enable(void) +{ + /* Wake-up the l3_slow clock */ + writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl); + + /* + * Note on Timers: + * There are 8 timers(0-7) out of which timer 0 is a secure timer. + * Timer 0 mux should not be changed + * + * To access the timer registers we need the to be + * enabled which is what we do in the first step + */ + + /* Enable timer1 */ + writel(PRCM_MOD_EN, &cmalwon->timer1clkctrl); + /* Select timer1 clock to be CLKIN (27MHz) */ + writel(BIT(1), CM_TIMER1_CLKSEL); + + /* Wait for timer1 to be ON-ACTIVE */ + while (((readl(&cmalwon->l3slowclkstctrl) + & (0x80000<<1))>>20) != 1) + ; + /* Wait for timer1 to be enabled */ + while (((readl(&cmalwon->timer1clkctrl) & 0x30000)>>16) != 0) + ; + /* Active posted mode */ + writel(PRCM_MOD_EN, (DM_TIMER1_BASE + 0x54)); + while (readl(DM_TIMER1_BASE + 0x10) & BIT(0)) + ; + /* Start timer1 */ + writel(BIT(0), (DM_TIMER1_BASE + 0x38)); + + /* eFuse */ + writel(PRCM_MOD_EN, CM_ALWON_CUST_EFUSE_CLKCTRL); + while (readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != PRCM_MOD_EN) + ; + + /* Enable gpio0 */ + writel(PRCM_MOD_EN, &cmalwon->gpio0clkctrl); + while (readl(&cmalwon->gpio0clkctrl) != PRCM_MOD_EN) + ; + writel((BIT(8)), &cmalwon->gpio0clkctrl); + + /* Enable spi */ + writel(PRCM_MOD_EN, &cmalwon->spiclkctrl); + while (readl(&cmalwon->spiclkctrl) != PRCM_MOD_EN) + ; + + /* Enable i2c0 */ + writel(PRCM_MOD_EN, &cmalwon->i2c0clkctrl); + while (readl(&cmalwon->i2c0clkctrl) != PRCM_MOD_EN) + ; + + /* Enable ethernet0 */ + writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl); + writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl); + writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl); + + /* Enable hsmmc */ + writel(PRCM_MOD_EN, &cmalwon->sdioclkctrl); + while (readl(&cmalwon->sdioclkctrl) != PRCM_MOD_EN) + ; +} + +void setup_clocks_for_console(void) +{ + /* Fix ROM code bug - from TI-PSP-04.00.02.14 */ + writel(0x0, CM_SYSCLK10_CLKSEL); + + ddr_pll_bypass_ti816x(); + + /* Enable uart0-2 */ + writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl); + while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN) + ; + writel(PRCM_MOD_EN, &cmalwon->uart1clkctrl); + while (readl(&cmalwon->uart1clkctrl) != PRCM_MOD_EN) + ; + writel(PRCM_MOD_EN, &cmalwon->uart2clkctrl); + while (readl(&cmalwon->uart2clkctrl) != PRCM_MOD_EN) + ; + while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100) + ; +} + +void prcm_init(void) +{ + /* Enable the control */ + writel(PRCM_MOD_EN, &cmalwon->controlclkctrl); + + main_pll_init_ti816x(); + ddr_pll_init_ti816x(); + + /* + * With clk freqs setup to desired values, + * enable the required peripherals + */ + peripheral_enable(); +} diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index 21cefd4..59ad25c 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -40,9 +40,11 @@ void dram_init_banksize(void) static struct dmm_lisa_map_regs *hw_lisa_map_regs = (struct dmm_lisa_map_regs *)DMM_BASE; #endif +#ifndef CONFIG_TI816X static struct vtp_reg *vtpreg[2] = { (struct vtp_reg *)VTP0_CTRL_ADDR, (struct vtp_reg *)VTP1_CTRL_ADDR}; +#endif #ifdef CONFIG_AM33XX static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; #endif @@ -64,6 +66,7 @@ void config_dmm(const struct dmm_lisa_map_regs *regs) } #endif +#ifndef CONFIG_TI816X static void config_vtp(int nr) { writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE, @@ -78,6 +81,7 @@ static void config_vtp(int nr) VTP_CTRL_READY) ; } +#endif void __weak ddr_pll_config(unsigned int ddrpll_m) { @@ -88,7 +92,9 @@ void config_ddr(unsigned int pll, unsigned int ioctrl, const struct emif_regs *regs, int nr) { ddr_pll_config(pll); +#ifndef CONFIG_TI816X config_vtp(nr); +#endif config_cmd_ctrl(ctrl, nr); config_ddr_data(data, nr); diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 0d4b9ae..519249e 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -13,6 +13,10 @@ #include +#ifdef CONFIG_TI81XX +#include +#endif + #define LDELAY 1000000 /*CM___CLKCTRL */ diff --git a/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h b/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h new file mode 100644 index 0000000..f069922 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h @@ -0,0 +1,142 @@ +/* + * ti81xx.h + * + * Copyright (C) 2013, Adeneo Embedded + * Antoine Tenart, + * + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + */ + +#ifndef _CLOCK_TI81XX_H_ +#define _CLOCK_TI81XX_H_ + +#define PRCM_MOD_EN 0x2 + +#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500) +#define CM_ALWON_BASE (PRCM_BASE + 0x1400) + +struct cm_def { + unsigned int resv0[2]; + unsigned int l3fastclkstctrl; + unsigned int resv1[1]; + unsigned int pciclkstctrl; + unsigned int resv2[1]; + unsigned int ducaticlkstctrl; + unsigned int resv3[1]; + unsigned int emif0clkctrl; + unsigned int emif1clkctrl; + unsigned int dmmclkctrl; + unsigned int fwclkctrl; + unsigned int resv4[10]; + unsigned int usbclkctrl; + unsigned int resv5[1]; + unsigned int sataclkctrl; + unsigned int resv6[4]; + unsigned int ducaticlkctrl; + unsigned int pciclkctrl; +}; + +struct cm_alwon { + unsigned int l3slowclkstctrl; + unsigned int ethclkstctrl; + unsigned int l3medclkstctrl; + unsigned int mmu_clkstctrl; + unsigned int mmucfg_clkstctrl; + unsigned int ocmc0clkstctrl; +#if defined(CONFIG_TI814X) + unsigned int vcpclkstctrl; +#elif defined(CONFIG_TI816X) + unsigned int ocmc1clkstctrl; +#endif + unsigned int mpuclkstctrl; + unsigned int sysclk4clkstctrl; + unsigned int sysclk5clkstctrl; + unsigned int sysclk6clkstctrl; + unsigned int rtcclkstctrl; + unsigned int l3fastclkstctrl; + unsigned int resv0[67]; + unsigned int mcasp0clkctrl; + unsigned int mcasp1clkctrl; + unsigned int mcasp2clkctrl; + unsigned int mcbspclkctrl; + unsigned int uart0clkctrl; + unsigned int uart1clkctrl; + unsigned int uart2clkctrl; + unsigned int gpio0clkctrl; + unsigned int gpio1clkctrl; + unsigned int i2c0clkctrl; + unsigned int i2c1clkctrl; +#if defined(CONFIG_TI814X) + unsigned int mcasp345clkctrl; + unsigned int atlclkctrl; + unsigned int mlbclkctrl; + unsigned int pataclkctrl; + unsigned int resv1[1]; + unsigned int uart3clkctrl; + unsigned int uart4clkctrl; + unsigned int uart5clkctrl; +#elif defined(CONFIG_TI816X) + unsigned int resv1[1]; + unsigned int timer1clkctrl; + unsigned int timer2clkctrl; + unsigned int timer3clkctrl; + unsigned int timer4clkctrl; + unsigned int timer5clkctrl; + unsigned int timer6clkctrl; + unsigned int timer7clkctrl; +#endif + unsigned int wdtimerclkctrl; + unsigned int spiclkctrl; + unsigned int mailboxclkctrl; + unsigned int spinboxclkctrl; + unsigned int mmudataclkctrl; + unsigned int resv2[2]; + unsigned int mmucfgclkctrl; +#if defined(CONFIG_TI814X) + unsigned int resv3[2]; +#elif defined(CONFIG_TI816X) + unsigned int resv3[1]; + unsigned int sdioclkctrl; +#endif + unsigned int ocmc0clkctrl; +#if defined(CONFIG_TI814X) + unsigned int vcpclkctrl; +#elif defined(CONFIG_TI816X) + unsigned int ocmc1clkctrl; +#endif + unsigned int resv4[2]; + unsigned int controlclkctrl; + unsigned int resv5[2]; + unsigned int gpmcclkctrl; + unsigned int ethernet0clkctrl; + unsigned int ethernet1clkctrl; + unsigned int mpuclkctrl; +#if defined(CONFIG_TI814X) + unsigned int debugssclkctrl; +#elif defined(CONFIG_TI816X) + unsigned int resv6[1]; +#endif + unsigned int l3clkctrl; + unsigned int l4hsclkctrl; + unsigned int l4lsclkctrl; + unsigned int rtcclkctrl; + unsigned int tpccclkctrl; + unsigned int tptc0clkctrl; + unsigned int tptc1clkctrl; + unsigned int tptc2clkctrl; + unsigned int tptc3clkctrl; +#if defined(CONFIG_TI814X) + unsigned int resv6[4]; + unsigned int dcan01clkctrl; + unsigned int mmchs0clkctrl; + unsigned int mmchs1clkctrl; + unsigned int mmchs2clkctrl; + unsigned int custefuseclkctrl; +#elif defined(CONFIG_TI816X) + unsigned int sr0clkctrl; + unsigned int sr1clkctrl; +#endif +}; + +#endif /* _CLOCK_TI81XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 18d7d99..95f7a9a 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -192,37 +192,46 @@ struct ddr_data_regs { * correspond to DATA1 registers defined here. */ struct ddr_regs { - unsigned int resv0[7]; - unsigned int cm0csratio; /* offset 0x01C */ + unsigned int resv0[3]; + unsigned int cm0config; /* offset 0x00C */ + unsigned int cm0configclk; /* offset 0x010 */ unsigned int resv1[2]; + unsigned int cm0csratio; /* offset 0x01C */ + unsigned int resv2[2]; unsigned int cm0dldiff; /* offset 0x028 */ unsigned int cm0iclkout; /* offset 0x02C */ - unsigned int resv2[8]; + unsigned int resv3[4]; + unsigned int cm1config; /* offset 0x040 */ + unsigned int cm1configclk; /* offset 0x044 */ + unsigned int resv4[2]; unsigned int cm1csratio; /* offset 0x050 */ - unsigned int resv3[2]; + unsigned int resv5[2]; unsigned int cm1dldiff; /* offset 0x05C */ unsigned int cm1iclkout; /* offset 0x060 */ - unsigned int resv4[8]; + unsigned int resv6[4]; + unsigned int cm2config; /* offset 0x074 */ + unsigned int cm2configclk; /* offset 0x078 */ + unsigned int resv7[2]; unsigned int cm2csratio; /* offset 0x084 */ - unsigned int resv5[2]; + unsigned int resv8[2]; unsigned int cm2dldiff; /* offset 0x090 */ unsigned int cm2iclkout; /* offset 0x094 */ - unsigned int resv6[12]; + unsigned int resv9[12]; unsigned int dt0rdsratio0; /* offset 0x0C8 */ - unsigned int resv7[4]; + unsigned int resv10[4]; unsigned int dt0wdsratio0; /* offset 0x0DC */ - unsigned int resv8[4]; + unsigned int resv11[4]; unsigned int dt0wiratio0; /* offset 0x0F0 */ - unsigned int resv9; + unsigned int resv12; unsigned int dt0wimode0; /* offset 0x0F8 */ unsigned int dt0giratio0; /* offset 0x0FC */ - unsigned int resv10; + unsigned int resv13; unsigned int dt0gimode0; /* offset 0x104 */ unsigned int dt0fwsratio0; /* offset 0x108 */ - unsigned int resv11[4]; + unsigned int resv14[4]; unsigned int dt0dqoffset; /* offset 0x11C */ unsigned int dt0wrsratio0; /* offset 0x120 */ - unsigned int resv12[4]; + unsigned int resv15[4]; unsigned int dt0rdelays0; /* offset 0x134 */ unsigned int dt0dldiff0; /* offset 0x138 */ }; diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index fa0bbda..2055b25 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -15,6 +15,8 @@ #include #ifdef CONFIG_AM33XX #include +#elif defined(CONFIG_TI816X) +#include #elif defined(CONFIG_TI814X) #include #elif defined(CONFIG_AM43XX) @@ -53,21 +55,13 @@ #define CM_CEFUSE 0x44E00A00 #define PRM_DEVICE 0x44E00F00 -/* VTP Base address */ -#define VTP1_CTRL_ADDR 0x48140E10 - /* DDR Base address */ #define DDR_CTRL_ADDR 0x44E10E04 #define DDR_CONTROL_BASE_ADDR 0x44E11404 -#define DDR_PHY_CMD_ADDR2 0x47C0C800 -#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 /* UART */ #define DEFAULT_UART_BASE UART0_BASE -#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) -#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE - /* GPMC Base address */ #define GPMC_BASE 0x50000000 diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h index 5297c63..8973fd8 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h @@ -36,12 +36,18 @@ /* VTP Base address */ #define VTP0_CTRL_ADDR 0x44E10E0C +#define VTP1_CTRL_ADDR 0x48140E10 /* DDR Base address */ #define DDR_PHY_CMD_ADDR 0x44E12000 #define DDR_PHY_DATA_ADDR 0x44E120C8 +#define DDR_PHY_CMD_ADDR2 0x47C0C800 +#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 #define DDR_DATA_REGS_NR 2 +#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) +#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE + /* CPSW Config space */ #define CPSW_MDIO_BASE 0x4A101000 diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index d4d5c41..303c594 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -36,10 +36,13 @@ /* VTP Base address */ #define VTP0_CTRL_ADDR 0x44E10E0C +#define VTP1_CTRL_ADDR 0x48140E10 /* DDR Base address */ #define DDR_PHY_CMD_ADDR 0x44E12000 #define DDR_PHY_DATA_ADDR 0x44E120C8 +#define DDR_PHY_CMD_ADDR2 0x47C0C800 +#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 #define DDR_DATA_REGS_NR 2 /* CPSW Config space */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h index 1ad8cb1..4509a23 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h @@ -36,12 +36,18 @@ /* VTP Base address */ #define VTP0_CTRL_ADDR 0x48140E0C +#define VTP1_CTRL_ADDR 0x48140E10 /* DDR Base address */ #define DDR_PHY_CMD_ADDR 0x47C0C400 #define DDR_PHY_DATA_ADDR 0x47C0C4C8 +#define DDR_PHY_CMD_ADDR2 0x47C0C800 +#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 #define DDR_DATA_REGS_NR 4 +#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) +#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE + /* CPSW Config space */ #define CPSW_MDIO_BASE 0x4A100800 diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h new file mode 100644 index 0000000..3c68064 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h @@ -0,0 +1,61 @@ +/* + * hardware_ti816x.h + * + * TI816x hardware specific header + * + * Copyright (C) 2013, Adeneo Embedded + * Antoine Tenart, + * Based on TI-PSP-04.00.02.14 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AM33XX_HARDWARE_TI816X_H +#define __AM33XX_HARDWARE_TI816X_H + +/* UART */ +#define UART0_BASE 0x48020000 +#define UART1_BASE 0x48022000 +#define UART2_BASE 0x48024000 + +/* Watchdog Timer */ +#define WDT_BASE 0x480C2000 + +/* Control Module Base Address */ +#define CTRL_BASE 0x48140000 + +/* PRCM Base Address */ +#define PRCM_BASE 0x48180000 + +#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) +#define PRM_RSTST (PRM_RSTCTRL + 8) + +/* VTP Base address */ +#define VTP0_CTRL_ADDR 0x48198358 +#define VTP1_CTRL_ADDR 0x4819A358 + +/* DDR Base address */ +#define DDR_PHY_CMD_ADDR 0x48198000 +#define DDR_PHY_DATA_ADDR 0x481980C8 +#define DDR_PHY_CMD_ADDR2 0x4819A000 +#define DDR_PHY_DATA_ADDR2 0x4819A0C8 +#define DDR_DATA_REGS_NR 4 + + +#define DDRPHY_0_CONFIG_BASE 0x48198000 +#define DDRPHY_1_CONFIG_BASE 0x4819A000 +#define DDRPHY_CONFIG_BASE ((emif == 0) ? \ + DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE) + +/* RTC base address */ +#define RTC_BASE 0x480C0000 + +#endif /* __AM33XX_HARDWARE_TI816X_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h index 51ba791..724e252 100644 --- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h +++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h @@ -27,6 +27,9 @@ #if defined(CONFIG_TI814X) #undef MMC_CLOCK_REFERENCE #define MMC_CLOCK_REFERENCE 192 /* MHz */ +#elif defined(CONFIG_TI816X) +#undef MMC_CLOCK_REFERENCE +#define MMC_CLOCK_REFERENCE 48 /* MHz */ #endif #endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h index f760d84..3249437 100644 --- a/arch/arm/include/asm/arch-am33xx/mux.h +++ b/arch/arm/include/asm/arch-am33xx/mux.h @@ -23,6 +23,8 @@ #include #elif defined(CONFIG_TI814X) #include +#elif defined(CONFIG_TI816X) +#include #elif defined(CONFIG_AM43XX) #include #endif diff --git a/arch/arm/include/asm/arch-am33xx/mux_ti816x.h b/arch/arm/include/asm/arch-am33xx/mux_ti816x.h new file mode 100644 index 0000000..e4e5a48 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/mux_ti816x.h @@ -0,0 +1,363 @@ +/* + * mux_ti816x.h + * + * Copyright (C) 2013, Adeneo Embedded + * Antoine Tenart, + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MUX_TI816X_H_ +#define _MUX_TI816X_H_ + +#include +#include + +#define MUX_CFG(value, offset) \ + __raw_writel(value, (CTRL_BASE + offset)); + +#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */ +#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */ +#define PULLUDEN (0x0 << 3) /* Pull up enabled */ +#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ +#define MODE(val) (val) /* used for Readability */ + + +/* + * PAD CONTROL OFFSETS + * Field names corresponds to the pad signal name + */ +struct pad_signals { + int pincntl1; + int pincntl2; + int pincntl3; + int pincntl4; + int pincntl5; + int pincntl6; + int pincntl7; + int pincntl8; + int pincntl9; + int pincntl10; + int pincntl11; + int pincntl12; + int pincntl13; + int pincntl14; + int pincntl15; + int pincntl16; + int pincntl17; + int pincntl18; + int pincntl19; + int pincntl20; + int pincntl21; + int pincntl22; + int pincntl23; + int pincntl24; + int pincntl25; + int pincntl26; + int pincntl27; + int pincntl28; + int pincntl29; + int pincntl30; + int pincntl31; + int pincntl32; + int pincntl33; + int pincntl34; + int pincntl35; + int pincntl36; + int pincntl37; + int pincntl38; + int pincntl39; + int pincntl40; + int pincntl41; + int pincntl42; + int pincntl43; + int pincntl44; + int pincntl45; + int pincntl46; + int pincntl47; + int pincntl48; + int pincntl49; + int pincntl50; + int pincntl51; + int pincntl52; + int pincntl53; + int pincntl54; + int pincntl55; + int pincntl56; + int pincntl57; + int pincntl58; + int pincntl59; + int pincntl60; + int pincntl61; + int pincntl62; + int pincntl63; + int pincntl64; + int pincntl65; + int pincntl66; + int pincntl67; + int pincntl68; + int pincntl69; + int pincntl70; + int pincntl71; + int pincntl72; + int pincntl73; + int pincntl74; + int pincntl75; + int pincntl76; + int pincntl77; + int pincntl78; + int pincntl79; + int pincntl80; + int pincntl81; + int pincntl82; + int pincntl83; + int pincntl84; + int pincntl85; + int pincntl86; + int pincntl87; + int pincntl88; + int pincntl89; + int pincntl90; + int pincntl91; + int pincntl92; + int pincntl93; + int pincntl94; + int pincntl95; + int pincntl96; + int pincntl97; + int pincntl98; + int pincntl99; + int pincntl100; + int pincntl101; + int pincntl102; + int pincntl103; + int pincntl104; + int pincntl105; + int pincntl106; + int pincntl107; + int pincntl108; + int pincntl109; + int pincntl110; + int pincntl111; + int pincntl112; + int pincntl113; + int pincntl114; + int pincntl115; + int pincntl116; + int pincntl117; + int pincntl118; + int pincntl119; + int pincntl120; + int pincntl121; + int pincntl122; + int pincntl123; + int pincntl124; + int pincntl125; + int pincntl126; + int pincntl127; + int pincntl128; + int pincntl129; + int pincntl130; + int pincntl131; + int pincntl132; + int pincntl133; + int pincntl134; + int pincntl135; + int pincntl136; + int pincntl137; + int pincntl138; + int pincntl139; + int pincntl140; + int pincntl141; + int pincntl142; + int pincntl143; + int pincntl144; + int pincntl145; + int pincntl146; + int pincntl147; + int pincntl148; + int pincntl149; + int pincntl150; + int pincntl151; + int pincntl152; + int pincntl153; + int pincntl154; + int pincntl155; + int pincntl156; + int pincntl157; + int pincntl158; + int pincntl159; + int pincntl160; + int pincntl161; + int pincntl162; + int pincntl163; + int pincntl164; + int pincntl165; + int pincntl166; + int pincntl167; + int pincntl168; + int pincntl169; + int pincntl170; + int pincntl171; + int pincntl172; + int pincntl173; + int pincntl174; + int pincntl175; + int pincntl176; + int pincntl177; + int pincntl178; + int pincntl179; + int pincntl180; + int pincntl181; + int pincntl182; + int pincntl183; + int pincntl184; + int pincntl185; + int pincntl186; + int pincntl187; + int pincntl188; + int pincntl189; + int pincntl190; + int pincntl191; + int pincntl192; + int pincntl193; + int pincntl194; + int pincntl195; + int pincntl196; + int pincntl197; + int pincntl198; + int pincntl199; + int pincntl200; + int pincntl201; + int pincntl202; + int pincntl203; + int pincntl204; + int pincntl205; + int pincntl206; + int pincntl207; + int pincntl208; + int pincntl209; + int pincntl210; + int pincntl211; + int pincntl212; + int pincntl213; + int pincntl214; + int pincntl215; + int pincntl216; + int pincntl217; + int pincntl218; + int pincntl219; + int pincntl220; + int pincntl221; + int pincntl222; + int pincntl223; + int pincntl224; + int pincntl225; + int pincntl226; + int pincntl227; + int pincntl228; + int pincntl229; + int pincntl230; + int pincntl231; + int pincntl232; + int pincntl233; + int pincntl234; + int pincntl235; + int pincntl236; + int pincntl237; + int pincntl238; + int pincntl239; + int pincntl240; + int pincntl241; + int pincntl242; + int pincntl243; + int pincntl244; + int pincntl245; + int pincntl246; + int pincntl247; + int pincntl248; + int pincntl249; + int pincntl250; + int pincntl251; + int pincntl252; + int pincntl253; + int pincntl254; + int pincntl255; + int pincntl256; + int pincntl257; + int pincntl258; + int pincntl259; + int pincntl260; + int pincntl261; + int pincntl262; + int pincntl263; + int pincntl264; + int pincntl265; + int pincntl266; + int pincntl267; + int pincntl268; + int pincntl269; + int pincntl270; + int pincntl271; + int pincntl272; + int pincntl273; + int pincntl274; + int pincntl275; + int pincntl276; + int pincntl277; + int pincntl278; + int pincntl279; + int pincntl280; + int pincntl281; + int pincntl282; + int pincntl283; + int pincntl284; + int pincntl285; + int pincntl286; + int pincntl287; + int pincntl288; + int pincntl289; + int pincntl290; + int pincntl291; + int pincntl292; + int pincntl293; + int pincntl294; + int pincntl295; + int pincntl296; + int pincntl297; + int pincntl298; + int pincntl299; + int pincntl300; + int pincntl301; + int pincntl302; + int pincntl303; + int pincntl304; + int pincntl305; + int pincntl306; + int pincntl307; + int pincntl308; + int pincntl309; + int pincntl310; + int pincntl311; + int pincntl312; + int pincntl313; + int pincntl314; + int pincntl315; + int pincntl316; + int pincntl317; + int pincntl318; + int pincntl319; + int pincntl320; + int pincntl321; + int pincntl322; + int pincntl323; +}; + +#endif /* endif _MUX_TI816X_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index 570f45c..95de9aa 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -7,6 +7,14 @@ #ifndef _ASM_ARCH_SPL_H_ #define _ASM_SPL_H_ +#if defined(CONFIG_TI816X) +#define BOOT_DEVICE_XIP 2 +#define BOOT_DEVICE_NAND 3 +#define BOOT_DEVICE_MMC1 6 +#define BOOT_DEVICE_MMC2 5 +#define BOOT_DEVICE_UART 0x43 +#define BOOT_DEVICE_MMC2_2 0xFF +#else #define BOOT_DEVICE_XIP 2 #define BOOT_DEVICE_NAND 5 #if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) @@ -21,11 +29,12 @@ #define BOOT_DEVICE_USBETH 68 #define BOOT_DEVICE_CPGMAC 70 #define BOOT_DEVICE_MMC2_2 0xFF +#endif #if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX) #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 #define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 -#elif defined(CONFIG_TI814X) +#elif defined(CONFIG_TI81XX) #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2 #define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1 #endif -- cgit v1.1