From b841c01d6a9c00ea1a4168b30ad4d6f45b4e519e Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 14 Sep 2011 19:59:33 +0000 Subject: arm, davinci: add SYSCFG1 base and register struct Signed-off-by: Heiko Schocher Cc: Paulraj Sandeep Cc: Albert ARIBAUD Signed-off-by: Sandeep Paulraj --- arch/arm/include/asm/arch-davinci/hardware.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 19ab680..dcc71d6 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -142,6 +142,7 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000 #define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000 #define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000 +#define DAVINCI_SYSCFG1_BASE 0x01e2c000 #define DAVINCI_MMC_SD0_BASE 0x01c40000 #define DAVINCI_MMC_SD1_BASE 0x01e1b000 #define DAVINCI_TIMER2_BASE 0x01f0c000 @@ -448,6 +449,21 @@ struct davinci_syscfg_regs { #define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20) #define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27) +struct davinci_syscfg1_regs { + dv_reg vtpio_ctl; + dv_reg ddr_slew; + dv_reg deepsleep; + dv_reg pupd_ena; + dv_reg pupd_sel; + dv_reg rxactive; + dv_reg pwrdwn; +}; + +#define davinci_syscfg1_regs \ + ((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE) + +#define DDR_SLEW_CMOSEN_BIT 4 + /* Interrupt controller */ struct davinci_aintc_regs { dv_reg revid; -- cgit v1.1