From b5e01eecc89e3e5c2ed3c17b803529be3c3702fb Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 10 Dec 2013 15:02:23 +0530 Subject: ARM: AM43xx: GP_EVM: Add support for DDR3 GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register Signed-off-by: Lokesh Vutla --- arch/arm/cpu/armv7/am33xx/ddr.c | 6 ++++-- arch/arm/cpu/armv7/omap-common/emif-common.c | 14 -------------- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 8 ++++++++ arch/arm/include/asm/arch-am33xx/gpio.h | 12 ++++++++++++ arch/arm/include/asm/emif.h | 14 ++++++++++++++ 5 files changed, 38 insertions(+), 16 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index 1abbb07..d05e666 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -97,8 +97,10 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr) writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); - configure_mr(nr, 0); - configure_mr(nr, 1); + if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) { + configure_mr(nr, 0); + configure_mr(nr, 1); + } } /** diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 5a3f285..cd6289b 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -50,20 +50,6 @@ inline u32 emif_num(u32 base) return 0; } -/* - * Get SDRAM type connected to EMIF. - * Assuming similar SDRAM parts are connected to both EMIF's - * which is typically the case. So it is sufficient to get - * SDRAM type from EMIF1. - */ -u32 emif_sdram_type() -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; - - return (readl(&emif->emif_sdram_config) & - EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT; -} - static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) { u32 mr; diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 6af4b84..c1777df 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -136,6 +136,14 @@ #define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294 #define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294 +#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 +#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 +#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84 +#define DDR3_DATA0_IOCTRL_VALUE 0x84 +#define DDR3_DATA1_IOCTRL_VALUE 0x84 +#define DDR3_DATA2_IOCTRL_VALUE 0x84 +#define DDR3_DATA3_IOCTRL_VALUE 0x84 + /** * Configure DMM */ diff --git a/arch/arm/include/asm/arch-am33xx/gpio.h b/arch/arm/include/asm/arch-am33xx/gpio.h index 13a047f..a1ffd49 100644 --- a/arch/arm/include/asm/arch-am33xx/gpio.h +++ b/arch/arm/include/asm/arch-am33xx/gpio.h @@ -13,4 +13,16 @@ #define AM33XX_GPIO2_BASE 0x481AC000 #define AM33XX_GPIO3_BASE 0x481AE000 +#define GPIO_22 22 + +/* GPIO CTRL register */ +#define GPIO_CTRL_DISABLEMODULE_SHIFT 0 +#define GPIO_CTRL_DISABLEMODULE_MASK (1 << 0) +#define GPIO_CTRL_ENABLEMODULE GPIO_CTRL_DISABLEMODULE_MASK + +/* GPIO OUTPUT ENABLE register */ +#define GPIO_OE_ENABLE(x) (1 << x) + +/* GPIO SETDATAOUT register */ +#define GPIO_SETDATAOUT(x) (1 << x) #endif /* _GPIO_AM33xx_H */ diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index e68c113..45668ca 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -1160,6 +1160,20 @@ static inline u32 get_emif_rev(u32 base) >> EMIF_REG_MAJOR_REVISION_SHIFT; } +/* + * Get SDRAM type connected to EMIF. + * Assuming similar SDRAM parts are connected to both EMIF's + * which is typically the case. So it is sufficient to get + * SDRAM type from EMIF1. + */ +static inline u32 emif_sdram_type(void) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + + return (readl(&emif->emif_sdram_config) & + EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT; +} + /* assert macros */ #if defined(DEBUG) #define emif_assert(c) ({ if (!(c)) for (;;); }) -- cgit v1.1