From aa14b42d53b03b9b9d7e19e4cb5f9e59f881c4dc Mon Sep 17 00:00:00 2001 From: Akshay Saraswat Date: Thu, 13 Nov 2014 22:38:15 +0530 Subject: Exynos5800: Introduce new proid for Exynos5800 This patch intends to add a new proid for Exynos5800 which is a variant of Exynos5420. Product id for Exynos5800 is 0x5422. Both Exynos5420 and Exynos5800 are pin to pin compitable. This gives us an advantage of reusing Exynos5420 clock, pinmux, memory and other settings. Signed-off-by: Alim Akhtar Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/cpu/armv7/exynos/clock.c | 19 ++++++++++--------- arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 2 +- arch/arm/cpu/armv7/exynos/pinmux.c | 2 +- arch/arm/include/asm/arch-exynos/cpu.h | 10 +++++++++- arch/arm/include/asm/arch-exynos/gpio.h | 4 ++-- 5 files changed, 23 insertions(+), 14 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 7558eff..4ecce44 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -118,7 +118,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) div = PLL_DIV_1024; else if (proid_is_exynos4412()) div = PLL_DIV_65535; - else if (proid_is_exynos5250() || proid_is_exynos5420()) + else if (proid_is_exynos5250() || proid_is_exynos5420() + || proid_is_exynos5800()) div = PLL_DIV_65536; else return 0; @@ -1581,7 +1582,7 @@ static unsigned long exynos4_get_i2c_clk(void) unsigned long get_pll_clk(int pllreg) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_get_pll_clk(pllreg); return exynos5_get_pll_clk(pllreg); } else { @@ -1617,7 +1618,7 @@ unsigned long get_i2c_clk(void) unsigned long get_pwm_clk(void) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_get_pwm_clk(); return clock_get_periph_rate(PERIPH_ID_PWM0); } else { @@ -1630,7 +1631,7 @@ unsigned long get_pwm_clk(void) unsigned long get_uart_clk(int dev_index) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_get_uart_clk(dev_index); return exynos5_get_uart_clk(dev_index); } else { @@ -1643,7 +1644,7 @@ unsigned long get_uart_clk(int dev_index) unsigned long get_mmc_clk(int dev_index) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_get_mmc_clk(dev_index); return exynos5_get_mmc_clk(dev_index); } else { @@ -1654,7 +1655,7 @@ unsigned long get_mmc_clk(int dev_index) void set_mmc_clk(int dev_index, unsigned int div) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) exynos5420_set_mmc_clk(dev_index, div); else exynos5_set_mmc_clk(dev_index, div); @@ -1668,7 +1669,7 @@ unsigned long get_lcd_clk(void) if (cpu_is_exynos4()) return exynos4_get_lcd_clk(); else { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_get_lcd_clk(); else return exynos5_get_lcd_clk(); @@ -1682,7 +1683,7 @@ void set_lcd_clk(void) else { if (proid_is_exynos5250()) exynos5_set_lcd_clk(); - else if (proid_is_exynos5420()) + else if (proid_is_exynos5420() || proid_is_exynos5800()) exynos5420_set_lcd_clk(); } } @@ -1696,7 +1697,7 @@ void set_mipi_clk(void) int set_spi_clk(int periph_id, unsigned int rate) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_set_spi_clk(periph_id, rate); return exynos5_set_spi_clk(periph_id, rate); } else { diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c index b6a9bc1..0aff3d0 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c @@ -971,7 +971,7 @@ static void exynos5420_system_clock_init(void) void system_clock_init(void) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) exynos5420_system_clock_init(); else exynos5250_system_clock_init(); diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 3d95dc3..94d0297 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -837,7 +837,7 @@ static int exynos4x12_pinmux_config(int peripheral, int flags) int exynos_pinmux_config(int peripheral, int flags) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_pinmux_config(peripheral, flags); else if (proid_is_exynos5250()) return exynos5_pinmux_config(peripheral, flags); diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index 78aceef..29674ad 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -227,6 +227,13 @@ static inline void s5p_set_cpu_id(void) /* Exynos5420 */ s5p_cpu_id = 0x5420; break; + case 0x422: + /* + * Exynos5800 is a variant of Exynos5420 + * and has product id 0x5422 + */ + s5p_cpu_id = 0x5800; + break; } } @@ -255,6 +262,7 @@ IS_EXYNOS_TYPE(exynos4210, 0x4210) IS_EXYNOS_TYPE(exynos4412, 0x4412) IS_EXYNOS_TYPE(exynos5250, 0x5250) IS_EXYNOS_TYPE(exynos5420, 0x5420) +IS_EXYNOS_TYPE(exynos5800, 0x5800) #define SAMSUNG_BASE(device, base) \ static inline unsigned int __attribute__((no_instrument_function)) \ @@ -265,7 +273,7 @@ static inline unsigned int __attribute__((no_instrument_function)) \ return EXYNOS4X12_##base; \ return EXYNOS4_##base; \ } else if (cpu_is_exynos5()) { \ - if (proid_is_exynos5420()) \ + if (proid_is_exynos5420() || proid_is_exynos5800()) \ return EXYNOS5420_##base; \ return EXYNOS5_##base; \ } \ diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 02287de..9699954 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -1398,7 +1398,7 @@ static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = { static inline struct gpio_info *get_gpio_data(void) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_gpio_data; else return exynos5_gpio_data; @@ -1415,7 +1415,7 @@ static inline struct gpio_info *get_gpio_data(void) static inline unsigned int get_bank_num(void) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return EXYNOS5420_GPIO_NUM_PARTS; else return EXYNOS5_GPIO_NUM_PARTS; -- cgit v1.1 From e6b723fc7093cb8c2976c4fd3ae3e1e4f67ee020 Mon Sep 17 00:00:00 2001 From: Akshay Saraswat Date: Thu, 13 Nov 2014 22:38:16 +0530 Subject: Exynos5800: Add DTS for new board Peach-Pi We have a new board Peach-Pi similar to Peach-Pit. Peach-Pi differs from Peach-Pit in configuration factors like display resolution, memory size, SoC version etc. Signed-off-by: Alim Akhtar Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/exynos5800-peach-pi.dts | 157 +++++++++++++++++++++++++++++++++++ 2 files changed, 159 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/exynos5800-peach-pi.dts (limited to 'arch/arm') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ba6dec9..e5846ea 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -12,7 +12,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5250-snow.dtb \ exynos5250-smdk5250.dtb \ exynos5420-smdk5420.dtb \ - exynos5420-peach-pit.dtb + exynos5420-peach-pit.dtb \ + exynos5800-peach-pi.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts new file mode 100644 index 0000000..8aedf8e --- /dev/null +++ b/arch/arm/dts/exynos5800-peach-pi.dts @@ -0,0 +1,157 @@ +/* + * SAMSUNG/GOOGLE Peach-Pit board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "exynos54xx.dtsi" + +/ { + model = "Samsung/Google Peach Pi board based on Exynos5800"; + + compatible = "google,pit-rev#", "google,pit", + "google,peach", "samsung,exynos5800", "samsung,exynos5"; + + config { + google,bad-wake-gpios = <&gpio 0x56 0>; /* gpx0-6 */ + hwid = "PIT TEST A-A 7848"; + lazy-init = <1>; + }; + + aliases { + serial0 = "/serial@12C30000"; + console = "/serial@12C30000"; + pmic = "/i2c@12ca0000"; + }; + + dmc { + mem-manuf = "samsung"; + mem-type = "ddr3"; + clock-frequency = <800000000>; + arm-frequency = <1700000000>; + }; + + tmu@10060000 { + samsung,min-temp = <25>; + samsung,max-temp = <125>; + samsung,start-warning = <95>; + samsung,start-tripping = <105>; + samsung,hw-tripping = <110>; + samsung,efuse-min-value = <40>; + samsung,efuse-value = <55>; + samsung,efuse-max-value = <100>; + samsung,slope = <274761730>; + samsung,dc-value = <25>; + }; + + /* MAX77802 is on i2c bus 4 */ + i2c@12ca0000 { + clock-frequency = <400000>; + power-regulator@9 { + compatible = "maxim,max77802-pmic"; + reg = <0x9>; + }; + }; + + i2c@12cd0000 { /* i2c7 */ + clock-frequency = <100000>; + soundcodec@20 { + reg = <0x20>; + compatible = "maxim,max98090-codec"; + }; + + edp-lvds-bridge@48 { + compatible = "parade,ps8625"; + reg = <0x48>; + }; + }; + + sound@3830000 { + samsung,codec-type = "max98090"; + }; + + i2c@12e10000 { /* i2c9 */ + clock-frequency = <400000>; + tpm@20 { + compatible = "infineon,slb9645-tpm"; + reg = <0x20>; + }; + }; + + spi@12d30000 { /* spi1 */ + spi-max-frequency = <50000000>; + firmware_storage_spi: flash@0 { + reg = <0>; + + /* + * A region for the kernel to store a panic event + * which the firmware will add to the log. + */ + elog-panic-event-offset = <0x01e00000 0x100000>; + + elog-shrink-size = <0x400>; + elog-full-threshold = <0xc00>; + }; + }; + + spi@12d40000 { /* spi2 */ + spi-max-frequency = <4000000>; + spi-deactivate-delay = <200>; + cros-ec@0 { + reg = <0>; + compatible = "google,cros-ec"; + spi-half-duplex; + spi-max-timeout-ms = <1100>; + spi-frame-header = <0xec>; + ec-interrupt = <&gpio 93 1>; /* GPX1_5 */ + + /* + * This describes the flash memory within the EC. Note + * that the STM32L flash erases to 0, not 0xff. + */ + #address-cells = <1>; + #size-cells = <1>; + flash@8000000 { + reg = <0x08000000 0x20000>; + erase-value = <0>; + }; + }; + }; + + xhci@12000000 { + samsung,vbus-gpio = <&gpio 0x40 0>; /* H00 */ + }; + + xhci@12400000 { + samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */ + }; + + fimd@14400000 { + samsung,vl-freq = <60>; + samsung,vl-col = <1920>; + samsung,vl-row = <1080>; + samsung,vl-width = <1920>; + samsung,vl-height = <1080>; + + samsung,vl-clkp; + samsung,vl-dp; + samsung,vl-bpix = <4>; + + samsung,vl-hspw = <80>; + samsung,vl-hbpd = <172>; + samsung,vl-hfpd = <60>; + samsung,vl-vspw = <10>; + samsung,vl-vbpd = <25>; + samsung,vl-vfpd = <10>; + samsung,vl-cmd-allow-len = <0xf>; + + samsung,winid = <3>; + samsung,interface-mode = <1>; + samsung,dp-enabled = <1>; + samsung,dual-lcd-enabled = <0>; + }; +}; -- cgit v1.1 From 79043d84da076e4eb47e04495c55216897c9a161 Mon Sep 17 00:00:00 2001 From: Akshay Saraswat Date: Thu, 13 Nov 2014 22:38:17 +0530 Subject: Config: Exynos5800: Enable build for Peach-Pi This adds following things : - New config and defconfig for Peach-Pi board. - Alterations in Kconfig and MAINTAINERS. - Addition of CONFIG_EXYNOS5800. - ADdition of exynos5800-peach-pi in dts list. Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/cpu/armv7/exynos/Kconfig | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index 090be93..13dbd95 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -44,11 +44,16 @@ config TARGET_SMDK5420 select SUPPORT_SPL select OF_CONTROL if !SPL_BUILD -config TARGET_PEACH_PIT +config TARGET_PEACH_PI bool "Peach Pi board" select SUPPORT_SPL select OF_CONTROL if !SPL_BUILD +config TARGET_PEACH_PIT + bool "Peach Pit board" + select SUPPORT_SPL + select OF_CONTROL if !SPL_BUILD + endchoice config SYS_SOC -- cgit v1.1 From 061091098a5ec55ff4b68b61592af8619c2c7d88 Mon Sep 17 00:00:00 2001 From: Alim Akhtar Date: Thu, 13 Nov 2014 22:38:18 +0530 Subject: DMC: Exynos5: Enable update mode for DREX controller As per Exynos5800 UM ver 0.00 section 17.13.2.1 CONCONTROL register bit 3 [update_mode], Exynos5800 does not support the PHY initiated update. And it is recommanded to set this field to 1'b1 during initialization. This patch sets this bit. Applying MC-initiated mode makes DDL tracking ON, that helps in compensate MIF voltage variation. Signed-off-by: Alim Akhtar Signed-off-by: Doug Anderson Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 19 +++++++++++++++++++ arch/arm/include/asm/arch-exynos/dmc.h | 1 + 2 files changed, 20 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c index b86dd2d..4d73b45 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c +++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c @@ -832,6 +832,25 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG); setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG); + /* + * As per Exynos5800 UM ver 0.00 section 17.13.2.1 + * CONCONTROL register bit 3 [update_mode], Exynos5800 does not + * support the PHY initiated update. And it is recommended to set + * this field to 1'b1 during initialization + * + * When we apply PHY-initiated mode, DLL lock value is determined + * once at DMC init time and not updated later when we change the MIF + * voltage based on ASV group in kernel. Applying MC-initiated mode + * makes sure that DLL tracing is ON so that silicon is able to + * compensate the voltage variation. + */ + val = readl(&drex0->concontrol); + val |= CONCONTROL_UPDATE_MODE; + writel(val , &drex0->concontrol); + val = readl(&drex1->concontrol); + val |= CONCONTROL_UPDATE_MODE; + writel(val , &drex1->concontrol); + return 0; } #endif diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h index ec3f9b6..4990a1a 100644 --- a/arch/arm/include/asm/arch-exynos/dmc.h +++ b/arch/arm/include/asm/arch-exynos/dmc.h @@ -450,6 +450,7 @@ enum mem_manuf { #define CONCONTROL_RD_FETCH_SHIFT 12 #define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT) #define CONCONTROL_AREF_EN_SHIFT 5 +#define CONCONTROL_UPDATE_MODE (1 << 3) /* PRECHCONFIG register field */ #define PRECHCONFIG_TP_CNT_SHIFT 24 -- cgit v1.1 From 0e03e824652745d652c6b557307fa784ec1669aa Mon Sep 17 00:00:00 2001 From: Akshay Saraswat Date: Thu, 13 Nov 2014 22:38:20 +0530 Subject: Exynos5: ddr3: Choose between single or double channel config Add a 4G configuration and choose it based on the number of banks declared in config file. A board with 4 SDRAM banks declared (as per CONFIG_NR_DRAM_BANKS) will end up with the 2G confiuration. Signed-off-by: Doug Anderson Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c index 4d73b45..7c0b12a 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c +++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c @@ -464,6 +464,16 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) + DMC_OFFSET); pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE; + if (CONFIG_NR_DRAM_BANKS > 4) { + /* Need both controllers. */ + mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_2; + mem->chips_per_channel = 2; + mem->chips_to_configure = 2; + } else { + /* 2GB requires a single controller */ + mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_1; + } + /* Enable PAUSE for DREX */ setbits_le32(&clk->pause, ENABLE_BIT); -- cgit v1.1 From 4f29862487ab94e791d17de2df5528d417e88c1c Mon Sep 17 00:00:00 2001 From: Vadim Bendebury Date: Thu, 13 Nov 2014 22:38:21 +0530 Subject: Peach-Pi: Use the enhanced usb_copy() prototype Exynos5800 IROM has a different, from 5250 and 5420, prototype of the usb_copy() function. Luckily the earlier version did not expect any arguments, which means the same code could be used with old and new SoCs, the old ones just ignoring the arguments. Signed-off-by: Vadim Bendebury Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/cpu/armv7/exynos/spl_boot.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/exynos/spl_boot.c b/arch/arm/cpu/armv7/exynos/spl_boot.c index 658e4cb..dbd312c 100644 --- a/arch/arm/cpu/armv7/exynos/spl_boot.c +++ b/arch/arm/cpu/armv7/exynos/spl_boot.c @@ -195,10 +195,16 @@ void copy_uboot_to_ram(void) void (*end_bootop_from_emmc)(void); #endif #ifdef CONFIG_USB_BOOTING - u32 (*usb_copy)(void); int is_cr_z_set; unsigned int sec_boot_check; + /* + * Note that older hardware (before Exynos5800) does not expect any + * arguments, but it does not hurt to pass them, so a common function + * prototype is used. + */ + u32 (*usb_copy)(u32 num_of_block, u32 *dst); + /* Read iRAM location to check for secondary USB boot mode */ sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE); if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT) @@ -240,7 +246,7 @@ void copy_uboot_to_ram(void) */ is_cr_z_set = config_branch_prediction(0); usb_copy = get_irom_func(USB_INDEX); - usb_copy(); + usb_copy(0, (u32 *)CONFIG_SYS_TEXT_BASE); config_branch_prediction(is_cr_z_set); break; #endif -- cgit v1.1 From c2056157f84aac0c996015e43ce824a61bfa8549 Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Thu, 6 Nov 2014 11:44:31 +0100 Subject: exynos: dts: Correct USB vbus-gpio numbering for Snow The current vbus GPIOs on snow make very little sense, their number is far above the maximum. As a result, USB doesn't work on snow. Correct the GPIO numbering so they match the current scheme for exynos5. Tested both EHCI and XHCI to correctly work after this change. Signed-off-by: Sjoerd Simons Acked-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/dts/exynos5250-snow.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts index 6fd9275..95af025 100644 --- a/arch/arm/dts/exynos5250-snow.dts +++ b/arch/arm/dts/exynos5250-snow.dts @@ -131,11 +131,11 @@ }; ehci@12110000 { - samsung,vbus-gpio = <&gpio 0x309 0>; /* X11 */ + samsung,vbus-gpio = <&gpio 0xb1 0>; /* X11 */ }; xhci@12000000 { - samsung,vbus-gpio = <&gpio 0x317 0>; /* X27 */ + samsung,vbus-gpio = <&gpio 0xbf 0>; /* X27 */ }; tmu@10060000 { -- cgit v1.1 From bdba13282814224b865223b09f44509090d19fb1 Mon Sep 17 00:00:00 2001 From: Suriyan Ramasami Date: Wed, 29 Oct 2014 09:22:42 -0700 Subject: arm: odroid: enable/disable usb host phy for exynos4412 Enable/disable the usb host phy on the odroid U/X2 boards which are based on the Exynos4412 SOC. Signed-off-by: Suriyan Ramasami Signed-off-by: Minkyu Kang --- arch/arm/cpu/armv7/exynos/power.c | 27 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/power.h | 7 +++++++ 2 files changed, 34 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c index e1ab3d6..1520d64 100644 --- a/arch/arm/cpu/armv7/exynos/power.c +++ b/arch/arm/cpu/armv7/exynos/power.c @@ -53,10 +53,37 @@ void exynos5_set_usbhost_phy_ctrl(unsigned int enable) } } +void exynos4412_set_usbhost_phy_ctrl(unsigned int enable) +{ + struct exynos4412_power *power = + (struct exynos4412_power *)samsung_get_base_power(); + + if (enable) { + /* Enabling USBHOST_PHY */ + setbits_le32(&power->usbhost_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + setbits_le32(&power->hsic1_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + setbits_le32(&power->hsic2_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + } else { + /* Disabling USBHOST_PHY */ + clrbits_le32(&power->usbhost_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + clrbits_le32(&power->hsic1_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + clrbits_le32(&power->hsic2_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + } +} + void set_usbhost_phy_ctrl(unsigned int enable) { if (cpu_is_exynos5()) exynos5_set_usbhost_phy_ctrl(enable); + else if (cpu_is_exynos4()) + if (proid_is_exynos4412()) + exynos4412_set_usbhost_phy_ctrl(enable); } static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable) diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h index e8a98a5..3f97b31 100644 --- a/arch/arm/include/asm/arch-exynos/power.h +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -210,6 +210,13 @@ struct exynos4_power { unsigned int gps_alive_option; }; +struct exynos4412_power { + unsigned char res1[0x0704]; + unsigned int usbhost_phy_control; + unsigned int hsic1_phy_control; + unsigned int hsic2_phy_control; +}; + struct exynos5_power { unsigned int om_stat; unsigned char res1[0x18]; -- cgit v1.1 From 6a23c6533c880d557e786df81fa21b62168db6d9 Mon Sep 17 00:00:00 2001 From: Suriyan Ramasami Date: Wed, 29 Oct 2014 09:22:43 -0700 Subject: arm: odroid: usb: add support for usb host including ethernet This change adds support for enabling the USB host features of the board. This includes the USB3503A hub and the SMC LAN9730 ethernet controller as well. Signed-off-by: Suriyan Ramasami Signed-off-by: Minkyu Kang --- arch/arm/dts/exynos4412-odroid.dts | 11 +++++++++++ arch/arm/include/asm/arch-exynos/ehci.h | 13 +++++++++++++ 2 files changed, 24 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts index 2a1f1dd..c78efec 100644 --- a/arch/arm/dts/exynos4412-odroid.dts +++ b/arch/arm/dts/exynos4412-odroid.dts @@ -67,4 +67,15 @@ div = <0x3>; index = <4>; }; + + ehci@12580000 { + compatible = "samsung,exynos-ehci"; + reg = <0x12580000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + phy { + compatible = "samsung,exynos-usb-phy"; + reg = <0x125B0000 0x100>; + }; + }; }; diff --git a/arch/arm/include/asm/arch-exynos/ehci.h b/arch/arm/include/asm/arch-exynos/ehci.h index d2d70bd..3800fa9 100644 --- a/arch/arm/include/asm/arch-exynos/ehci.h +++ b/arch/arm/include/asm/arch-exynos/ehci.h @@ -12,6 +12,13 @@ #define CLK_24MHZ 5 +#define PHYPWR_NORMAL_MASK_PHY0 (0x39 << 0) +#define PHYPWR_NORMAL_MASK_PHY1 (0x7 << 6) +#define PHYPWR_NORMAL_MASK_HSIC0 (0x7 << 9) +#define PHYPWR_NORMAL_MASK_HSIC1 (0x7 << 12) +#define RSTCON_HOSTPHY_SWRST (0xf << 3) +#define RSTCON_SWRST (0x1 << 0) + #define HOST_CTRL0_PHYSWRSTALL (1 << 31) #define HOST_CTRL0_COMMONON_N (1 << 9) #define HOST_CTRL0_SIDDQ (1 << 6) @@ -61,6 +68,12 @@ struct exynos_usb_phy { unsigned int usbotgtune; }; +struct exynos4412_usb_phy { + unsigned int usbphyctrl; + unsigned int usbphyclk; + unsigned int usbphyrstcon; +}; + /* Switch on the VBUS power. */ int board_usb_vbus_init(void); -- cgit v1.1