From 5f603761c3de00423cad405e064cd2fc822feab1 Mon Sep 17 00:00:00 2001 From: Praveen Rao Date: Mon, 9 Mar 2015 17:12:06 -0500 Subject: ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870 This patch enables the workaround for ARM errata 798870 for OMAP5 / DRA7 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock." An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced here as well. Signed-off-by: Praveen Rao Signed-off-by: Angela Stegmaier Signed-off-by: Nishanth Menon Tested-by: Matt Porter Reviewed-by: Tom Rini --- arch/arm/cpu/armv7/omap5/hwinit.c | 7 +++++++ arch/arm/include/asm/arch-omap5/sys_proto.h | 3 +++ 2 files changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index a8a474a..f806055 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -381,3 +381,10 @@ void setup_warmreset_time(void) rst_val |= rst_time; writel(rst_val, (*prcm)->prm_rsttime); } + +void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr, + u32 cpu_rev_comb, u32 cpu_variant, + u32 cpu_rev) +{ + omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl); +} diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 1038303..ea84665 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -66,4 +66,7 @@ static inline u32 usec_to_32k(u32 usec) { return div_round_up(32768 * usec, 1000000); } + +#define OMAP5_SERVICE_L2ACTLR_SET 0x104 + #endif -- cgit v1.1