From 6a00a9cb1536c5a19269d539642fb1cced0b5a9f Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 1 Sep 2015 10:47:27 +0800 Subject: armv8/fsl-lsch3: fdt: Check the pointer returned from call to a function may be NULL Pointer 'reg' returned from call to function 'fdt_getprop' may be NULL, will be passed to function and may be dereferenced there by passing argument 1 to function 'of_read_number'. So check pointer 'reg' first. Signed-off-by: Alison Wang Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/fdt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c index 567c419..922e8a0 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c @@ -33,8 +33,8 @@ void ft_fixup_cpu(void *blob) off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); while (off != -FDT_ERR_NOTFOUND) { reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0); - core_id = of_read_number(reg, addr_cells); if (reg) { + core_id = of_read_number(reg, addr_cells); if (core_id == 0 || (is_core_online(core_id))) { val = spin_tbl_addr; val += id_to_core(core_id) * -- cgit v1.1 From 0cbba8e9532f1e8cff5190baf7a4f23c27f67db4 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Wed, 28 Oct 2015 10:40:23 +0800 Subject: ls102xa: fdt: Disable IFC in SD boot for QSPI As QSPI/DSPI and IFC are pin multiplexed, IFC is disabled in SD boot for QSPI. This patch will add fdt support for this rule. Signed-off-by: Alison Wang Reviewed-by: York Sun --- arch/arm/cpu/armv7/ls102xa/fdt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index e01d911..856abed 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -171,7 +171,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan", "clock-frequency", busclk / 2, 1); -#ifdef CONFIG_QSPI_BOOT +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT, CONFIG_SYS_IFC_ADDR); fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); -- cgit v1.1 From f4f0b7403a06d2642ca40e6a0b18ee7336f276a8 Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Thu, 17 Sep 2015 16:16:35 +0530 Subject: Data types defined for 64 bit physical address Data types and I/O functions have been defined for 64 bit physical addresses in arm. Signed-off-by: Aneesh Bansal Reviewed-by: York Sun --- arch/arm/include/asm/io.h | 4 ++-- arch/arm/include/asm/types.h | 10 +++++++--- 2 files changed, 9 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index bfbe0a0..75773bd 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -46,7 +46,7 @@ static inline void sync(void) static inline void * map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) { - return (void *)paddr; + return (void *)((unsigned long)paddr); } /* @@ -59,7 +59,7 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags) static inline phys_addr_t virt_to_phys(void * vaddr) { - return (phys_addr_t)(vaddr); + return (phys_addr_t)((unsigned long)vaddr); } /* diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h index ee77c41..388058e 100644 --- a/arch/arm/include/asm/types.h +++ b/arch/arm/include/asm/types.h @@ -45,12 +45,16 @@ typedef unsigned long long u64; #define BITS_PER_LONG 32 #endif /* CONFIG_ARM64 */ -/* Dma addresses are 32-bits wide. */ - +#ifdef CONFIG_PHYS_64BIT +typedef unsigned long long dma_addr_t; +typedef unsigned long long phys_addr_t; +typedef unsigned long long phys_size_t; +#else +/* DMA addresses are 32-bits wide */ typedef u32 dma_addr_t; - typedef unsigned long phys_addr_t; typedef unsigned long phys_size_t; +#endif #endif /* __KERNEL__ */ -- cgit v1.1 From 5757e06c69a02fe95208a503504756b7d422e64f Mon Sep 17 00:00:00 2001 From: "horia.geanta@freescale.com" Date: Thu, 15 Oct 2015 14:21:31 +0300 Subject: arm: ls102xa: enable snooping for CAAM transactions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable snooping for CAAM read & write transactions by programming the SCFG snoop configuration register: SCFG_SNPCNFGCR[SECRDSNP] SCFG_SNPCNFGCR[SECWRSNP] Signed-off-by: Horia Geantă Reviewed-by: Zhengxiong Jin Reviewed-by: York Sun --- arch/arm/cpu/armv7/ls102xa/cpu.c | 3 +++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 + 2 files changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index e2eb5f3..df2e1b7 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -301,6 +301,7 @@ int arch_cpu_init(void) void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); void *rcpm2_base = (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET); + struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; u32 state; /* @@ -328,6 +329,8 @@ int arch_cpu_init(void) */ fsl_epu_clean(epu_base); + setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR); + return 0; } diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 60aa0d3..fbd06ba 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -144,6 +144,7 @@ struct ccsr_gur { }; #define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00 +#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 #define SCFG_ETSECCMCR_GE0_CLK125 0x00000000 #define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 -- cgit v1.1 From 435acd83b2b4f31699732f090d28d66cabb05912 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Mon, 26 Oct 2015 19:47:41 +0800 Subject: armv7/ls1021a: move ns_access to common file Config Security Level Register is different between different SoCs, so put the CSL register definition into the arch specific directory. Signed-off-by: Mingkai Hu Signed-off-by: Hou Zhiqiang Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- arch/arm/include/asm/arch-ls102xa/ns_access.h | 103 ++++++++++++++++++++------ 1 file changed, 82 insertions(+), 21 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h b/arch/arm/include/asm/arch-ls102xa/ns_access.h index b53f699..a921fb6 100644 --- a/arch/arm/include/asm/arch-ls102xa/ns_access.h +++ b/arch/arm/include/asm/arch-ls102xa/ns_access.h @@ -7,22 +7,6 @@ #ifndef __FSL_NS_ACCESS_H_ #define __FSL_NS_ACCESS_H_ -enum csu_cslx_access { - CSU_NS_SUP_R = 0x08, - CSU_NS_SUP_W = 0x80, - CSU_NS_SUP_RW = 0x88, - CSU_NS_USER_R = 0x04, - CSU_NS_USER_W = 0x40, - CSU_NS_USER_RW = 0x44, - CSU_S_SUP_R = 0x02, - CSU_S_SUP_W = 0x20, - CSU_S_SUP_RW = 0x22, - CSU_S_USER_R = 0x01, - CSU_S_USER_W = 0x10, - CSU_S_USER_RW = 0x11, - CSU_ALL_RW = 0xff, -}; - enum csu_cslx_ind { CSU_CSLX_PCIE2_IO = 0, CSU_CSLX_PCIE1_IO, @@ -108,11 +92,88 @@ enum csu_cslx_ind { CSU_CSLX_MAX, }; -struct csu_ns_dev { - unsigned long ind; - uint32_t val; +static struct csu_ns_dev ns_dev[] = { + { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, + { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, + { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, + { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, + { CSU_CSLX_OCRAM, CSU_ALL_RW }, + { CSU_CSLX_GIC, CSU_ALL_RW }, + { CSU_CSLX_PCIE1, CSU_ALL_RW }, + { CSU_CSLX_OCRAM2, CSU_ALL_RW }, + { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, + { CSU_CSLX_PCIE2, CSU_ALL_RW }, + { CSU_CSLX_SATA, CSU_ALL_RW }, + { CSU_CSLX_USB3, CSU_ALL_RW }, + { CSU_CSLX_SERDES, CSU_ALL_RW }, + { CSU_CSLX_QDMA, CSU_ALL_RW }, + { CSU_CSLX_LPUART2, CSU_ALL_RW }, + { CSU_CSLX_LPUART1, CSU_ALL_RW }, + { CSU_CSLX_LPUART4, CSU_ALL_RW }, + { CSU_CSLX_LPUART3, CSU_ALL_RW }, + { CSU_CSLX_LPUART6, CSU_ALL_RW }, + { CSU_CSLX_LPUART5, CSU_ALL_RW }, + { CSU_CSLX_DSPI2, CSU_ALL_RW }, + { CSU_CSLX_DSPI1, CSU_ALL_RW }, + { CSU_CSLX_QSPI, CSU_ALL_RW }, + { CSU_CSLX_ESDHC, CSU_ALL_RW }, + { CSU_CSLX_2D_ACE, CSU_ALL_RW }, + { CSU_CSLX_IFC, CSU_ALL_RW }, + { CSU_CSLX_I2C1, CSU_ALL_RW }, + { CSU_CSLX_USB2, CSU_ALL_RW }, + { CSU_CSLX_I2C3, CSU_ALL_RW }, + { CSU_CSLX_I2C2, CSU_ALL_RW }, + { CSU_CSLX_DUART2, CSU_ALL_RW }, + { CSU_CSLX_DUART1, CSU_ALL_RW }, + { CSU_CSLX_WDT2, CSU_ALL_RW }, + { CSU_CSLX_WDT1, CSU_ALL_RW }, + { CSU_CSLX_EDMA, CSU_ALL_RW }, + { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, + { CSU_CSLX_DDR, CSU_ALL_RW }, + { CSU_CSLX_QUICC, CSU_ALL_RW }, + { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, + { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, + { CSU_CSLX_SFP, CSU_ALL_RW }, + { CSU_CSLX_TMU, CSU_ALL_RW }, + { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, + { CSU_CSLX_RESERVED0, CSU_ALL_RW }, + { CSU_CSLX_ETSEC1, CSU_ALL_RW }, + { CSU_CSLX_SEC5_5, CSU_ALL_RW }, + { CSU_CSLX_ETSEC3, CSU_ALL_RW }, + { CSU_CSLX_ETSEC2, CSU_ALL_RW }, + { CSU_CSLX_GPIO2, CSU_ALL_RW }, + { CSU_CSLX_GPIO1, CSU_ALL_RW }, + { CSU_CSLX_GPIO4, CSU_ALL_RW }, + { CSU_CSLX_GPIO3, CSU_ALL_RW }, + { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, + { CSU_CSLX_CSU, CSU_ALL_RW }, + { CSU_CSLX_ASRC, CSU_ALL_RW }, + { CSU_CSLX_SPDIF, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, + { CSU_CSLX_SAI2, CSU_ALL_RW }, + { CSU_CSLX_SAI1, CSU_ALL_RW }, + { CSU_CSLX_SAI4, CSU_ALL_RW }, + { CSU_CSLX_SAI3, CSU_ALL_RW }, + { CSU_CSLX_FTM2, CSU_ALL_RW }, + { CSU_CSLX_FTM1, CSU_ALL_RW }, + { CSU_CSLX_FTM4, CSU_ALL_RW }, + { CSU_CSLX_FTM3, CSU_ALL_RW }, + { CSU_CSLX_FTM6, CSU_ALL_RW }, + { CSU_CSLX_FTM5, CSU_ALL_RW }, + { CSU_CSLX_FTM8, CSU_ALL_RW }, + { CSU_CSLX_FTM7, CSU_ALL_RW }, + { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, + { CSU_CSLX_EPU, CSU_ALL_RW }, + { CSU_CSLX_GDI, CSU_ALL_RW }, + { CSU_CSLX_DDI, CSU_ALL_RW }, + { CSU_CSLX_RESERVED1, CSU_ALL_RW }, + { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, + { CSU_CSLX_RESERVED2, CSU_ALL_RW }, }; -void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num); - #endif -- cgit v1.1 From 9f3183d2d69f6d392fb943d249934f8648531e7e Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Mon, 26 Oct 2015 19:47:50 +0800 Subject: armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu Signed-off-by: Hou Zhiqiang Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- arch/arm/cpu/armv8/Makefile | 2 +- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 21 + arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 | 244 ++++++++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 514 +++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/cpu.h | 8 + arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 198 +++++++ .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 146 +++++ .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 189 ++++++ arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 363 ++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/ls2085a_serdes.c | 116 ++++ arch/arm/cpu/armv8/fsl-layerscape/mp.c | 183 ++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 86 +++ arch/arm/cpu/armv8/fsl-layerscape/spl.c | 76 +++ arch/arm/cpu/armv8/fsl-lsch3/Makefile | 13 - arch/arm/cpu/armv8/fsl-lsch3/README | 244 -------- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 638 --------------------- arch/arm/cpu/armv8/fsl-lsch3/cpu.h | 8 - arch/arm/cpu/armv8/fsl-lsch3/fdt.c | 189 ------ arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c | 146 ----- arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S | 355 ------------ arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c | 117 ---- arch/arm/cpu/armv8/fsl-lsch3/mp.c | 183 ------ arch/arm/cpu/armv8/fsl-lsch3/mp.h | 38 -- arch/arm/cpu/armv8/fsl-lsch3/soc.c | 107 ---- arch/arm/cpu/armv8/fsl-lsch3/speed.c | 189 ------ arch/arm/cpu/armv8/fsl-lsch3/speed.h | 7 - arch/arm/include/asm/arch-fsl-layerscape/clock.h | 24 + arch/arm/include/asm/arch-fsl-layerscape/config.h | 96 ++++ arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 165 ++++++ arch/arm/include/asm/arch-fsl-layerscape/fdt.h | 14 + .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 66 +++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 268 +++++++++ .../arm/include/asm/arch-fsl-layerscape/imx-regs.h | 55 ++ .../asm/arch-fsl-layerscape/ls2085a_stream_id.h | 64 +++ arch/arm/include/asm/arch-fsl-layerscape/mmu.h | 10 + arch/arm/include/asm/arch-fsl-layerscape/mp.h | 38 ++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 47 ++ arch/arm/include/asm/arch-fsl-layerscape/speed.h | 10 + arch/arm/include/asm/arch-fsl-lsch3/clock.h | 24 - arch/arm/include/asm/arch-fsl-lsch3/config.h | 185 ------ arch/arm/include/asm/arch-fsl-lsch3/fdt.h | 10 - arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h | 67 --- arch/arm/include/asm/arch-fsl-lsch3/gpio.h | 9 - arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 183 ------ arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h | 13 - .../include/asm/arch-fsl-lsch3/ls2085a_stream_id.h | 64 --- arch/arm/include/asm/arch-fsl-lsch3/soc.h | 28 - arch/arm/include/asm/config.h | 7 +- 48 files changed, 3004 insertions(+), 2823 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/Makefile create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/cpu.c create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/cpu.h create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/fdt.c create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls2085a_serdes.c create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/mp.c create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/soc.c create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/spl.c delete mode 100644 arch/arm/cpu/armv8/fsl-lsch3/Makefile delete mode 100644 arch/arm/cpu/armv8/fsl-lsch3/README delete mode 100644 arch/arm/cpu/armv8/fsl-lsch3/cpu.c delete mode 100644 arch/arm/cpu/armv8/fsl-lsch3/cpu.h delete mode 100644 arch/arm/cpu/armv8/fsl-lsch3/fdt.c delete mode 100644 arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c delete mode 100644 arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S delete mode 100644 arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c delete mode 100644 arch/arm/cpu/armv8/fsl-lsch3/mp.c delete mode 100644 arch/arm/cpu/armv8/fsl-lsch3/mp.h delete mode 100644 arch/arm/cpu/armv8/fsl-lsch3/soc.c delete mode 100644 arch/arm/cpu/armv8/fsl-lsch3/speed.c delete mode 100644 arch/arm/cpu/armv8/fsl-lsch3/speed.h create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/clock.h create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/config.h create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/cpu.h create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fdt.h create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/ls2085a_stream_id.h create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/mmu.h create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/mp.h create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/soc.h create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/speed.h delete mode 100644 arch/arm/include/asm/arch-fsl-lsch3/clock.h delete mode 100644 arch/arm/include/asm/arch-fsl-lsch3/config.h delete mode 100644 arch/arm/include/asm/arch-fsl-lsch3/fdt.h delete mode 100644 arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h delete mode 100644 arch/arm/include/asm/arch-fsl-lsch3/gpio.h delete mode 100644 arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h delete mode 100644 arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h delete mode 100644 arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h delete mode 100644 arch/arm/include/asm/arch-fsl-lsch3/soc.h (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index adb11b3..48c041b 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -15,6 +15,6 @@ obj-y += cache.o obj-y += tlb.o obj-y += transition.o -obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/ +obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/ obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/ obj-$(CONFIG_TARGET_HIKEY) += hisilicon/ diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile new file mode 100644 index 0000000..ccb3aa5 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -0,0 +1,21 @@ +# +# Copyright 2014-2015, Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cpu.o +obj-y += lowlevel.o +obj-y += soc.o +obj-$(CONFIG_MP) += mp.o +obj-$(CONFIG_OF_LIBFDT) += fdt.o +obj-$(CONFIG_SPL) += spl.o + +ifneq ($(CONFIG_FSL_LSCH3),) +obj-y += fsl_lsch3_speed.o +obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o +endif + +ifneq ($(CONFIG_LS2085A),) +obj-$(CONFIG_SYS_HAS_SERDES) += ls2085a_serdes.o +endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 new file mode 100644 index 0000000..03e18f6 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 @@ -0,0 +1,244 @@ +# +# Copyright 2014-2015 Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +Freescale LayerScape with Chassis Generation 3 + +This architecture supports Freescale ARMv8 SoCs with Chassis generation 3, +for example LS2085A. + +DDR Layout +============ +Entire DDR region splits into two regions. + - Region 1 is at address 0x8000_0000 to 0xffff_ffff. + - Region 2 is at 0x80_8000_0000 to the top of total memory, + for example 16GB, 0x83_ffff_ffff. + +All DDR memory is marked as cache-enabled. + +When MC and Debug server is enabled, they carve 512MB away from the high +end of DDR. For example, if the total DDR is 16GB, it shrinks to 15.5GB +with MC and Debug server enabled. Linux only sees 15.5GB. + +The reserved 512MB layout looks like + + +---------------+ <-- top/end of memory + | 256MB | debug server + +---------------+ + | 256MB | MC + +---------------+ + | ... | + +MC requires the memory to be aligned with 512MB, so even debug server is +not enabled, 512MB is reserved, not 256MB. + +Flash Layout +============ + +(1) A typical layout of various images (including Linux and other firmware images) + is shown below considering a 32MB NOR flash device present on most + pre-silicon platforms (simulator and emulator): + + ------------------------- + | FIT Image | + | (linux + DTB + RFS) | + ------------------------- ----> 0x0120_0000 + | Debug Server FW | + ------------------------- ----> 0x00C0_0000 + | AIOP FW | + ------------------------- ----> 0x0070_0000 + | MC FW | + ------------------------- ----> 0x006C_0000 + | MC DPL Blob | + ------------------------- ----> 0x0020_0000 + | BootLoader + Env| + ------------------------- ----> 0x0000_1000 + | PBI | + ------------------------- ----> 0x0000_0080 + | RCW | + ------------------------- ----> 0x0000_0000 + + 32-MB NOR flash layout for pre-silicon platforms (simulator and emulator) + +(2) A typical layout of various images (including Linux and other firmware images) + is shown below considering a 128MB NOR flash device present on QDS and RDB + boards: + ----------------------------------------- ----> 0x5_8800_0000 --- + | .. Unused .. (7M) | | + ----------------------------------------- ----> 0x5_8790_0000 | + | FIT Image (linux + DTB + RFS) (40M) | | + ----------------------------------------- ----> 0x5_8510_0000 | + | PHY firmware (2M) | | + ----------------------------------------- ----> 0x5_84F0_0000 | 64K + | Debug Server FW (2M) | | Alt + ----------------------------------------- ----> 0x5_84D0_0000 | Bank + | AIOP FW (4M) | | + ----------------------------------------- ----> 0x5_8490_0000 (vbank4) + | MC DPC Blob (1M) | | + ----------------------------------------- ----> 0x5_8480_0000 | + | MC DPL Blob (1M) | | + ----------------------------------------- ----> 0x5_8470_0000 | + | MC FW (4M) | | + ----------------------------------------- ----> 0x5_8430_0000 | + | BootLoader Environment (1M) | | + ----------------------------------------- ----> 0x5_8420_0000 | + | BootLoader (1M) | | + ----------------------------------------- ----> 0x5_8410_0000 | + | RCW and PBI (1M) | | + ----------------------------------------- ----> 0x5_8400_0000 --- + | .. Unused .. (7M) | | + ----------------------------------------- ----> 0x5_8390_0000 | + | FIT Image (linux + DTB + RFS) (40M) | | + ----------------------------------------- ----> 0x5_8110_0000 | + | PHY firmware (2M) | | + ----------------------------------------- ----> 0x5_80F0_0000 | 64K + | Debug Server FW (2M) | | Bank + ----------------------------------------- ----> 0x5_80D0_0000 | + | AIOP FW (4M) | | + ----------------------------------------- ----> 0x5_8090_0000 (vbank0) + | MC DPC Blob (1M) | | + ----------------------------------------- ----> 0x5_8080_0000 | + | MC DPL Blob (1M) | | + ----------------------------------------- ----> 0x5_8070_0000 | + | MC FW (4M) | | + ----------------------------------------- ----> 0x5_8030_0000 | + | BootLoader Environment (1M) | | + ----------------------------------------- ----> 0x5_8020_0000 | + | BootLoader (1M) | | + ----------------------------------------- ----> 0x5_8010_0000 | + | RCW and PBI (1M) | | + ----------------------------------------- ----> 0x5_8000_0000 --- + + 128-MB NOR flash layout for QDS and RDB boards + +Environment Variables +===================== +mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined + the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. + +mcmemsize: MC DRAM block size. If this variable is not defined, the value + CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. + +Booting from NAND +------------------- +Booting from NAND requires two images, RCW and u-boot-with-spl.bin. +The difference between NAND boot RCW image and NOR boot image is the PBI +command sequence. Below is one example for PBI commands for QDS which uses +NAND device with 2KB/page, block size 128KB. + +1) CCSR 4-byte write to 0x00e00404, data=0x00000000 +2) CCSR 4-byte write to 0x00e00400, data=0x1800a000 +The above two commands set bootloc register to 0x00000000_1800a000 where +the u-boot code will be running in OCRAM. + +3) Block Copy: SRC=0x0107, SRC_ADDR=0x00020000, DEST_ADDR=0x1800a000, +BLOCK_SIZE=0x00014000 +This command copies u-boot image from NAND device into OCRAM. The values need +to adjust accordingly. + +SRC should match the cfg_rcw_src, the reset config pins. It depends + on the NAND device. See reference manual for cfg_rcw_src. +SRC_ADDR is the offset of u-boot-with-spl.bin image in NAND device. In + the example above, 128KB. For easy maintenance, we put it at + the beginning of next block from RCW. +DEST_ADDR is fixed at 0x1800a000, matching bootloc set above. +BLOCK_SIZE is the size to be copied by PBI. + +RCW image should be written to the beginning of NAND device. Example of using +u-boot command + +nand write 0 + +To form the NAND image, build u-boot with NAND config, for example, +ls2085aqds_nand_defconfig. The image needed is u-boot-with-spl.bin. +The u-boot image should be written to match SRC_ADDR, in above example 0x20000. + +nand write 200000 + +With these two images in NAND device, the board can boot from NAND. + +Another example for RDB boards, + +1) CCSR 4-byte write to 0x00e00404, data=0x00000000 +2) CCSR 4-byte write to 0x00e00400, data=0x1800a000 +3) Block Copy: SRC=0x0119, SRC_ADDR=0x00080000, DEST_ADDR=0x1800a000, +BLOCK_SIZE=0x00014000 + +nand write 0 +nand write 80000 + +Notice the difference from QDS is SRC, SRC_ADDR and the offset of u-boot image +to match board NAND device with 4KB/page, block size 512KB. + +MMU Translation Tables +====================== + +(1) Early MMU Tables: + + Level 0 Level 1 Level 2 +------------------ ------------------ ------------------ +| 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 | +------------------ ------------------ ------------------ +| 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 | +------------------ | ------------------ ------------------ +| invalid | | | 0x00_8000_0000 | | 0x00_0040_0000 | +------------------ | ------------------ ------------------ + | | 0x00_c000_0000 | | 0x00_0060_0000 | + | ------------------ ------------------ + | | 0x01_0000_0000 | | 0x00_0080_0000 | + | ------------------ ------------------ + | ... ... + | ------------------ + | | 0x05_8000_0000 | --| + | ------------------ | + | | 0x05_c000_0000 | | + | ------------------ | + | ... | + | ------------------ | ------------------ + |--> | 0x80_0000_0000 | |-> | 0x00_3000_0000 | + ------------------ ------------------ + | 0x80_4000_0000 | | 0x00_3020_0000 | + ------------------ ------------------ + | 0x80_8000_0000 | | 0x00_3040_0000 | + ------------------ ------------------ + | 0x80_c000_0000 | | 0x00_3060_0000 | + ------------------ ------------------ + | 0x81_0000_0000 | | 0x00_3080_0000 | + ------------------ ------------------ + ... ... + +(2) Final MMU Tables: + + Level 0 Level 1 Level 2 +------------------ ------------------ ------------------ +| 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 | +------------------ ------------------ ------------------ +| 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 | +------------------ | ------------------ ------------------ +| invalid | | | 0x00_8000_0000 | | 0x00_0040_0000 | +------------------ | ------------------ ------------------ + | | 0x00_c000_0000 | | 0x00_0060_0000 | + | ------------------ ------------------ + | | 0x01_0000_0000 | | 0x00_0080_0000 | + | ------------------ ------------------ + | ... ... + | ------------------ + | | 0x08_0000_0000 | --| + | ------------------ | + | | 0x08_4000_0000 | | + | ------------------ | + | ... | + | ------------------ | ------------------ + |--> | 0x80_0000_0000 | |--> | 0x08_0000_0000 | + ------------------ ------------------ + | 0x80_4000_0000 | | 0x08_0020_0000 | + ------------------ ------------------ + | 0x80_8000_0000 | | 0x08_0040_0000 | + ------------------ ------------------ + | 0x80_c000_0000 | | 0x08_0060_0000 | + ------------------ ------------------ + | 0x81_0000_0000 | | 0x08_0080_0000 | + ------------------ ------------------ + ... ... diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c new file mode 100644 index 0000000..be7442d --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -0,0 +1,514 @@ +/* + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_MP +#include +#endif +#include +#include +#include +#ifdef CONFIG_FSL_ESDHC +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +void cpu_name(char *name) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int i, svr, ver; + + svr = gur_in32(&gur->svr); + ver = SVR_SOC_VER(svr); + + for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) + if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) { + strcpy(name, cpu_type_list[i].name); + + if (IS_E_PROCESSOR(svr)) + strcat(name, "E"); + break; + } + + if (i == ARRAY_SIZE(cpu_type_list)) + strcpy(name, "unknown"); +} + +#ifndef CONFIG_SYS_DCACHE_OFF +/* + * Set the block entries according to the information of the table. + */ +static int set_block_entry(const struct sys_mmu_table *list, + struct table_info *table) +{ + u64 block_size = 0, block_shift = 0; + u64 block_addr, index; + int j; + + if (table->entry_size == BLOCK_SIZE_L1) { + block_size = BLOCK_SIZE_L1; + block_shift = SECTION_SHIFT_L1; + } else if (table->entry_size == BLOCK_SIZE_L2) { + block_size = BLOCK_SIZE_L2; + block_shift = SECTION_SHIFT_L2; + } else { + return -EINVAL; + } + + block_addr = list->phys_addr; + index = (list->virt_addr - table->table_base) >> block_shift; + + for (j = 0; j < (list->size >> block_shift); j++) { + set_pgtable_section(table->ptr, + index, + block_addr, + list->memory_type, + list->share); + block_addr += block_size; + index++; + } + + return 0; +} + +/* + * Find the corresponding table entry for the list. + */ +static int find_table(const struct sys_mmu_table *list, + struct table_info *table, u64 *level0_table) +{ + u64 index = 0, level = 0; + u64 *level_table = level0_table; + u64 temp_base = 0, block_size = 0, block_shift = 0; + + while (level < 3) { + if (level == 0) { + block_size = BLOCK_SIZE_L0; + block_shift = SECTION_SHIFT_L0; + } else if (level == 1) { + block_size = BLOCK_SIZE_L1; + block_shift = SECTION_SHIFT_L1; + } else if (level == 2) { + block_size = BLOCK_SIZE_L2; + block_shift = SECTION_SHIFT_L2; + } + + index = 0; + while (list->virt_addr >= temp_base) { + index++; + temp_base += block_size; + } + + temp_base -= block_size; + + if ((level_table[index - 1] & PMD_TYPE_MASK) == + PMD_TYPE_TABLE) { + level_table = (u64 *)(level_table[index - 1] & + ~PMD_TYPE_MASK); + level++; + continue; + } else { + if (level == 0) + return -EINVAL; + + if ((list->phys_addr + list->size) > + (temp_base + block_size * NUM_OF_ENTRY)) + return -EINVAL; + + /* + * Check the address and size of the list member is + * aligned with the block size. + */ + if (((list->phys_addr & (block_size - 1)) != 0) || + ((list->size & (block_size - 1)) != 0)) + return -EINVAL; + + table->ptr = level_table; + table->table_base = temp_base - + ((index - 1) << block_shift); + table->entry_size = block_size; + + return 0; + } + } + return -EINVAL; +} + +/* + * To start MMU before DDR is available, we create MMU table in SRAM. + * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three + * levels of translation tables here to cover 40-bit address space. + * We use 4KB granule size, with 40 bits physical address, T0SZ=24 + * Level 0 IA[39], table address @0 + * Level 1 IA[38:30], table address @0x1000, 0x2000 + * Level 2 IA[29:21], table address @0x3000, 0x4000 + * Address above 0x5000 is free for other purpose. + */ +static inline void early_mmu_setup(void) +{ + unsigned int el, i; + u64 *level0_table = (u64 *)CONFIG_SYS_FSL_OCRAM_BASE; + u64 *level1_table0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x1000); + u64 *level1_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000); + u64 *level2_table0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000); + u64 *level2_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x4000); + + struct table_info table = {level0_table, 0, BLOCK_SIZE_L0}; + + /* Invalidate all table entries */ + memset(level0_table, 0, 0x5000); + + /* Fill in the table entries */ + set_pgtable_table(level0_table, 0, level1_table0); + set_pgtable_table(level0_table, 1, level1_table1); + set_pgtable_table(level1_table0, 0, level2_table0); + +#ifdef CONFIG_FSL_LSCH3 + set_pgtable_table(level1_table0, + CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1, + level2_table1); +#endif + /* Find the table and fill in the block entries */ + for (i = 0; i < ARRAY_SIZE(early_mmu_table); i++) { + if (find_table(&early_mmu_table[i], + &table, level0_table) == 0) { + /* + * If find_table() returns error, it cannot be dealt + * with here. Breakpoint can be added for debugging. + */ + set_block_entry(&early_mmu_table[i], &table); + /* + * If set_block_entry() returns error, it cannot be + * dealt with here too. + */ + } + } + + el = current_el(); + + set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR, + MEMORY_ATTRIBUTES); + set_sctlr(get_sctlr() | CR_M); +} + +/* + * The final tables look similar to early tables, but different in detail. + * These tables are in DRAM. Sub tables are added to enable cache for + * QBMan and OCRAM. + * + * Level 1 table 0 contains 512 entries for each 1GB from 0 to 512GB. + * Level 1 table 1 contains 512 entries for each 1GB from 512GB to 1TB. + * Level 2 table 0 contains 512 entries for each 2MB from 0 to 1GB. + * + * For LSCH3: + * Level 2 table 1 contains 512 entries for each 2MB from 32GB to 33GB. + */ +static inline void final_mmu_setup(void) +{ + unsigned int el, i; + u64 *level0_table = (u64 *)gd->arch.tlb_addr; + u64 *level1_table0 = (u64 *)(gd->arch.tlb_addr + 0x1000); + u64 *level1_table1 = (u64 *)(gd->arch.tlb_addr + 0x2000); + u64 *level2_table0 = (u64 *)(gd->arch.tlb_addr + 0x3000); +#ifdef CONFIG_FSL_LSCH3 + u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000); +#endif + struct table_info table = {level0_table, 0, BLOCK_SIZE_L0}; + + /* Invalidate all table entries */ + memset(level0_table, 0, PGTABLE_SIZE); + + /* Fill in the table entries */ + set_pgtable_table(level0_table, 0, level1_table0); + set_pgtable_table(level0_table, 1, level1_table1); + set_pgtable_table(level1_table0, 0, level2_table0); +#ifdef CONFIG_FSL_LSCH3 + set_pgtable_table(level1_table0, + CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1, + level2_table1); +#endif + + /* Find the table and fill in the block entries */ + for (i = 0; i < ARRAY_SIZE(final_mmu_table); i++) { + if (find_table(&final_mmu_table[i], + &table, level0_table) == 0) { + if (set_block_entry(&final_mmu_table[i], + &table) != 0) { + printf("MMU error: could not set block entry for %p\n", + &final_mmu_table[i]); + } + + } else { + printf("MMU error: could not find the table for %p\n", + &final_mmu_table[i]); + } + } + + /* flush new MMU table */ + flush_dcache_range(gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + + /* point TTBR to the new table */ + el = current_el(); + + set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR_FINAL, + MEMORY_ATTRIBUTES); + /* + * MMU is already enabled, just need to invalidate TLB to load the + * new table. The new table is compatible with the current table, if + * MMU somehow walks through the new table before invalidation TLB, + * it still works. So we don't need to turn off MMU here. + */ +} + +int arch_cpu_init(void) +{ + icache_enable(); + __asm_invalidate_dcache_all(); + __asm_invalidate_tlb_all(); + early_mmu_setup(); + set_sctlr(get_sctlr() | CR_C); + return 0; +} + +/* + * This function is called from lib/board.c. + * It recreates MMU table in main memory. MMU and d-cache are enabled earlier. + * There is no need to disable d-cache for this operation. + */ +void enable_caches(void) +{ + final_mmu_setup(); + __asm_invalidate_tlb_all(); +} +#endif + +static inline u32 initiator_type(u32 cluster, int init_id) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; + u32 type = 0; + + type = gur_in32(&gur->tp_ityp[idx]); + if (type & TP_ITYP_AV) + return type; + + return 0; +} + +u32 cpu_mask(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + int i = 0, count = 0; + u32 cluster, type, mask = 0; + + do { + int j; + + cluster = gur_in32(&gur->tp_cluster[i].lower); + for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { + type = initiator_type(cluster, j); + if (type) { + if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM) + mask |= 1 << count; + count++; + } + } + i++; + } while ((cluster & TP_CLUSTER_EOC) == 0x0); + + return mask; +} + +/* + * Return the number of cores on this SOC. + */ +int cpu_numcores(void) +{ + return hweight32(cpu_mask()); +} + +int fsl_qoriq_core_to_cluster(unsigned int core) +{ + struct ccsr_gur __iomem *gur = + (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); + int i = 0, count = 0; + u32 cluster; + + do { + int j; + + cluster = gur_in32(&gur->tp_cluster[i].lower); + for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { + if (initiator_type(cluster, j)) { + if (count == core) + return i; + count++; + } + } + i++; + } while ((cluster & TP_CLUSTER_EOC) == 0x0); + + return -1; /* cannot identify the cluster */ +} + +u32 fsl_qoriq_core_to_type(unsigned int core) +{ + struct ccsr_gur __iomem *gur = + (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); + int i = 0, count = 0; + u32 cluster, type; + + do { + int j; + + cluster = gur_in32(&gur->tp_cluster[i].lower); + for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { + type = initiator_type(cluster, j); + if (type) { + if (count == core) + return type; + count++; + } + } + i++; + } while ((cluster & TP_CLUSTER_EOC) == 0x0); + + return -1; /* cannot identify the cluster */ +} + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct sys_info sysinfo; + char buf[32]; + unsigned int i, core; + u32 type, rcw; + + puts("SoC: "); + + cpu_name(buf); + printf(" %s (0x%x)\n", buf, gur_in32(&gur->svr)); + memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); + get_sys_info(&sysinfo); + puts("Clock Configuration:"); + for_each_cpu(i, core, cpu_numcores(), cpu_mask()) { + if (!(i % 3)) + puts("\n "); + type = TP_ITYP_VER(fsl_qoriq_core_to_type(core)); + printf("CPU%d(%s):%-4s MHz ", core, + type == TY_ITYP_VER_A7 ? "A7 " : + (type == TY_ITYP_VER_A53 ? "A53" : + (type == TY_ITYP_VER_A57 ? "A57" : " ")), + strmhz(buf, sysinfo.freq_processor[core])); + } + printf("\n Bus: %-4s MHz ", + strmhz(buf, sysinfo.freq_systembus)); + printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus)); +#ifdef CONFIG_FSL_LSCH3 + printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2)); +#endif + puts("\n"); + + /* + * Display the RCW, so that no one gets confused as to what RCW + * we're actually using for this boot. + */ + puts("Reset Configuration Word (RCW):"); + for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { + rcw = gur_in32(&gur->rcwsr[i]); + if ((i % 4) == 0) + printf("\n %08x:", i * 4); + printf(" %08x", rcw); + } + puts("\n"); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC +int cpu_mmc_init(bd_t *bis) +{ + return fsl_esdhc_mmc_init(bis); +} +#endif + +int cpu_eth_init(bd_t *bis) +{ + int error = 0; + +#ifdef CONFIG_FSL_MC_ENET + error = fsl_mc_ldpaa_init(bis); +#endif + return error; +} + +int arch_early_init_r(void) +{ +#ifdef CONFIG_MP + int rv = 1; + + rv = fsl_layerscape_wake_seconday_cores(); + if (rv) + printf("Did not wake secondary cores\n"); +#endif + +#ifdef CONFIG_SYS_HAS_SERDES + fsl_serdes_init(); +#endif + return 0; +} + +int timer_init(void) +{ + u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR; +#ifdef CONFIG_FSL_LSCH3 + u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; +#endif +#ifdef COUNTER_FREQUENCY_REAL + unsigned long cntfrq = COUNTER_FREQUENCY_REAL; + + /* Update with accurate clock frequency */ + asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory"); +#endif + +#ifdef CONFIG_FSL_LSCH3 + /* Enable timebase for all clusters. + * It is safe to do so even some clusters are not enabled. + */ + out_le32(cltbenr, 0xf); +#endif + + /* Enable clock for timer + * This is a global setting. + */ + out_le32(cntcr, 0x1); + + return 0; +} + +void reset_cpu(ulong addr) +{ + u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR; + u32 val; + + /* Raise RESET_REQ_B */ + val = scfg_in32(rstcr); + val |= 0x02; + scfg_out32(rstcr, val); +} diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.h b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h new file mode 100644 index 0000000..8072f3c --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h @@ -0,0 +1,8 @@ +/* + * Copyright 2014-2015, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +int fsl_qoriq_core_to_cluster(unsigned int core); +u32 cpu_mask(void); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c new file mode 100644 index 0000000..4839e33 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -0,0 +1,198 @@ +/* + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#ifdef CONFIG_FSL_LSCH3 +#include +#endif +#ifdef CONFIG_FSL_ESDHC +#include +#endif +#ifdef CONFIG_MP +#include +#endif + +#ifdef CONFIG_MP +void ft_fixup_cpu(void *blob) +{ + int off; + __maybe_unused u64 spin_tbl_addr = (u64)get_spin_tbl_addr(); + fdt32_t *reg; + int addr_cells; + u64 val, core_id; + size_t *boot_code_size = &(__secondary_boot_code_size); + + off = fdt_path_offset(blob, "/cpus"); + if (off < 0) { + puts("couldn't find /cpus node\n"); + return; + } + of_bus_default_count_cells(blob, off, &addr_cells, NULL); + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + while (off != -FDT_ERR_NOTFOUND) { + reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0); + if (reg) { + core_id = of_read_number(reg, addr_cells); + if (core_id == 0 || (is_core_online(core_id))) { + val = spin_tbl_addr; + val += id_to_core(core_id) * + SPIN_TABLE_ELEM_SIZE; + val = cpu_to_fdt64(val); + fdt_setprop_string(blob, off, "enable-method", + "spin-table"); + fdt_setprop(blob, off, "cpu-release-addr", + &val, sizeof(val)); + } else { + debug("skipping offline core\n"); + } + } else { + puts("Warning: found cpu node without reg property\n"); + } + off = fdt_node_offset_by_prop_value(blob, off, "device_type", + "cpu", 4); + } + + fdt_add_mem_rsv(blob, (uintptr_t)&secondary_boot_code, + *boot_code_size); +} +#endif + +/* + * the burden is on the the caller to not request a count + * exceeding the bounds of the stream_ids[] array + */ +void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt) +{ + int i; + + if (count > max_cnt) { + printf("\n%s: ERROR: max per-device stream ID count exceed\n", + __func__); + return; + } + + for (i = 0; i < count; i++) + stream_ids[i] = start_id++; +} + +/* + * This function updates the mmu-masters property on the SMMU + * node as per the SMMU binding-- phandle and list of stream IDs + * for each MMU master. + */ +void append_mmu_masters(void *blob, const char *smmu_path, + const char *master_name, u32 *stream_ids, int count) +{ + u32 phandle; + int smmu_nodeoffset; + int master_nodeoffset; + int i; + + /* get phandle of mmu master device */ + master_nodeoffset = fdt_path_offset(blob, master_name); + if (master_nodeoffset < 0) { + printf("\n%s: ERROR: master not found\n", __func__); + return; + } + phandle = fdt_get_phandle(blob, master_nodeoffset); + if (!phandle) { /* if master has no phandle, create one */ + phandle = fdt_create_phandle(blob, master_nodeoffset); + if (!phandle) { + printf("\n%s: ERROR: unable to create phandle\n", + __func__); + return; + } + } + + /* append it to mmu-masters */ + smmu_nodeoffset = fdt_path_offset(blob, smmu_path); + if (fdt_appendprop_u32(blob, smmu_nodeoffset, "mmu-masters", + phandle) < 0) { + printf("\n%s: ERROR: unable to update SMMU node\n", __func__); + return; + } + + /* for each stream ID, append to mmu-masters */ + for (i = 0; i < count; i++) { + fdt_appendprop_u32(blob, smmu_nodeoffset, "mmu-masters", + stream_ids[i]); + } + + /* fix up #stream-id-cells with stream ID count */ + if (fdt_setprop_u32(blob, master_nodeoffset, "#stream-id-cells", + count) < 0) + printf("\n%s: ERROR: unable to update #stream-id-cells\n", + __func__); +} + + +/* + * The info below summarizes how streamID partitioning works + * for ls2085a and how it is conveyed to the OS via the device tree. + * + * -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA) + * -all legacy devices get a unique ICID assigned and programmed in + * their AMQR registers by u-boot + * -u-boot updates the hardware device tree with streamID properties + * for each platform/legacy device (smmu-masters property) + * + * -PCIe + * -for each PCI controller that is active (as per RCW settings), + * u-boot will allocate a range of ICID and convey that to Linux via + * the device tree (smmu-masters property) + * + * -DPAA2 + * -u-boot will allocate a range of ICIDs to be used by the Management + * Complex for containers and will set these values in the MC DPC image. + * -the MC is responsible for allocating and setting up ICIDs + * for all DPAA2 devices. + * + */ +#ifdef CONFIG_FSL_LSCH3 +static void fdt_fixup_smmu(void *blob) +{ + int nodeoffset; + + nodeoffset = fdt_path_offset(blob, "/iommu@5000000"); + if (nodeoffset < 0) { + printf("\n%s: WARNING: no SMMU node found\n", __func__); + return; + } + + /* fixup for all PCI controllers */ +#ifdef CONFIG_PCI + fdt_fixup_smmu_pcie(blob); +#endif +} +#endif + +void ft_cpu_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_MP + ft_fixup_cpu(blob); +#endif + +#ifdef CONFIG_SYS_NS16550 + do_fixup_by_compat_u32(blob, "fsl,ns16550", + "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); +#endif + +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif + +#ifdef CONFIG_FSL_ESDHC + fdt_fixup_esdhc(blob, bd); +#endif + +#ifdef CONFIG_FSL_LSCH3 + fdt_fixup_smmu(blob); +#endif +} diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c new file mode 100644 index 0000000..2ab8da6 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -0,0 +1,146 @@ +/* + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SYS_FSL_SRDS_1 +static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT]; +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 +static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT]; +#endif + +int is_serdes_configured(enum srds_prtcl device) +{ + int ret = 0; + +#ifdef CONFIG_SYS_FSL_SRDS_1 + ret |= serdes1_prtcl_map[device]; +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + ret |= serdes2_prtcl_map[device]; +#endif + + return !!ret; +} + +int serdes_get_first_lane(u32 sd, enum srds_prtcl device) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 cfg = gur_in32(&gur->rcwsr[28]); + int i; + + switch (sd) { +#ifdef CONFIG_SYS_FSL_SRDS_1 + case FSL_SRDS_1: + cfg &= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; + cfg >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + break; +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + case FSL_SRDS_2: + cfg &= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; + cfg >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + break; +#endif + default: + printf("invalid SerDes%d\n", sd); + break; + } + /* Is serdes enabled at all? */ + if (cfg == 0) + return -ENODEV; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_get_prtcl(sd, cfg, i) == device) + return i; + } + + return -ENODEV; +} + +void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, + u8 serdes_prtcl_map[SERDES_PRCTL_COUNT]) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 cfg; + int lane; + + memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map)); + + cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask; + cfg >>= sd_prctl_shift; + printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); + + if (!is_serdes_prtcl_valid(sd, cfg)) + printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg); + + for (lane = 0; lane < SRDS_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); + if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT)) + debug("Unknown SerDes lane protocol %d\n", lane_prtcl); + else { + serdes_prtcl_map[lane_prtcl] = 1; +#ifdef CONFIG_FSL_MC_ENET + switch (lane_prtcl) { + case QSGMII_A: + wriop_init_dpmac(sd, 5, (int)lane_prtcl); + wriop_init_dpmac(sd, 6, (int)lane_prtcl); + wriop_init_dpmac(sd, 7, (int)lane_prtcl); + wriop_init_dpmac(sd, 8, (int)lane_prtcl); + break; + case QSGMII_B: + wriop_init_dpmac(sd, 1, (int)lane_prtcl); + wriop_init_dpmac(sd, 2, (int)lane_prtcl); + wriop_init_dpmac(sd, 3, (int)lane_prtcl); + wriop_init_dpmac(sd, 4, (int)lane_prtcl); + break; + case QSGMII_C: + wriop_init_dpmac(sd, 13, (int)lane_prtcl); + wriop_init_dpmac(sd, 14, (int)lane_prtcl); + wriop_init_dpmac(sd, 15, (int)lane_prtcl); + wriop_init_dpmac(sd, 16, (int)lane_prtcl); + break; + case QSGMII_D: + wriop_init_dpmac(sd, 9, (int)lane_prtcl); + wriop_init_dpmac(sd, 10, (int)lane_prtcl); + wriop_init_dpmac(sd, 11, (int)lane_prtcl); + wriop_init_dpmac(sd, 12, (int)lane_prtcl); + break; + default: + if (lane_prtcl >= SGMII1 && + lane_prtcl <= SGMII16) + wriop_init_dpmac(sd, lane + 1, + (int)lane_prtcl); + break; + } +#endif + } + } +} + +void fsl_serdes_init(void) +{ +#ifdef CONFIG_SYS_FSL_SRDS_1 + serdes_init(FSL_SRDS_1, + CONFIG_SYS_FSL_LSCH3_SERDES_ADDR, + FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK, + FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT, + serdes1_prtcl_map); +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + serdes_init(FSL_SRDS_2, + CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000, + FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK, + FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT, + serdes2_prtcl_map); +#endif +} diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c new file mode 100644 index 0000000..4054c3c --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -0,0 +1,189 @@ +/* + * Copyright 2014-2015, Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Derived from arch/power/cpu/mpc85xx/speed.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include "cpu.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS +#define CONFIG_SYS_FSL_NUM_CC_PLLS 6 +#endif + + +void get_sys_info(struct sys_info *sys_info) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); +#ifdef CONFIG_FSL_IFC + struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; + u32 ccr; +#endif + struct ccsr_clk_cluster_group __iomem *clk_grp[2] = { + (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR), + (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR) + }; + struct ccsr_clk_ctrl __iomem *clk_ctrl = + (void *)(CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR); + unsigned int cpu; + const u8 core_cplx_pll[16] = { + [0] = 0, /* CC1 PPL / 1 */ + [1] = 0, /* CC1 PPL / 2 */ + [2] = 0, /* CC1 PPL / 4 */ + [4] = 1, /* CC2 PPL / 1 */ + [5] = 1, /* CC2 PPL / 2 */ + [6] = 1, /* CC2 PPL / 4 */ + [8] = 2, /* CC3 PPL / 1 */ + [9] = 2, /* CC3 PPL / 2 */ + [10] = 2, /* CC3 PPL / 4 */ + [12] = 3, /* CC4 PPL / 1 */ + [13] = 3, /* CC4 PPL / 2 */ + [14] = 3, /* CC4 PPL / 4 */ + }; + + const u8 core_cplx_pll_div[16] = { + [0] = 1, /* CC1 PPL / 1 */ + [1] = 2, /* CC1 PPL / 2 */ + [2] = 4, /* CC1 PPL / 4 */ + [4] = 1, /* CC2 PPL / 1 */ + [5] = 2, /* CC2 PPL / 2 */ + [6] = 4, /* CC2 PPL / 4 */ + [8] = 1, /* CC3 PPL / 1 */ + [9] = 2, /* CC3 PPL / 2 */ + [10] = 4, /* CC3 PPL / 4 */ + [12] = 1, /* CC4 PPL / 1 */ + [13] = 2, /* CC4 PPL / 2 */ + [14] = 4, /* CC4 PPL / 4 */ + }; + + uint i, cluster; + uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; + uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; + unsigned long sysclk = CONFIG_SYS_CLK_FREQ; + int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS; + u32 c_pll_sel, cplx_pll; + void *offset; + + sys_info->freq_systembus = sysclk; +#ifdef CONFIG_DDR_CLK_FREQ + sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; + sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ; +#else + sys_info->freq_ddrbus = sysclk; + sys_info->freq_ddrbus2 = sysclk; +#endif + + sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> + FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) & + FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK; + /* Platform clock is half of platform PLL */ + sys_info->freq_systembus /= 2; + sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> + FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & + FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; + sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >> + FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) & + FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK; + + for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { + /* + * fixme: prefer to combine the following into one line, but + * cannot pass compiling without warning about in_le32. + */ + offset = (void *)((size_t)clk_grp[i/3] + + offsetof(struct ccsr_clk_cluster_group, + pllngsr[i%3].gsr)); + ratio[i] = (in_le32(offset) >> 1) & 0x3f; + freq_c_pll[i] = sysclk * ratio[i]; + } + + for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { + cluster = fsl_qoriq_core_to_cluster(cpu); + c_pll_sel = (in_le32(&clk_ctrl->clkcncsr[cluster].csr) >> 27) + & 0xf; + cplx_pll = core_cplx_pll[c_pll_sel]; + cplx_pll += cc_group[cluster] - 1; + sys_info->freq_processor[cpu] = + freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; + } + +#if defined(CONFIG_FSL_IFC) + ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr); + ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; + + sys_info->freq_localbus = sys_info->freq_systembus / ccr; +#endif +} + + +int get_clocks(void) +{ + struct sys_info sys_info; + get_sys_info(&sys_info); + gd->cpu_clk = sys_info.freq_processor[0]; + gd->bus_clk = sys_info.freq_systembus; + gd->mem_clk = sys_info.freq_ddrbus; + gd->arch.mem2_clk = sys_info.freq_ddrbus2; +#if defined(CONFIG_FSL_ESDHC) + gd->arch.sdhc_clk = gd->bus_clk / 2; +#endif /* defined(CONFIG_FSL_ESDHC) */ + + if (gd->cpu_clk != 0) + return 0; + else + return 1; +} + +/******************************************** + * get_bus_freq + * return system bus freq in Hz + *********************************************/ +ulong get_bus_freq(ulong dummy) +{ + if (!gd->bus_clk) + get_clocks(); + + return gd->bus_clk; +} + +/******************************************** + * get_ddr_freq + * return ddr bus freq in Hz + *********************************************/ +ulong get_ddr_freq(ulong ctrl_num) +{ + if (!gd->mem_clk) + get_clocks(); + + /* + * DDR controller 0 & 1 are on memory complex 0 + * DDR controler 2 is on memory complext 1 + */ + if (ctrl_num >= 2) + return gd->arch.mem2_clk; + + return gd->mem_clk; +} + +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_I2C_CLK: + return get_bus_freq(0) / 2; + case MXC_DSPI_CLK: + return get_bus_freq(0) / 2; + default: + printf("Unsupported clock\n"); + } + return 0; +} diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S new file mode 100644 index 0000000..41e1704 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -0,0 +1,363 @@ +/* + * (C) Copyright 2014-2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Extracted from armv8/start.S + */ + +#include +#include +#include +#include +#ifdef CONFIG_MP +#include +#endif + +ENTRY(lowlevel_init) + mov x29, lr /* Save LR */ + +#ifdef CONFIG_FSL_LSCH3 + /* Add fully-coherent masters to DVM domain */ + ldr x0, =CCI_MN_BASE + ldr x1, =CCI_MN_RNF_NODEID_LIST + ldr x2, =CCI_MN_DVM_DOMAIN_CTL_SET + bl ccn504_add_masters_to_dvm + + /* Set all RN-I ports to QoS of 15 */ + ldr x0, =CCI_S0_QOS_CONTROL_BASE(0) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S1_QOS_CONTROL_BASE(0) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S2_QOS_CONTROL_BASE(0) + ldr x1, =0x00FF000C + bl ccn504_set_qos + + ldr x0, =CCI_S0_QOS_CONTROL_BASE(2) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S1_QOS_CONTROL_BASE(2) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S2_QOS_CONTROL_BASE(2) + ldr x1, =0x00FF000C + bl ccn504_set_qos + + ldr x0, =CCI_S0_QOS_CONTROL_BASE(6) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S1_QOS_CONTROL_BASE(6) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S2_QOS_CONTROL_BASE(6) + ldr x1, =0x00FF000C + bl ccn504_set_qos + + ldr x0, =CCI_S0_QOS_CONTROL_BASE(12) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S1_QOS_CONTROL_BASE(12) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S2_QOS_CONTROL_BASE(12) + ldr x1, =0x00FF000C + bl ccn504_set_qos + + ldr x0, =CCI_S0_QOS_CONTROL_BASE(16) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S1_QOS_CONTROL_BASE(16) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S2_QOS_CONTROL_BASE(16) + ldr x1, =0x00FF000C + bl ccn504_set_qos + + ldr x0, =CCI_S0_QOS_CONTROL_BASE(20) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S1_QOS_CONTROL_BASE(20) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S2_QOS_CONTROL_BASE(20) + ldr x1, =0x00FF000C + bl ccn504_set_qos +#endif + + /* Set the SMMU page size in the sACR register */ + ldr x1, =SMMU_BASE + ldr w0, [x1, #0x10] + orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */ + str w0, [x1, #0x10] + + /* Initialize GIC Secure Bank Status */ +#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) + branch_if_slave x0, 1f + ldr x0, =GICD_BASE + bl gic_init_secure +1: +#ifdef CONFIG_GICV3 + ldr x0, =GICR_BASE + bl gic_init_secure_percpu +#elif defined(CONFIG_GICV2) + ldr x0, =GICD_BASE + ldr x1, =GICC_BASE + bl gic_init_secure_percpu +#endif +#endif + + branch_if_master x0, x1, 2f + +#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY) + ldr x0, =secondary_boot_func + blr x0 +#endif + +2: +#ifdef CONFIG_FSL_TZPC_BP147 + /* Set Non Secure access for all devices protected via TZPC */ + ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */ + orr w0, w0, #1 << 3 /* DCFG_RESET is accessible from NS world */ + str w0, [x1] + + isb + dsb sy +#endif + +#ifdef CONFIG_FSL_TZASC_400 + /* Set TZASC so that: + * a. We use only Region0 whose global secure write/read is EN + * b. We use only Region0 whose NSAID write/read is EN + * + * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just + * placeholders. + */ + ldr x1, =TZASC_GATE_KEEPER(0) + ldr x0, [x1] /* Filter 0 Gate Keeper Register */ + orr x0, x0, #1 << 0 /* Set open_request for Filter 0 */ + str x0, [x1] + + ldr x1, =TZASC_GATE_KEEPER(1) + ldr x0, [x1] /* Filter 0 Gate Keeper Register */ + orr x0, x0, #1 << 0 /* Set open_request for Filter 0 */ + str x0, [x1] + + ldr x1, =TZASC_REGION_ATTRIBUTES_0(0) + ldr x0, [x1] /* Region-0 Attributes Register */ + orr x0, x0, #1 << 31 /* Set Sec global write en, Bit[31] */ + orr x0, x0, #1 << 30 /* Set Sec global read en, Bit[30] */ + str x0, [x1] + + ldr x1, =TZASC_REGION_ATTRIBUTES_0(1) + ldr x0, [x1] /* Region-1 Attributes Register */ + orr x0, x0, #1 << 31 /* Set Sec global write en, Bit[31] */ + orr x0, x0, #1 << 30 /* Set Sec global read en, Bit[30] */ + str x0, [x1] + + ldr x1, =TZASC_REGION_ID_ACCESS_0(0) + ldr w0, [x1] /* Region-0 Access Register */ + mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */ + str w0, [x1] + + ldr x1, =TZASC_REGION_ID_ACCESS_0(1) + ldr w0, [x1] /* Region-1 Attributes Register */ + mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */ + str w0, [x1] + + isb + dsb sy +#endif + mov lr, x29 /* Restore LR */ + ret +ENDPROC(lowlevel_init) + +hnf_pstate_poll: + /* x0 has the desired status, return 0 for success, 1 for timeout + * clobber x1, x2, x3, x4, x6, x7 + */ + mov x1, x0 + mov x7, #0 /* flag for timeout */ + mrs x3, cntpct_el0 /* read timer */ + add x3, x3, #1200 /* timeout after 100 microseconds */ + mov x0, #0x18 + movk x0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */ + mov w6, #8 /* HN-F node count */ +1: + ldr x2, [x0] + cmp x2, x1 /* check status */ + b.eq 2f + mrs x4, cntpct_el0 + cmp x4, x3 + b.ls 1b + mov x7, #1 /* timeout */ + b 3f +2: + add x0, x0, #0x10000 /* move to next node */ + subs w6, w6, #1 + cbnz w6, 1b +3: + mov x0, x7 + ret + +hnf_set_pstate: + /* x0 has the desired state, clobber x1, x2, x6 */ + mov x1, x0 + /* power state to SFONLY */ + mov w6, #8 /* HN-F node count */ + mov x0, #0x10 + movk x0, #0x420, lsl #16 /* HNF0_PSTATE_REQ */ +1: /* set pstate to sfonly */ + ldr x2, [x0] + and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */ + orr x2, x2, x1 + str x2, [x0] + add x0, x0, #0x10000 /* move to next node */ + subs w6, w6, #1 + cbnz w6, 1b + + ret + +ENTRY(__asm_flush_l3_cache) + /* + * Return status in x0 + * success 0 + * tmeout 1 for setting SFONLY, 2 for FAM, 3 for both + */ + mov x29, lr + mov x8, #0 + + dsb sy + mov x0, #0x1 /* HNFPSTAT_SFONLY */ + bl hnf_set_pstate + + mov x0, #0x4 /* SFONLY status */ + bl hnf_pstate_poll + cbz x0, 1f + mov x8, #1 /* timeout */ +1: + dsb sy + mov x0, #0x3 /* HNFPSTAT_FAM */ + bl hnf_set_pstate + + mov x0, #0xc /* FAM status */ + bl hnf_pstate_poll + cbz x0, 1f + add x8, x8, #0x2 +1: + mov x0, x8 + mov lr, x29 + ret +ENDPROC(__asm_flush_l3_cache) + +#ifdef CONFIG_MP + /* Keep literals not used by the secondary boot code outside it */ + .ltorg + + /* Using 64 bit alignment since the spin table is accessed as data */ + .align 4 + .global secondary_boot_code + /* Secondary Boot Code starts here */ +secondary_boot_code: + .global __spin_table +__spin_table: + .space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE + + .align 2 +ENTRY(secondary_boot_func) + /* + * MPIDR_EL1 Fields: + * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1) + * MPIDR[7:2] = AFF0_RES + * MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3) + * MPIDR[23:16] = AFF2_CLUSTERID + * MPIDR[24] = MT + * MPIDR[29:25] = RES0 + * MPIDR[30] = U + * MPIDR[31] = ME + * MPIDR[39:32] = AFF3 + * + * Linear Processor ID (LPID) calculation from MPIDR_EL1: + * (We only use AFF0_CPUID and AFF1_CLUSTERID for now + * until AFF2_CLUSTERID and AFF3 have non-zero values) + * + * LPID = MPIDR[15:8] | MPIDR[1:0] + */ + mrs x0, mpidr_el1 + ubfm x1, x0, #8, #15 + ubfm x2, x0, #0, #1 + orr x10, x2, x1, lsl #2 /* x10 has LPID */ + ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */ + /* + * offset of the spin table element for this core from start of spin + * table (each elem is padded to 64 bytes) + */ + lsl x1, x10, #6 + ldr x0, =__spin_table + /* physical address of this cpus spin table element */ + add x11, x1, x0 + + ldr x0, =__real_cntfrq + ldr x0, [x0] + msr cntfrq_el0, x0 /* set with real frequency */ + str x9, [x11, #16] /* LPID */ + mov x4, #1 + str x4, [x11, #8] /* STATUS */ + dsb sy +#if defined(CONFIG_GICV3) + gic_wait_for_interrupt_m x0 +#elif defined(CONFIG_GICV2) + ldr x0, =GICC_BASE + gic_wait_for_interrupt_m x0, w1 +#endif + + bl secondary_switch_to_el2 +#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 + bl secondary_switch_to_el1 +#endif + +slave_cpu: + wfe + ldr x0, [x11] + cbz x0, slave_cpu +#ifndef CONFIG_ARMV8_SWITCH_TO_EL1 + mrs x1, sctlr_el2 +#else + mrs x1, sctlr_el1 +#endif + tbz x1, #25, cpu_is_le + rev x0, x0 /* BE to LE conversion */ +cpu_is_le: + br x0 /* branch to the given address */ +ENDPROC(secondary_boot_func) + +ENTRY(secondary_switch_to_el2) + switch_el x0, 1f, 0f, 0f +0: ret +1: armv8_switch_to_el2_m x0 +ENDPROC(secondary_switch_to_el2) + +ENTRY(secondary_switch_to_el1) + switch_el x0, 0f, 1f, 0f +0: ret +1: armv8_switch_to_el1_m x0, x1 +ENDPROC(secondary_switch_to_el1) + + /* Ensure that the literals used by the secondary boot code are + * assembled within it (this is required so that we can protect + * this area with a single memreserve region + */ + .ltorg + + /* 64 bit alignment for elements accessed as data */ + .align 4 + .global __real_cntfrq +__real_cntfrq: + .quad COUNTER_FREQUENCY + .globl __secondary_boot_code_size + .type __secondary_boot_code_size, %object + /* Secondary Boot Code ends here */ +__secondary_boot_code_size: + .quad .-secondary_boot_code +#endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2085a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2085a_serdes.c new file mode 100644 index 0000000..ea3114c --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2085a_serdes.c @@ -0,0 +1,116 @@ +/* + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct serdes_config { + u8 protocol; + u8 lanes[SRDS_MAX_LANES]; +}; + +static struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {0x03, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2 } }, + {0x05, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII4, SGMII3, SGMII2, SGMII1 } }, + {0x07, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, + SGMII1 } }, + {0x09, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, + SGMII1 } }, + {0x0A, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, + SGMII1 } }, + {0x0C, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, + SGMII1 } }, + {0x0E, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, + SGMII1 } }, + {0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } }, + {0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } }, + {0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } }, + {0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } }, + {0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } }, + {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A, + QSGMII_B} }, + {0x35, {QSGMII_C, QSGMII_D, QSGMII_A, PCIE2, XFI4, XFI3, XFI2, XFI1 } }, + {} +}; +static struct serdes_config serdes2_cfg_tbl[] = { + /* SerDes 2 */ + {0x07, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, + SGMII16 } }, + {0x09, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, + SGMII16 } }, + {0x0A, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, + SGMII16 } }, + {0x0C, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, + SGMII16 } }, + {0x0E, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, + SGMII16 } }, + {0x3D, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } }, + {0x3E, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } }, + {0x3F, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } }, + {0x40, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } }, + {0x41, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } }, + {0x42, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } }, + {0x43, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } }, + {0x44, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } }, + {0x45, {PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15, + SGMII16 } }, + {0x47, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4, + PCIE4 } }, + {0x49, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, + SATA2 } }, + {0x4A, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, + SATA2 } }, + {} +}; + +static struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, + serdes2_cfg_tbl, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c new file mode 100644 index 0000000..1b13d32 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -0,0 +1,183 @@ +/* + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void *get_spin_tbl_addr(void) +{ + return &__spin_table; +} + +phys_addr_t determine_mp_bootpg(void) +{ + return (phys_addr_t)&secondary_boot_code; +} + +int fsl_layerscape_wake_seconday_cores(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR); + u32 cores, cpu_up_mask = 1; + int i, timeout = 10; + u64 *table = get_spin_tbl_addr(); + +#ifdef COUNTER_FREQUENCY_REAL + /* update for secondary cores */ + __real_cntfrq = COUNTER_FREQUENCY_REAL; + flush_dcache_range((unsigned long)&__real_cntfrq, + (unsigned long)&__real_cntfrq + 8); +#endif + + cores = cpu_mask(); + /* Clear spin table so that secondary processors + * observe the correct value after waking up from wfe. + */ + memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE); + flush_dcache_range((unsigned long)table, + (unsigned long)table + + (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE)); + + printf("Waking secondary cores to start from %lx\n", gd->relocaddr); + + gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32)); + gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr); + gur_out32(&gur->scratchrw[6], 1); + asm volatile("dsb st" : : : "memory"); + rst->brrl = cores; + asm volatile("dsb st" : : : "memory"); + + /* This is needed as a precautionary measure. + * If some code before this has accidentally released the secondary + * cores then the pre-bootloader code will trap them in a "wfe" unless + * the scratchrw[6] is set. In this case we need a sev here to get these + * cores moving again. + */ + asm volatile("sev"); + + while (timeout--) { + flush_dcache_range((unsigned long)table, (unsigned long)table + + CONFIG_MAX_CPUS * 64); + for (i = 1; i < CONFIG_MAX_CPUS; i++) { + if (table[i * WORDS_PER_SPIN_TABLE_ENTRY + + SPIN_TABLE_ELEM_STATUS_IDX]) + cpu_up_mask |= 1 << i; + } + if (hweight32(cpu_up_mask) == hweight32(cores)) + break; + udelay(10); + } + if (timeout <= 0) { + printf("Not all cores (0x%x) are up (0x%x)\n", + cores, cpu_up_mask); + return 1; + } + printf("All (%d) cores are up.\n", hweight32(cores)); + + return 0; +} + +int is_core_valid(unsigned int core) +{ + return !!((1 << core) & cpu_mask()); +} + +int is_core_online(u64 cpu_id) +{ + u64 *table; + int pos = id_to_core(cpu_id); + table = (u64 *)get_spin_tbl_addr() + pos * WORDS_PER_SPIN_TABLE_ENTRY; + return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1; +} + +int cpu_reset(int nr) +{ + puts("Feature is not implemented.\n"); + + return 0; +} + +int cpu_disable(int nr) +{ + puts("Feature is not implemented.\n"); + + return 0; +} + +int core_to_pos(int nr) +{ + u32 cores = cpu_mask(); + int i, count = 0; + + if (nr == 0) { + return 0; + } else if (nr >= hweight32(cores)) { + puts("Not a valid core number.\n"); + return -1; + } + + for (i = 1; i < 32; i++) { + if (is_core_valid(i)) { + count++; + if (count == nr) + break; + } + } + + return count; +} + +int cpu_status(int nr) +{ + u64 *table; + int pos; + + if (nr == 0) { + table = (u64 *)get_spin_tbl_addr(); + printf("table base @ 0x%p\n", table); + } else { + pos = core_to_pos(nr); + if (pos < 0) + return -1; + table = (u64 *)get_spin_tbl_addr() + pos * + WORDS_PER_SPIN_TABLE_ENTRY; + printf("table @ 0x%p\n", table); + printf(" addr - 0x%016llx\n", + table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX]); + printf(" status - 0x%016llx\n", + table[SPIN_TABLE_ELEM_STATUS_IDX]); + printf(" lpid - 0x%016llx\n", + table[SPIN_TABLE_ELEM_LPID_IDX]); + } + + return 0; +} + +int cpu_release(int nr, int argc, char * const argv[]) +{ + u64 boot_addr; + u64 *table = (u64 *)get_spin_tbl_addr(); + int pos; + + pos = core_to_pos(nr); + if (pos <= 0) + return -1; + + table += pos * WORDS_PER_SPIN_TABLE_ENTRY; + boot_addr = simple_strtoull(argv[0], NULL, 16); + table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr; + flush_dcache_range((unsigned long)table, + (unsigned long)table + SPIN_TABLE_ELEM_SIZE); + asm volatile("dsb st"); + smp_kick_all_cpus(); /* only those with entry addr set will run */ + + return 0; +} diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c new file mode 100644 index 0000000..73e48a7 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -0,0 +1,86 @@ +/* + * Copyright 2014-2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_LS2085A +static void erratum_a008751(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008751 + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; + + writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4); +#endif +} + +static void erratum_rcw_src(void) +{ +#if defined(CONFIG_SPL) + u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; + u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE; + u32 val; + + val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); + val &= ~DCFG_PORSR1_RCW_SRC; + val |= DCFG_PORSR1_RCW_SRC_NOR; + out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val); +#endif +} + +#define I2C_DEBUG_REG 0x6 +#define I2C_GLITCH_EN 0x8 +/* + * This erratum requires setting glitch_en bit to enable + * digital glitch filter to improve clock stability. + */ +static void erratum_a009203(void) +{ + u8 __iomem *ptr; +#ifdef CONFIG_SYS_I2C +#ifdef I2C1_BASE_ADDR + ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); + + writeb(I2C_GLITCH_EN, ptr); +#endif +#ifdef I2C2_BASE_ADDR + ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG); + + writeb(I2C_GLITCH_EN, ptr); +#endif +#ifdef I2C3_BASE_ADDR + ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG); + + writeb(I2C_GLITCH_EN, ptr); +#endif +#ifdef I2C4_BASE_ADDR + ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG); + + writeb(I2C_GLITCH_EN, ptr); +#endif +#endif +} + +void fsl_lsch3_early_init_f(void) +{ + erratum_a008751(); + erratum_rcw_src(); + init_early_memctl_regs(); /* tighten IFC timing */ + erratum_a009203(); +} +#endif + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + return 0; +} +#endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c new file mode 100644 index 0000000..2f30d4b --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -0,0 +1,76 @@ +/* + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +u32 spl_boot_device(void) +{ +#ifdef CONFIG_SPL_MMC_SUPPORT + return BOOT_DEVICE_MMC1; +#endif +#ifdef CONFIG_SPL_NAND_SUPPORT + return BOOT_DEVICE_NAND; +#endif + return 0; +} + +u32 spl_boot_mode(void) +{ + switch (spl_boot_device()) { + case BOOT_DEVICE_MMC1: +#ifdef CONFIG_SPL_FAT_SUPPORT + return MMCSD_MODE_FAT; +#else + return MMCSD_MODE_RAW; +#endif + case BOOT_DEVICE_NAND: + return 0; + default: + puts("spl: error: unsupported device\n"); + hang(); + } +} + +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + /* Set global data pointer */ + gd = &gdata; + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); +#ifdef CONFIG_LS2085A + arch_cpu_init(); +#endif +#ifdef CONFIG_FSL_IFC + init_early_memctl_regs(); +#endif + board_early_init_f(); + timer_init(); +#ifdef CONFIG_LS2085A + env_init(); +#endif + get_clocks(); + + preloader_console_init(); + +#ifdef CONFIG_SPL_I2C_SUPPORT + i2c_init_all(); +#endif + dram_init(); + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} +#endif diff --git a/arch/arm/cpu/armv8/fsl-lsch3/Makefile b/arch/arm/cpu/armv8/fsl-lsch3/Makefile deleted file mode 100644 index 9f7815b..0000000 --- a/arch/arm/cpu/armv8/fsl-lsch3/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright 2014, Freescale Semiconductor -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += cpu.o -obj-y += lowlevel.o -obj-y += soc.o -obj-y += speed.o -obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o ls2085a_serdes.o -obj-$(CONFIG_MP) += mp.o -obj-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README deleted file mode 100644 index 08da7e4..0000000 --- a/arch/arm/cpu/armv8/fsl-lsch3/README +++ /dev/null @@ -1,244 +0,0 @@ -# -# Copyright 2014 Freescale Semiconductor -# -# SPDX-License-Identifier: GPL-2.0+ -# - -Freescale LayerScape with Chassis Generation 3 - -This architecture supports Freescale ARMv8 SoCs with Chassis generation 3, -for example LS2085A. - -DDR Layout -============ -Entire DDR region splits into two regions. - - Region 1 is at address 0x8000_0000 to 0xffff_ffff. - - Region 2 is at 0x80_8000_0000 to the top of total memory, - for example 16GB, 0x83_ffff_ffff. - -All DDR memory is marked as cache-enabled. - -When MC and Debug server is enabled, they carve 512MB away from the high -end of DDR. For example, if the total DDR is 16GB, it shrinks to 15.5GB -with MC and Debug server enabled. Linux only sees 15.5GB. - -The reserved 512MB layout looks like - - +---------------+ <-- top/end of memory - | 256MB | debug server - +---------------+ - | 256MB | MC - +---------------+ - | ... | - -MC requires the memory to be aligned with 512MB, so even debug server is -not enabled, 512MB is reserved, not 256MB. - -Flash Layout -============ - -(1) A typical layout of various images (including Linux and other firmware images) - is shown below considering a 32MB NOR flash device present on most - pre-silicon platforms (simulator and emulator): - - ------------------------- - | FIT Image | - | (linux + DTB + RFS) | - ------------------------- ----> 0x0120_0000 - | Debug Server FW | - ------------------------- ----> 0x00C0_0000 - | AIOP FW | - ------------------------- ----> 0x0070_0000 - | MC FW | - ------------------------- ----> 0x006C_0000 - | MC DPL Blob | - ------------------------- ----> 0x0020_0000 - | BootLoader + Env| - ------------------------- ----> 0x0000_1000 - | PBI | - ------------------------- ----> 0x0000_0080 - | RCW | - ------------------------- ----> 0x0000_0000 - - 32-MB NOR flash layout for pre-silicon platforms (simulator and emulator) - -(2) A typical layout of various images (including Linux and other firmware images) - is shown below considering a 128MB NOR flash device present on QDS and RDB - boards: - ----------------------------------------- ----> 0x5_8800_0000 --- - | .. Unused .. (7M) | | - ----------------------------------------- ----> 0x5_8790_0000 | - | FIT Image (linux + DTB + RFS) (40M) | | - ----------------------------------------- ----> 0x5_8510_0000 | - | PHY firmware (2M) | | - ----------------------------------------- ----> 0x5_84F0_0000 | 64K - | Debug Server FW (2M) | | Alt - ----------------------------------------- ----> 0x5_84D0_0000 | Bank - | AIOP FW (4M) | | - ----------------------------------------- ----> 0x5_8490_0000 (vbank4) - | MC DPC Blob (1M) | | - ----------------------------------------- ----> 0x5_8480_0000 | - | MC DPL Blob (1M) | | - ----------------------------------------- ----> 0x5_8470_0000 | - | MC FW (4M) | | - ----------------------------------------- ----> 0x5_8430_0000 | - | BootLoader Environment (1M) | | - ----------------------------------------- ----> 0x5_8420_0000 | - | BootLoader (1M) | | - ----------------------------------------- ----> 0x5_8410_0000 | - | RCW and PBI (1M) | | - ----------------------------------------- ----> 0x5_8400_0000 --- - | .. Unused .. (7M) | | - ----------------------------------------- ----> 0x5_8390_0000 | - | FIT Image (linux + DTB + RFS) (40M) | | - ----------------------------------------- ----> 0x5_8110_0000 | - | PHY firmware (2M) | | - ----------------------------------------- ----> 0x5_80F0_0000 | 64K - | Debug Server FW (2M) | | Bank - ----------------------------------------- ----> 0x5_80D0_0000 | - | AIOP FW (4M) | | - ----------------------------------------- ----> 0x5_8090_0000 (vbank0) - | MC DPC Blob (1M) | | - ----------------------------------------- ----> 0x5_8080_0000 | - | MC DPL Blob (1M) | | - ----------------------------------------- ----> 0x5_8070_0000 | - | MC FW (4M) | | - ----------------------------------------- ----> 0x5_8030_0000 | - | BootLoader Environment (1M) | | - ----------------------------------------- ----> 0x5_8020_0000 | - | BootLoader (1M) | | - ----------------------------------------- ----> 0x5_8010_0000 | - | RCW and PBI (1M) | | - ----------------------------------------- ----> 0x5_8000_0000 --- - - 128-MB NOR flash layout for QDS and RDB boards - -Environment Variables -===================== -mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined - the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. - -mcmemsize: MC DRAM block size. If this variable is not defined, the value - CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. - -Booting from NAND -------------------- -Booting from NAND requires two images, RCW and u-boot-with-spl.bin. -The difference between NAND boot RCW image and NOR boot image is the PBI -command sequence. Below is one example for PBI commands for QDS which uses -NAND device with 2KB/page, block size 128KB. - -1) CCSR 4-byte write to 0x00e00404, data=0x00000000 -2) CCSR 4-byte write to 0x00e00400, data=0x1800a000 -The above two commands set bootloc register to 0x00000000_1800a000 where -the u-boot code will be running in OCRAM. - -3) Block Copy: SRC=0x0107, SRC_ADDR=0x00020000, DEST_ADDR=0x1800a000, -BLOCK_SIZE=0x00014000 -This command copies u-boot image from NAND device into OCRAM. The values need -to adjust accordingly. - -SRC should match the cfg_rcw_src, the reset config pins. It depends - on the NAND device. See reference manual for cfg_rcw_src. -SRC_ADDR is the offset of u-boot-with-spl.bin image in NAND device. In - the example above, 128KB. For easy maintenance, we put it at - the beginning of next block from RCW. -DEST_ADDR is fixed at 0x1800a000, matching bootloc set above. -BLOCK_SIZE is the size to be copied by PBI. - -RCW image should be written to the beginning of NAND device. Example of using -u-boot command - -nand write 0 - -To form the NAND image, build u-boot with NAND config, for example, -ls2085aqds_nand_defconfig. The image needed is u-boot-with-spl.bin. -The u-boot image should be written to match SRC_ADDR, in above example 0x20000. - -nand write 200000 - -With these two images in NAND device, the board can boot from NAND. - -Another example for RDB boards, - -1) CCSR 4-byte write to 0x00e00404, data=0x00000000 -2) CCSR 4-byte write to 0x00e00400, data=0x1800a000 -3) Block Copy: SRC=0x0119, SRC_ADDR=0x00080000, DEST_ADDR=0x1800a000, -BLOCK_SIZE=0x00014000 - -nand write 0 -nand write 80000 - -Notice the difference from QDS is SRC, SRC_ADDR and the offset of u-boot image -to match board NAND device with 4KB/page, block size 512KB. - -MMU Translation Tables -====================== - -(1) Early MMU Tables: - - Level 0 Level 1 Level 2 ------------------- ------------------ ------------------ -| 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 | ------------------- ------------------ ------------------ -| 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 | ------------------- | ------------------ ------------------ -| invalid | | | 0x00_8000_0000 | | 0x00_0040_0000 | ------------------- | ------------------ ------------------ - | | 0x00_c000_0000 | | 0x00_0060_0000 | - | ------------------ ------------------ - | | 0x01_0000_0000 | | 0x00_0080_0000 | - | ------------------ ------------------ - | ... ... - | ------------------ - | | 0x05_8000_0000 | --| - | ------------------ | - | | 0x05_c000_0000 | | - | ------------------ | - | ... | - | ------------------ | ------------------ - |--> | 0x80_0000_0000 | |-> | 0x00_3000_0000 | - ------------------ ------------------ - | 0x80_4000_0000 | | 0x00_3020_0000 | - ------------------ ------------------ - | 0x80_8000_0000 | | 0x00_3040_0000 | - ------------------ ------------------ - | 0x80_c000_0000 | | 0x00_3060_0000 | - ------------------ ------------------ - | 0x81_0000_0000 | | 0x00_3080_0000 | - ------------------ ------------------ - ... ... - -(2) Final MMU Tables: - - Level 0 Level 1 Level 2 ------------------- ------------------ ------------------ -| 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 | ------------------- ------------------ ------------------ -| 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 | ------------------- | ------------------ ------------------ -| invalid | | | 0x00_8000_0000 | | 0x00_0040_0000 | ------------------- | ------------------ ------------------ - | | 0x00_c000_0000 | | 0x00_0060_0000 | - | ------------------ ------------------ - | | 0x01_0000_0000 | | 0x00_0080_0000 | - | ------------------ ------------------ - | ... ... - | ------------------ - | | 0x08_0000_0000 | --| - | ------------------ | - | | 0x08_4000_0000 | | - | ------------------ | - | ... | - | ------------------ | ------------------ - |--> | 0x80_0000_0000 | |--> | 0x08_0000_0000 | - ------------------ ------------------ - | 0x80_4000_0000 | | 0x08_0020_0000 | - ------------------ ------------------ - | 0x80_8000_0000 | | 0x08_0040_0000 | - ------------------ ------------------ - | 0x80_c000_0000 | | 0x08_0060_0000 | - ------------------ ------------------ - | 0x81_0000_0000 | | 0x08_0080_0000 | - ------------------ ------------------ - ... ... diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c deleted file mode 100644 index eb1213e..0000000 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ /dev/null @@ -1,638 +0,0 @@ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_FSL_ESDHC -#include -#endif -#include "cpu.h" -#include "mp.h" -#include "speed.h" - -DECLARE_GLOBAL_DATA_PTR; - -static struct cpu_type cpu_type_list[] = { -#ifdef CONFIG_LS2085A - CPU_TYPE_ENTRY(LS2085, LS2085, 8), - CPU_TYPE_ENTRY(LS2080, LS2080, 8), - CPU_TYPE_ENTRY(LS2045, LS2045, 4), -#endif -}; - -void cpu_name(char *name) -{ - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - unsigned int i, svr, ver; - - svr = in_le32(&gur->svr); - ver = SVR_SOC_VER(svr); - - for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) - if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) { - strcpy(name, cpu_type_list[i].name); - - if (IS_E_PROCESSOR(svr)) - strcat(name, "E"); - break; - } - - if (i == ARRAY_SIZE(cpu_type_list)) - strcpy(name, "unknown"); -} - -#ifndef CONFIG_SYS_DCACHE_OFF - -#define SECTION_SHIFT_L0 39UL -#define SECTION_SHIFT_L1 30UL -#define SECTION_SHIFT_L2 21UL -#define BLOCK_SIZE_L0 0x8000000000 -#define BLOCK_SIZE_L1 0x40000000 -#define BLOCK_SIZE_L2 0x200000 - -#define NUM_OF_ENTRY 512 - -#define TCR_EL2_PS_40BIT (2 << 16) -#define LSCH3_VA_BITS (40) -#define LSCH3_TCR (TCR_TG0_4K | \ - TCR_EL2_PS_40BIT | \ - TCR_SHARED_NON | \ - TCR_ORGN_NC | \ - TCR_IRGN_NC | \ - TCR_T0SZ(LSCH3_VA_BITS)) -#define LSCH3_TCR_FINAL (TCR_TG0_4K | \ - TCR_EL2_PS_40BIT | \ - TCR_SHARED_OUTER | \ - TCR_ORGN_WBWA | \ - TCR_IRGN_WBWA | \ - TCR_T0SZ(LSCH3_VA_BITS)) - -#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000 -#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 -#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000 -#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000 -#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000 -#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000 -#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000 -#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 -#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 -#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000 -#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000 -#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000 -#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000 -#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000 -#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000 -#define CONFIG_SYS_FSL_MC_BASE 0x80c000000 -#define CONFIG_SYS_FSL_MC_SIZE 0x4000000 -#define CONFIG_SYS_FSL_NI_BASE 0x810000000 -#define CONFIG_SYS_FSL_NI_SIZE 0x8000000 -#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000 -#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000 -#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000 -#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000 -#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000 -#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000 -#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 -#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 -#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 -#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000 -#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 - -struct sys_mmu_table { - u64 virt_addr; - u64 phys_addr; - u64 size; - u64 memory_type; - u64 share; -}; - -static const struct sys_mmu_table lsch3_early_mmu_table[] = { - { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, - CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, - /* For IFC Region #1, only the first 4MB is cache-enabled */ - { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, - CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, - CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, - CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, - MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, - CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, - { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, -}; - -static const struct sys_mmu_table lsch3_final_mmu_table[] = { - { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, - CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, - { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, - CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, - CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, - CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, - CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - /* For QBMAN portal, only the first 64MB is cache-enabled */ - { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, - CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, - CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, - CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, - MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, -#ifdef CONFIG_LS2085A - { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, - CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, -#endif - { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, - CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, - CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, - CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, -}; - -struct table_info { - u64 *ptr; - u64 table_base; - u64 entry_size; -}; - -/* - * Set the block entries according to the information of the table. - */ -static int set_block_entry(const struct sys_mmu_table *list, - struct table_info *table) -{ - u64 block_size = 0, block_shift = 0; - u64 block_addr, index; - int j; - - if (table->entry_size == BLOCK_SIZE_L1) { - block_size = BLOCK_SIZE_L1; - block_shift = SECTION_SHIFT_L1; - } else if (table->entry_size == BLOCK_SIZE_L2) { - block_size = BLOCK_SIZE_L2; - block_shift = SECTION_SHIFT_L2; - } else { - return -EINVAL; - } - - block_addr = list->phys_addr; - index = (list->virt_addr - table->table_base) >> block_shift; - - for (j = 0; j < (list->size >> block_shift); j++) { - set_pgtable_section(table->ptr, - index, - block_addr, - list->memory_type, - list->share); - block_addr += block_size; - index++; - } - - return 0; -} - -/* - * Find the corresponding table entry for the list. - */ -static int find_table(const struct sys_mmu_table *list, - struct table_info *table, u64 *level0_table) -{ - u64 index = 0, level = 0; - u64 *level_table = level0_table; - u64 temp_base = 0, block_size = 0, block_shift = 0; - - while (level < 3) { - if (level == 0) { - block_size = BLOCK_SIZE_L0; - block_shift = SECTION_SHIFT_L0; - } else if (level == 1) { - block_size = BLOCK_SIZE_L1; - block_shift = SECTION_SHIFT_L1; - } else if (level == 2) { - block_size = BLOCK_SIZE_L2; - block_shift = SECTION_SHIFT_L2; - } - - index = 0; - while (list->virt_addr >= temp_base) { - index++; - temp_base += block_size; - } - - temp_base -= block_size; - - if ((level_table[index - 1] & PMD_TYPE_MASK) == - PMD_TYPE_TABLE) { - level_table = (u64 *)(level_table[index - 1] & - ~PMD_TYPE_MASK); - level++; - continue; - } else { - if (level == 0) - return -EINVAL; - - if ((list->phys_addr + list->size) > - (temp_base + block_size * NUM_OF_ENTRY)) - return -EINVAL; - - /* - * Check the address and size of the list member is - * aligned with the block size. - */ - if (((list->phys_addr & (block_size - 1)) != 0) || - ((list->size & (block_size - 1)) != 0)) - return -EINVAL; - - table->ptr = level_table; - table->table_base = temp_base - - ((index - 1) << block_shift); - table->entry_size = block_size; - - return 0; - } - } - return -EINVAL; -} - -/* - * To start MMU before DDR is available, we create MMU table in SRAM. - * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three - * levels of translation tables here to cover 40-bit address space. - * We use 4KB granule size, with 40 bits physical address, T0SZ=24 - * Level 0 IA[39], table address @0 - * Level 1 IA[38:30], table address @0x1000, 0x2000 - * Level 2 IA[29:21], table address @0x3000, 0x4000 - * Address above 0x5000 is free for other purpose. - */ -static inline void early_mmu_setup(void) -{ - unsigned int el, i; - u64 *level0_table = (u64 *)CONFIG_SYS_FSL_OCRAM_BASE; - u64 *level1_table0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x1000); - u64 *level1_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000); - u64 *level2_table0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000); - u64 *level2_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x4000); - struct table_info table = {level0_table, 0, BLOCK_SIZE_L0}; - - /* Invalidate all table entries */ - memset(level0_table, 0, 0x5000); - - /* Fill in the table entries */ - set_pgtable_table(level0_table, 0, level1_table0); - set_pgtable_table(level0_table, 1, level1_table1); - set_pgtable_table(level1_table0, 0, level2_table0); - set_pgtable_table(level1_table0, - CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1, - level2_table1); - - /* Find the table and fill in the block entries */ - for (i = 0; i < ARRAY_SIZE(lsch3_early_mmu_table); i++) { - if (find_table(&lsch3_early_mmu_table[i], - &table, level0_table) == 0) { - /* - * If find_table() returns error, it cannot be dealt - * with here. Breakpoint can be added for debugging. - */ - set_block_entry(&lsch3_early_mmu_table[i], &table); - /* - * If set_block_entry() returns error, it cannot be - * dealt with here too. - */ - } - } - - el = current_el(); - set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR, MEMORY_ATTRIBUTES); - set_sctlr(get_sctlr() | CR_M); -} - -/* - * The final tables look similar to early tables, but different in detail. - * These tables are in DRAM. Sub tables are added to enable cache for - * QBMan and OCRAM. - * - * Level 1 table 0 contains 512 entries for each 1GB from 0 to 512GB. - * Level 1 table 1 contains 512 entries for each 1GB from 512GB to 1TB. - * Level 2 table 0 contains 512 entries for each 2MB from 0 to 1GB. - * Level 2 table 1 contains 512 entries for each 2MB from 32GB to 33GB. - */ -static inline void final_mmu_setup(void) -{ - unsigned int el, i; - u64 *level0_table = (u64 *)gd->arch.tlb_addr; - u64 *level1_table0 = (u64 *)(gd->arch.tlb_addr + 0x1000); - u64 *level1_table1 = (u64 *)(gd->arch.tlb_addr + 0x2000); - u64 *level2_table0 = (u64 *)(gd->arch.tlb_addr + 0x3000); - u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000); - struct table_info table = {level0_table, 0, BLOCK_SIZE_L0}; - - /* Invalidate all table entries */ - memset(level0_table, 0, PGTABLE_SIZE); - - /* Fill in the table entries */ - set_pgtable_table(level0_table, 0, level1_table0); - set_pgtable_table(level0_table, 1, level1_table1); - set_pgtable_table(level1_table0, 0, level2_table0); - set_pgtable_table(level1_table0, - CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1, - level2_table1); - - /* Find the table and fill in the block entries */ - for (i = 0; i < ARRAY_SIZE(lsch3_final_mmu_table); i++) { - if (find_table(&lsch3_final_mmu_table[i], - &table, level0_table) == 0) { - if (set_block_entry(&lsch3_final_mmu_table[i], - &table) != 0) { - printf("MMU error: could not set block entry for %p\n", - &lsch3_final_mmu_table[i]); - } - - } else { - printf("MMU error: could not find the table for %p\n", - &lsch3_final_mmu_table[i]); - } - } - - /* flush new MMU table */ - flush_dcache_range(gd->arch.tlb_addr, - gd->arch.tlb_addr + gd->arch.tlb_size); - - /* point TTBR to the new table */ - el = current_el(); - set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR_FINAL, - MEMORY_ATTRIBUTES); - /* - * MMU is already enabled, just need to invalidate TLB to load the - * new table. The new table is compatible with the current table, if - * MMU somehow walks through the new table before invalidation TLB, - * it still works. So we don't need to turn off MMU here. - */ -} - -int arch_cpu_init(void) -{ - icache_enable(); - __asm_invalidate_dcache_all(); - __asm_invalidate_tlb_all(); - early_mmu_setup(); - set_sctlr(get_sctlr() | CR_C); - return 0; -} - -/* - * This function is called from lib/board.c. - * It recreates MMU table in main memory. MMU and d-cache are enabled earlier. - * There is no need to disable d-cache for this operation. - */ -void enable_caches(void) -{ - final_mmu_setup(); - __asm_invalidate_tlb_all(); -} -#endif - -static inline u32 initiator_type(u32 cluster, int init_id) -{ - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; - u32 type = in_le32(&gur->tp_ityp[idx]); - - if (type & TP_ITYP_AV) - return type; - - return 0; -} - -u32 cpu_mask(void) -{ - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - int i = 0, count = 0; - u32 cluster, type, mask = 0; - - do { - int j; - cluster = in_le32(&gur->tp_cluster[i].lower); - for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { - type = initiator_type(cluster, j); - if (type) { - if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM) - mask |= 1 << count; - count++; - } - } - i++; - } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); - - return mask; -} - -/* - * Return the number of cores on this SOC. - */ -int cpu_numcores(void) -{ - return hweight32(cpu_mask()); -} - -int fsl_qoriq_core_to_cluster(unsigned int core) -{ - struct ccsr_gur __iomem *gur = - (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); - int i = 0, count = 0; - u32 cluster; - - do { - int j; - cluster = in_le32(&gur->tp_cluster[i].lower); - for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { - if (initiator_type(cluster, j)) { - if (count == core) - return i; - count++; - } - } - i++; - } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); - - return -1; /* cannot identify the cluster */ -} - -u32 fsl_qoriq_core_to_type(unsigned int core) -{ - struct ccsr_gur __iomem *gur = - (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); - int i = 0, count = 0; - u32 cluster, type; - - do { - int j; - cluster = in_le32(&gur->tp_cluster[i].lower); - for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { - type = initiator_type(cluster, j); - if (type) { - if (count == core) - return type; - count++; - } - } - i++; - } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); - - return -1; /* cannot identify the cluster */ -} - -#ifdef CONFIG_DISPLAY_CPUINFO -int print_cpuinfo(void) -{ - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - struct sys_info sysinfo; - char buf[32]; - unsigned int i, core; - u32 type; - - puts("SoC: "); - - cpu_name(buf); - printf(" %s (0x%x)\n", buf, in_le32(&gur->svr)); - - memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); - - get_sys_info(&sysinfo); - puts("Clock Configuration:"); - for_each_cpu(i, core, cpu_numcores(), cpu_mask()) { - if (!(i % 3)) - puts("\n "); - type = TP_ITYP_VER(fsl_qoriq_core_to_type(core)); - printf("CPU%d(%s):%-4s MHz ", core, - type == TY_ITYP_VER_A7 ? "A7 " : - (type == TY_ITYP_VER_A53 ? "A53" : - (type == TY_ITYP_VER_A57 ? "A57" : " ")), - strmhz(buf, sysinfo.freq_processor[core])); - } - printf("\n Bus: %-4s MHz ", - strmhz(buf, sysinfo.freq_systembus)); - printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus)); - printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2)); - puts("\n"); - - /* Display the RCW, so that no one gets confused as to what RCW - * we're actually using for this boot. - */ - puts("Reset Configuration Word (RCW):"); - for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { - u32 rcw = in_le32(&gur->rcwsr[i]); - - if ((i % 4) == 0) - printf("\n %02x:", i * 4); - printf(" %08x", rcw); - } - puts("\n"); - - return 0; -} -#endif - -#ifdef CONFIG_FSL_ESDHC -int cpu_mmc_init(bd_t *bis) -{ - return fsl_esdhc_mmc_init(bis); -} -#endif - -int cpu_eth_init(bd_t *bis) -{ - int error = 0; - -#ifdef CONFIG_FSL_MC_ENET - error = fsl_mc_ldpaa_init(bis); -#endif - return error; -} - -int arch_early_init_r(void) -{ - int rv; - rv = fsl_lsch3_wake_seconday_cores(); - - if (rv) - printf("Did not wake secondary cores\n"); - -#ifdef CONFIG_SYS_HAS_SERDES - fsl_serdes_init(); -#endif - return 0; -} - -int timer_init(void) -{ - u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR; - u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; -#ifdef COUNTER_FREQUENCY_REAL - unsigned long cntfrq = COUNTER_FREQUENCY_REAL; - - /* Update with accurate clock frequency */ - asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory"); -#endif - - /* Enable timebase for all clusters. - * It is safe to do so even some clusters are not enabled. - */ - out_le32(cltbenr, 0xf); - - /* Enable clock for timer - * This is a global setting. - */ - out_le32(cntcr, 0x1); - - return 0; -} - -void reset_cpu(ulong addr) -{ - u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR; - u32 val; - - /* Raise RESET_REQ_B */ - val = in_le32(rstcr); - val |= 0x02; - out_le32(rstcr, val); -} diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.h b/arch/arm/cpu/armv8/fsl-lsch3/cpu.h deleted file mode 100644 index 2e3312b..0000000 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.h +++ /dev/null @@ -1,8 +0,0 @@ -/* - * Copyright 2014, Freescale Semiconductor - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -int fsl_qoriq_core_to_cluster(unsigned int core); -u32 cpu_mask(void); diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c deleted file mode 100644 index 922e8a0..0000000 --- a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#ifdef CONFIG_FSL_ESDHC -#include -#endif -#include "mp.h" - -#ifdef CONFIG_MP -void ft_fixup_cpu(void *blob) -{ - int off; - __maybe_unused u64 spin_tbl_addr = (u64)get_spin_tbl_addr(); - fdt32_t *reg; - int addr_cells; - u64 val, core_id; - size_t *boot_code_size = &(__secondary_boot_code_size); - - off = fdt_path_offset(blob, "/cpus"); - if (off < 0) { - puts("couldn't find /cpus node\n"); - return; - } - of_bus_default_count_cells(blob, off, &addr_cells, NULL); - - off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); - while (off != -FDT_ERR_NOTFOUND) { - reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0); - if (reg) { - core_id = of_read_number(reg, addr_cells); - if (core_id == 0 || (is_core_online(core_id))) { - val = spin_tbl_addr; - val += id_to_core(core_id) * - SPIN_TABLE_ELEM_SIZE; - val = cpu_to_fdt64(val); - fdt_setprop_string(blob, off, "enable-method", - "spin-table"); - fdt_setprop(blob, off, "cpu-release-addr", - &val, sizeof(val)); - } else { - debug("skipping offline core\n"); - } - } else { - puts("Warning: found cpu node without reg property\n"); - } - off = fdt_node_offset_by_prop_value(blob, off, "device_type", - "cpu", 4); - } - - fdt_add_mem_rsv(blob, (uintptr_t)&secondary_boot_code, - *boot_code_size); -} -#endif - -/* - * the burden is on the the caller to not request a count - * exceeding the bounds of the stream_ids[] array - */ -void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt) -{ - int i; - - if (count > max_cnt) { - printf("\n%s: ERROR: max per-device stream ID count exceed\n", - __func__); - return; - } - - for (i = 0; i < count; i++) - stream_ids[i] = start_id++; -} - -/* - * This function updates the mmu-masters property on the SMMU - * node as per the SMMU binding-- phandle and list of stream IDs - * for each MMU master. - */ -void append_mmu_masters(void *blob, const char *smmu_path, - const char *master_name, u32 *stream_ids, int count) -{ - u32 phandle; - int smmu_nodeoffset; - int master_nodeoffset; - int i; - - /* get phandle of mmu master device */ - master_nodeoffset = fdt_path_offset(blob, master_name); - if (master_nodeoffset < 0) { - printf("\n%s: ERROR: master not found\n", __func__); - return; - } - phandle = fdt_get_phandle(blob, master_nodeoffset); - if (!phandle) { /* if master has no phandle, create one */ - phandle = fdt_create_phandle(blob, master_nodeoffset); - if (!phandle) { - printf("\n%s: ERROR: unable to create phandle\n", - __func__); - return; - } - } - - /* append it to mmu-masters */ - smmu_nodeoffset = fdt_path_offset(blob, smmu_path); - if (fdt_appendprop_u32(blob, smmu_nodeoffset, "mmu-masters", - phandle) < 0) { - printf("\n%s: ERROR: unable to update SMMU node\n", __func__); - return; - } - - /* for each stream ID, append to mmu-masters */ - for (i = 0; i < count; i++) { - fdt_appendprop_u32(blob, smmu_nodeoffset, "mmu-masters", - stream_ids[i]); - } - - /* fix up #stream-id-cells with stream ID count */ - if (fdt_setprop_u32(blob, master_nodeoffset, "#stream-id-cells", - count) < 0) - printf("\n%s: ERROR: unable to update #stream-id-cells\n", - __func__); -} - - -/* - * The info below summarizes how streamID partitioning works - * for ls2085a and how it is conveyed to the OS via the device tree. - * - * -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA) - * -all legacy devices get a unique ICID assigned and programmed in - * their AMQR registers by u-boot - * -u-boot updates the hardware device tree with streamID properties - * for each platform/legacy device (smmu-masters property) - * - * -PCIe - * -for each PCI controller that is active (as per RCW settings), - * u-boot will allocate a range of ICID and convey that to Linux via - * the device tree (smmu-masters property) - * - * -DPAA2 - * -u-boot will allocate a range of ICIDs to be used by the Management - * Complex for containers and will set these values in the MC DPC image. - * -the MC is responsible for allocating and setting up ICIDs - * for all DPAA2 devices. - * - */ -static void fdt_fixup_smmu(void *blob) -{ - int nodeoffset; - - nodeoffset = fdt_path_offset(blob, "/iommu@5000000"); - if (nodeoffset < 0) { - printf("\n%s: WARNING: no SMMU node found\n", __func__); - return; - } - - /* fixup for all PCI controllers */ -#ifdef CONFIG_PCI - fdt_fixup_smmu_pcie(blob); -#endif -} - -void ft_cpu_setup(void *blob, bd_t *bd) -{ -#ifdef CONFIG_MP - ft_fixup_cpu(blob); -#endif - -#ifdef CONFIG_SYS_NS16550 - do_fixup_by_compat_u32(blob, "fsl,ns16550", - "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); -#endif - -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - -#if defined(CONFIG_FSL_ESDHC) - fdt_fixup_esdhc(blob, bd); -#endif - - fdt_fixup_smmu(blob); -} diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c deleted file mode 100644 index ae08343..0000000 --- a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_SYS_FSL_SRDS_1 -static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT]; -#endif -#ifdef CONFIG_SYS_FSL_SRDS_2 -static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT]; -#endif - -int is_serdes_configured(enum srds_prtcl device) -{ - int ret = 0; - -#ifdef CONFIG_SYS_FSL_SRDS_1 - ret |= serdes1_prtcl_map[device]; -#endif -#ifdef CONFIG_SYS_FSL_SRDS_2 - ret |= serdes2_prtcl_map[device]; -#endif - - return !!ret; -} - -int serdes_get_first_lane(u32 sd, enum srds_prtcl device) -{ - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - u32 cfg = in_le32(&gur->rcwsr[28]); - int i; - - switch (sd) { -#ifdef CONFIG_SYS_FSL_SRDS_1 - case FSL_SRDS_1: - cfg &= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; - cfg >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; - break; -#endif -#ifdef CONFIG_SYS_FSL_SRDS_2 - case FSL_SRDS_2: - cfg &= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; - cfg >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; - break; -#endif - default: - printf("invalid SerDes%d\n", sd); - break; - } - /* Is serdes enabled at all? */ - if (cfg == 0) - return -ENODEV; - - for (i = 0; i < SRDS_MAX_LANES; i++) { - if (serdes_get_prtcl(sd, cfg, i) == device) - return i; - } - - return -ENODEV; -} - -void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, - u8 serdes_prtcl_map[SERDES_PRCTL_COUNT]) -{ - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - u32 cfg; - int lane; - - memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map)); - - cfg = in_le32(&gur->rcwsr[28]) & sd_prctl_mask; - cfg >>= sd_prctl_shift; - printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); - - if (!is_serdes_prtcl_valid(sd, cfg)) - printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg); - - for (lane = 0; lane < SRDS_MAX_LANES; lane++) { - enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); - if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT)) - debug("Unknown SerDes lane protocol %d\n", lane_prtcl); - else { - serdes_prtcl_map[lane_prtcl] = 1; -#ifdef CONFIG_FSL_MC_ENET - switch (lane_prtcl) { - case QSGMII_A: - wriop_init_dpmac(sd, 5, (int)lane_prtcl); - wriop_init_dpmac(sd, 6, (int)lane_prtcl); - wriop_init_dpmac(sd, 7, (int)lane_prtcl); - wriop_init_dpmac(sd, 8, (int)lane_prtcl); - break; - case QSGMII_B: - wriop_init_dpmac(sd, 1, (int)lane_prtcl); - wriop_init_dpmac(sd, 2, (int)lane_prtcl); - wriop_init_dpmac(sd, 3, (int)lane_prtcl); - wriop_init_dpmac(sd, 4, (int)lane_prtcl); - break; - case QSGMII_C: - wriop_init_dpmac(sd, 13, (int)lane_prtcl); - wriop_init_dpmac(sd, 14, (int)lane_prtcl); - wriop_init_dpmac(sd, 15, (int)lane_prtcl); - wriop_init_dpmac(sd, 16, (int)lane_prtcl); - break; - case QSGMII_D: - wriop_init_dpmac(sd, 9, (int)lane_prtcl); - wriop_init_dpmac(sd, 10, (int)lane_prtcl); - wriop_init_dpmac(sd, 11, (int)lane_prtcl); - wriop_init_dpmac(sd, 12, (int)lane_prtcl); - break; - default: - if (lane_prtcl >= SGMII1 && - lane_prtcl <= SGMII16) - wriop_init_dpmac(sd, lane + 1, - (int)lane_prtcl); - break; - } -#endif - } - } -} - -void fsl_serdes_init(void) -{ -#ifdef CONFIG_SYS_FSL_SRDS_1 - serdes_init(FSL_SRDS_1, - CONFIG_SYS_FSL_LSCH3_SERDES_ADDR, - FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK, - FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT, - serdes1_prtcl_map); -#endif -#ifdef CONFIG_SYS_FSL_SRDS_2 - serdes_init(FSL_SRDS_2, - CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000, - FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK, - FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT, - serdes2_prtcl_map); -#endif -} diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S deleted file mode 100644 index 6b19d36..0000000 --- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S +++ /dev/null @@ -1,355 +0,0 @@ -/* - * (C) Copyright 2014 Freescale Semiconductor - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Extracted from armv8/start.S - */ - -#include -#include -#include -#include -#include "mp.h" - -ENTRY(lowlevel_init) - mov x29, lr /* Save LR */ - - /* Add fully-coherent masters to DVM domain */ - ldr x0, =CCI_MN_BASE - ldr x1, =CCI_MN_RNF_NODEID_LIST - ldr x2, =CCI_MN_DVM_DOMAIN_CTL_SET - bl ccn504_add_masters_to_dvm - - /* Set all RN-I ports to QoS of 15 */ - ldr x0, =CCI_S0_QOS_CONTROL_BASE(0) - ldr x1, =0x00FF000C - bl ccn504_set_qos - ldr x0, =CCI_S1_QOS_CONTROL_BASE(0) - ldr x1, =0x00FF000C - bl ccn504_set_qos - ldr x0, =CCI_S2_QOS_CONTROL_BASE(0) - ldr x1, =0x00FF000C - bl ccn504_set_qos - - ldr x0, =CCI_S0_QOS_CONTROL_BASE(2) - ldr x1, =0x00FF000C - bl ccn504_set_qos - ldr x0, =CCI_S1_QOS_CONTROL_BASE(2) - ldr x1, =0x00FF000C - bl ccn504_set_qos - ldr x0, =CCI_S2_QOS_CONTROL_BASE(2) - ldr x1, =0x00FF000C - bl ccn504_set_qos - - ldr x0, =CCI_S0_QOS_CONTROL_BASE(6) - ldr x1, =0x00FF000C - bl ccn504_set_qos - ldr x0, =CCI_S1_QOS_CONTROL_BASE(6) - ldr x1, =0x00FF000C - bl ccn504_set_qos - ldr x0, =CCI_S2_QOS_CONTROL_BASE(6) - ldr x1, =0x00FF000C - bl ccn504_set_qos - - ldr x0, =CCI_S0_QOS_CONTROL_BASE(12) - ldr x1, =0x00FF000C - bl ccn504_set_qos - ldr x0, =CCI_S1_QOS_CONTROL_BASE(12) - ldr x1, =0x00FF000C - bl ccn504_set_qos - ldr x0, =CCI_S2_QOS_CONTROL_BASE(12) - ldr x1, =0x00FF000C - bl ccn504_set_qos - - ldr x0, =CCI_S0_QOS_CONTROL_BASE(16) - ldr x1, =0x00FF000C - bl ccn504_set_qos - ldr x0, =CCI_S1_QOS_CONTROL_BASE(16) - ldr x1, =0x00FF000C - bl ccn504_set_qos - ldr x0, =CCI_S2_QOS_CONTROL_BASE(16) - ldr x1, =0x00FF000C - bl ccn504_set_qos - - ldr x0, =CCI_S0_QOS_CONTROL_BASE(20) - ldr x1, =0x00FF000C - bl ccn504_set_qos - ldr x0, =CCI_S1_QOS_CONTROL_BASE(20) - ldr x1, =0x00FF000C - bl ccn504_set_qos - ldr x0, =CCI_S2_QOS_CONTROL_BASE(20) - ldr x1, =0x00FF000C - bl ccn504_set_qos - - /* Set the SMMU page size in the sACR register */ - ldr x1, =SMMU_BASE - ldr w0, [x1, #0x10] - orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */ - str w0, [x1, #0x10] - - /* Initialize GIC Secure Bank Status */ -#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) - branch_if_slave x0, 1f - ldr x0, =GICD_BASE - bl gic_init_secure -1: -#ifdef CONFIG_GICV3 - ldr x0, =GICR_BASE - bl gic_init_secure_percpu -#elif defined(CONFIG_GICV2) - ldr x0, =GICD_BASE - ldr x1, =GICC_BASE - bl gic_init_secure_percpu -#endif -#endif - - branch_if_master x0, x1, 2f - - ldr x0, =secondary_boot_func - blr x0 -2: - -#ifdef CONFIG_FSL_TZPC_BP147 - /* Set Non Secure access for all devices protected via TZPC */ - ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */ - orr w0, w0, #1 << 3 /* DCFG_RESET is accessible from NS world */ - str w0, [x1] - - isb - dsb sy -#endif - -#ifdef CONFIG_FSL_TZASC_400 - /* Set TZASC so that: - * a. We use only Region0 whose global secure write/read is EN - * b. We use only Region0 whose NSAID write/read is EN - * - * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just - * placeholders. - */ - ldr x1, =TZASC_GATE_KEEPER(0) - ldr x0, [x1] /* Filter 0 Gate Keeper Register */ - orr x0, x0, #1 << 0 /* Set open_request for Filter 0 */ - str x0, [x1] - - ldr x1, =TZASC_GATE_KEEPER(1) - ldr x0, [x1] /* Filter 0 Gate Keeper Register */ - orr x0, x0, #1 << 0 /* Set open_request for Filter 0 */ - str x0, [x1] - - ldr x1, =TZASC_REGION_ATTRIBUTES_0(0) - ldr x0, [x1] /* Region-0 Attributes Register */ - orr x0, x0, #1 << 31 /* Set Sec global write en, Bit[31] */ - orr x0, x0, #1 << 30 /* Set Sec global read en, Bit[30] */ - str x0, [x1] - - ldr x1, =TZASC_REGION_ATTRIBUTES_0(1) - ldr x0, [x1] /* Region-1 Attributes Register */ - orr x0, x0, #1 << 31 /* Set Sec global write en, Bit[31] */ - orr x0, x0, #1 << 30 /* Set Sec global read en, Bit[30] */ - str x0, [x1] - - ldr x1, =TZASC_REGION_ID_ACCESS_0(0) - ldr w0, [x1] /* Region-0 Access Register */ - mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */ - str w0, [x1] - - ldr x1, =TZASC_REGION_ID_ACCESS_0(1) - ldr w0, [x1] /* Region-1 Attributes Register */ - mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */ - str w0, [x1] - - isb - dsb sy -#endif - mov lr, x29 /* Restore LR */ - ret -ENDPROC(lowlevel_init) - -hnf_pstate_poll: - /* x0 has the desired status, return 0 for success, 1 for timeout - * clobber x1, x2, x3, x4, x6, x7 - */ - mov x1, x0 - mov x7, #0 /* flag for timeout */ - mrs x3, cntpct_el0 /* read timer */ - add x3, x3, #1200 /* timeout after 100 microseconds */ - mov x0, #0x18 - movk x0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */ - mov w6, #8 /* HN-F node count */ -1: - ldr x2, [x0] - cmp x2, x1 /* check status */ - b.eq 2f - mrs x4, cntpct_el0 - cmp x4, x3 - b.ls 1b - mov x7, #1 /* timeout */ - b 3f -2: - add x0, x0, #0x10000 /* move to next node */ - subs w6, w6, #1 - cbnz w6, 1b -3: - mov x0, x7 - ret - -hnf_set_pstate: - /* x0 has the desired state, clobber x1, x2, x6 */ - mov x1, x0 - /* power state to SFONLY */ - mov w6, #8 /* HN-F node count */ - mov x0, #0x10 - movk x0, #0x420, lsl #16 /* HNF0_PSTATE_REQ */ -1: /* set pstate to sfonly */ - ldr x2, [x0] - and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */ - orr x2, x2, x1 - str x2, [x0] - add x0, x0, #0x10000 /* move to next node */ - subs w6, w6, #1 - cbnz w6, 1b - - ret - -ENTRY(__asm_flush_l3_cache) - /* - * Return status in x0 - * success 0 - * tmeout 1 for setting SFONLY, 2 for FAM, 3 for both - */ - mov x29, lr - mov x8, #0 - - dsb sy - mov x0, #0x1 /* HNFPSTAT_SFONLY */ - bl hnf_set_pstate - - mov x0, #0x4 /* SFONLY status */ - bl hnf_pstate_poll - cbz x0, 1f - mov x8, #1 /* timeout */ -1: - dsb sy - mov x0, #0x3 /* HNFPSTAT_FAM */ - bl hnf_set_pstate - - mov x0, #0xc /* FAM status */ - bl hnf_pstate_poll - cbz x0, 1f - add x8, x8, #0x2 -1: - mov x0, x8 - mov lr, x29 - ret -ENDPROC(__asm_flush_l3_cache) - - /* Keep literals not used by the secondary boot code outside it */ - .ltorg - - /* Using 64 bit alignment since the spin table is accessed as data */ - .align 4 - .global secondary_boot_code - /* Secondary Boot Code starts here */ -secondary_boot_code: - .global __spin_table -__spin_table: - .space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE - - .align 2 -ENTRY(secondary_boot_func) - /* - * MPIDR_EL1 Fields: - * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1) - * MPIDR[7:2] = AFF0_RES - * MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3) - * MPIDR[23:16] = AFF2_CLUSTERID - * MPIDR[24] = MT - * MPIDR[29:25] = RES0 - * MPIDR[30] = U - * MPIDR[31] = ME - * MPIDR[39:32] = AFF3 - * - * Linear Processor ID (LPID) calculation from MPIDR_EL1: - * (We only use AFF0_CPUID and AFF1_CLUSTERID for now - * until AFF2_CLUSTERID and AFF3 have non-zero values) - * - * LPID = MPIDR[15:8] | MPIDR[1:0] - */ - mrs x0, mpidr_el1 - ubfm x1, x0, #8, #15 - ubfm x2, x0, #0, #1 - orr x10, x2, x1, lsl #2 /* x10 has LPID */ - ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */ - /* - * offset of the spin table element for this core from start of spin - * table (each elem is padded to 64 bytes) - */ - lsl x1, x10, #6 - ldr x0, =__spin_table - /* physical address of this cpus spin table element */ - add x11, x1, x0 - - ldr x0, =__real_cntfrq - ldr x0, [x0] - msr cntfrq_el0, x0 /* set with real frequency */ - str x9, [x11, #16] /* LPID */ - mov x4, #1 - str x4, [x11, #8] /* STATUS */ - dsb sy -#if defined(CONFIG_GICV3) - gic_wait_for_interrupt_m x0 -#elif defined(CONFIG_GICV2) - ldr x0, =GICC_BASE - gic_wait_for_interrupt_m x0, w1 -#endif - - bl secondary_switch_to_el2 -#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 - bl secondary_switch_to_el1 -#endif - -slave_cpu: - wfe - ldr x0, [x11] - cbz x0, slave_cpu -#ifndef CONFIG_ARMV8_SWITCH_TO_EL1 - mrs x1, sctlr_el2 -#else - mrs x1, sctlr_el1 -#endif - tbz x1, #25, cpu_is_le - rev x0, x0 /* BE to LE conversion */ -cpu_is_le: - br x0 /* branch to the given address */ -ENDPROC(secondary_boot_func) - -ENTRY(secondary_switch_to_el2) - switch_el x0, 1f, 0f, 0f -0: ret -1: armv8_switch_to_el2_m x0 -ENDPROC(secondary_switch_to_el2) - -ENTRY(secondary_switch_to_el1) - switch_el x0, 0f, 1f, 0f -0: ret -1: armv8_switch_to_el1_m x0, x1 -ENDPROC(secondary_switch_to_el1) - - /* Ensure that the literals used by the secondary boot code are - * assembled within it (this is required so that we can protect - * this area with a single memreserve region - */ - .ltorg - - /* 64 bit alignment for elements accessed as data */ - .align 4 - .global __real_cntfrq -__real_cntfrq: - .quad COUNTER_FREQUENCY - .globl __secondary_boot_code_size - .type __secondary_boot_code_size, %object - /* Secondary Boot Code ends here */ -__secondary_boot_code_size: - .quad .-secondary_boot_code diff --git a/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c b/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c deleted file mode 100644 index 0b79a50..0000000 --- a/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -struct serdes_config { - u8 protocol; - u8 lanes[SRDS_MAX_LANES]; -}; - -static struct serdes_config serdes1_cfg_tbl[] = { - /* SerDes 1 */ - {0x03, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2 } }, - {0x05, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII4, SGMII3, SGMII2, SGMII1 } }, - {0x07, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, - SGMII1 } }, - {0x09, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, - SGMII1 } }, - {0x0A, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, - SGMII1 } }, - {0x0C, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, - SGMII1 } }, - {0x0E, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, - SGMII1 } }, - {0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } }, - {0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } }, - {0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } }, - {0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } }, - {0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } }, - {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A, - QSGMII_B} }, - {0x35, {QSGMII_C, QSGMII_D, QSGMII_A, PCIE2, XFI4, XFI3, XFI2, XFI1 } }, - {} -}; -static struct serdes_config serdes2_cfg_tbl[] = { - /* SerDes 2 */ - {0x07, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, - SGMII16 } }, - {0x09, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, - SGMII16 } }, - {0x0A, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, - SGMII16 } }, - {0x0C, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, - SGMII16 } }, - {0x0E, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, - SGMII16 } }, - {0x3D, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } }, - {0x3E, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } }, - {0x3F, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } }, - {0x40, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } }, - {0x41, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } }, - {0x42, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } }, - {0x43, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } }, - {0x44, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } }, - {0x45, {PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15, - SGMII16 } }, - {0x47, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4, - PCIE4 } }, - {0x49, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, - SATA2 } }, - {0x4A, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, - SATA2 } }, - {} -}; - -static struct serdes_config *serdes_cfg_tbl[] = { - serdes1_cfg_tbl, - serdes2_cfg_tbl, -}; - -enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) -{ - struct serdes_config *ptr; - - if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) - return 0; - - ptr = serdes_cfg_tbl[serdes]; - while (ptr->protocol) { - if (ptr->protocol == cfg) - return ptr->lanes[lane]; - ptr++; - } - - return 0; -} - -int is_serdes_prtcl_valid(int serdes, u32 prtcl) -{ - int i; - struct serdes_config *ptr; - - if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) - return 0; - - ptr = serdes_cfg_tbl[serdes]; - while (ptr->protocol) { - if (ptr->protocol == prtcl) - break; - ptr++; - } - - if (!ptr->protocol) - return 0; - - for (i = 0; i < SRDS_MAX_LANES; i++) { - if (ptr->lanes[i] != NONE) - return 1; - } - - return 0; -} diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.c b/arch/arm/cpu/armv8/fsl-lsch3/mp.c deleted file mode 100644 index da7853a..0000000 --- a/arch/arm/cpu/armv8/fsl-lsch3/mp.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include "mp.h" - -DECLARE_GLOBAL_DATA_PTR; - -void *get_spin_tbl_addr(void) -{ - return &__spin_table; -} - -phys_addr_t determine_mp_bootpg(void) -{ - return (phys_addr_t)&secondary_boot_code; -} - -int fsl_lsch3_wake_seconday_cores(void) -{ - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR); - u32 cores, cpu_up_mask = 1; - int i, timeout = 10; - u64 *table = get_spin_tbl_addr(); - -#ifdef COUNTER_FREQUENCY_REAL - /* update for secondary cores */ - __real_cntfrq = COUNTER_FREQUENCY_REAL; - flush_dcache_range((unsigned long)&__real_cntfrq, - (unsigned long)&__real_cntfrq + 8); -#endif - - cores = cpu_mask(); - /* Clear spin table so that secondary processors - * observe the correct value after waking up from wfe. - */ - memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE); - flush_dcache_range((unsigned long)table, - (unsigned long)table + - (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE)); - - printf("Waking secondary cores to start from %lx\n", gd->relocaddr); - out_le32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32)); - out_le32(&gur->bootlocptrl, (u32)gd->relocaddr); - out_le32(&gur->scratchrw[6], 1); - asm volatile("dsb st" : : : "memory"); - rst->brrl = cores; - asm volatile("dsb st" : : : "memory"); - - /* This is needed as a precautionary measure. - * If some code before this has accidentally released the secondary - * cores then the pre-bootloader code will trap them in a "wfe" unless - * the scratchrw[6] is set. In this case we need a sev here to get these - * cores moving again. - */ - asm volatile("sev"); - - while (timeout--) { - flush_dcache_range((unsigned long)table, (unsigned long)table + - CONFIG_MAX_CPUS * 64); - for (i = 1; i < CONFIG_MAX_CPUS; i++) { - if (table[i * WORDS_PER_SPIN_TABLE_ENTRY + - SPIN_TABLE_ELEM_STATUS_IDX]) - cpu_up_mask |= 1 << i; - } - if (hweight32(cpu_up_mask) == hweight32(cores)) - break; - udelay(10); - } - if (timeout <= 0) { - printf("Not all cores (0x%x) are up (0x%x)\n", - cores, cpu_up_mask); - return 1; - } - printf("All (%d) cores are up.\n", hweight32(cores)); - - return 0; -} - -int is_core_valid(unsigned int core) -{ - return !!((1 << core) & cpu_mask()); -} - -int is_core_online(u64 cpu_id) -{ - u64 *table; - int pos = id_to_core(cpu_id); - table = (u64 *)get_spin_tbl_addr() + pos * WORDS_PER_SPIN_TABLE_ENTRY; - return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1; -} - -int cpu_reset(int nr) -{ - puts("Feature is not implemented.\n"); - - return 0; -} - -int cpu_disable(int nr) -{ - puts("Feature is not implemented.\n"); - - return 0; -} - -int core_to_pos(int nr) -{ - u32 cores = cpu_mask(); - int i, count = 0; - - if (nr == 0) { - return 0; - } else if (nr >= hweight32(cores)) { - puts("Not a valid core number.\n"); - return -1; - } - - for (i = 1; i < 32; i++) { - if (is_core_valid(i)) { - count++; - if (count == nr) - break; - } - } - - return count; -} - -int cpu_status(int nr) -{ - u64 *table; - int pos; - - if (nr == 0) { - table = (u64 *)get_spin_tbl_addr(); - printf("table base @ 0x%p\n", table); - } else { - pos = core_to_pos(nr); - if (pos < 0) - return -1; - table = (u64 *)get_spin_tbl_addr() + pos * - WORDS_PER_SPIN_TABLE_ENTRY; - printf("table @ 0x%p\n", table); - printf(" addr - 0x%016llx\n", - table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX]); - printf(" status - 0x%016llx\n", - table[SPIN_TABLE_ELEM_STATUS_IDX]); - printf(" lpid - 0x%016llx\n", - table[SPIN_TABLE_ELEM_LPID_IDX]); - } - - return 0; -} - -int cpu_release(int nr, int argc, char * const argv[]) -{ - u64 boot_addr; - u64 *table = (u64 *)get_spin_tbl_addr(); - int pos; - - pos = core_to_pos(nr); - if (pos <= 0) - return -1; - - table += pos * WORDS_PER_SPIN_TABLE_ENTRY; - boot_addr = simple_strtoull(argv[0], NULL, 16); - table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr; - flush_dcache_range((unsigned long)table, - (unsigned long)table + SPIN_TABLE_ELEM_SIZE); - asm volatile("dsb st"); - smp_kick_all_cpus(); /* only those with entry addr set will run */ - - return 0; -} diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.h b/arch/arm/cpu/armv8/fsl-lsch3/mp.h deleted file mode 100644 index c985d6a..0000000 --- a/arch/arm/cpu/armv8/fsl-lsch3/mp.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright 2014, Freescale Semiconductor - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _FSL_CH3_MP_H -#define _FSL_CH3_MP_H - -/* -* Each spin table element is defined as -* struct { -* uint64_t entry_addr; -* uint64_t status; -* uint64_t lpid; -* }; -* we pad this struct to 64 bytes so each entry is in its own cacheline -* the actual spin table is an array of these structures -*/ -#define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0 -#define SPIN_TABLE_ELEM_STATUS_IDX 1 -#define SPIN_TABLE_ELEM_LPID_IDX 2 -#define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */ -#define SPIN_TABLE_ELEM_SIZE 64 - -#define id_to_core(x) ((x & 3) | (x >> 6)) -#ifndef __ASSEMBLY__ -extern u64 __spin_table[]; -extern u64 __real_cntfrq; -extern u64 *secondary_boot_code; -extern size_t __secondary_boot_code_size; -int fsl_lsch3_wake_seconday_cores(void); -void *get_spin_tbl_addr(void); -phys_addr_t determine_mp_bootpg(void); -void secondary_boot_func(void); -int is_core_online(u64 cpu_id); -#endif -#endif /* _FSL_CH3_MP_H */ diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c b/arch/arm/cpu/armv8/fsl-lsch3/soc.c deleted file mode 100644 index 2538001..0000000 --- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright 2015 Freescale Semiconductor - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -static void erratum_a008751(void) -{ -#ifdef CONFIG_SYS_FSL_ERRATUM_A008751 - u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; - - writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4); -#endif -} - -static void erratum_rcw_src(void) -{ -#if defined(CONFIG_SPL) - u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; - u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE; - u32 val; - - val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); - val &= ~DCFG_PORSR1_RCW_SRC; - val |= DCFG_PORSR1_RCW_SRC_NOR; - out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val); -#endif -} - -#define I2C_DEBUG_REG 0x6 -#define I2C_GLITCH_EN 0x8 -/* - * This erratum requires setting glitch_en bit to enable - * digital glitch filter to improve clock stability. - */ -static void erratum_a009203(void) -{ - u8 __iomem *ptr; -#ifdef CONFIG_SYS_I2C -#ifdef I2C1_BASE_ADDR - ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); - - writeb(I2C_GLITCH_EN, ptr); -#endif -#ifdef I2C2_BASE_ADDR - ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG); - - writeb(I2C_GLITCH_EN, ptr); -#endif -#ifdef I2C3_BASE_ADDR - ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG); - - writeb(I2C_GLITCH_EN, ptr); -#endif -#ifdef I2C4_BASE_ADDR - ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG); - - writeb(I2C_GLITCH_EN, ptr); -#endif -#endif -} - -void fsl_lsch3_early_init_f(void) -{ - erratum_a008751(); - erratum_rcw_src(); - init_early_memctl_regs(); /* tighten IFC timing */ - erratum_a009203(); -} - -#ifdef CONFIG_SPL_BUILD -void board_init_f(ulong dummy) -{ - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); - - arch_cpu_init(); - board_early_init_f(); - timer_init(); - env_init(); - gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); - - serial_init(); - console_init_f(); - dram_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - board_init_r(NULL, 0); -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_NAND; -} -#endif diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c b/arch/arm/cpu/armv8/fsl-lsch3/speed.c deleted file mode 100644 index d9f137c..0000000 --- a/arch/arm/cpu/armv8/fsl-lsch3/speed.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * Copyright 2014, Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Derived from arch/power/cpu/mpc85xx/speed.c - */ - -#include -#include -#include -#include -#include -#include -#include -#include "cpu.h" - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS -#define CONFIG_SYS_FSL_NUM_CC_PLLS 6 -#endif - - -void get_sys_info(struct sys_info *sys_info) -{ - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); -#ifdef CONFIG_FSL_IFC - struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; - u32 ccr; -#endif - struct ccsr_clk_cluster_group __iomem *clk_grp[2] = { - (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR), - (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR) - }; - struct ccsr_clk_ctrl __iomem *clk_ctrl = - (void *)(CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR); - unsigned int cpu; - const u8 core_cplx_pll[16] = { - [0] = 0, /* CC1 PPL / 1 */ - [1] = 0, /* CC1 PPL / 2 */ - [2] = 0, /* CC1 PPL / 4 */ - [4] = 1, /* CC2 PPL / 1 */ - [5] = 1, /* CC2 PPL / 2 */ - [6] = 1, /* CC2 PPL / 4 */ - [8] = 2, /* CC3 PPL / 1 */ - [9] = 2, /* CC3 PPL / 2 */ - [10] = 2, /* CC3 PPL / 4 */ - [12] = 3, /* CC4 PPL / 1 */ - [13] = 3, /* CC4 PPL / 2 */ - [14] = 3, /* CC4 PPL / 4 */ - }; - - const u8 core_cplx_pll_div[16] = { - [0] = 1, /* CC1 PPL / 1 */ - [1] = 2, /* CC1 PPL / 2 */ - [2] = 4, /* CC1 PPL / 4 */ - [4] = 1, /* CC2 PPL / 1 */ - [5] = 2, /* CC2 PPL / 2 */ - [6] = 4, /* CC2 PPL / 4 */ - [8] = 1, /* CC3 PPL / 1 */ - [9] = 2, /* CC3 PPL / 2 */ - [10] = 4, /* CC3 PPL / 4 */ - [12] = 1, /* CC4 PPL / 1 */ - [13] = 2, /* CC4 PPL / 2 */ - [14] = 4, /* CC4 PPL / 4 */ - }; - - uint i, cluster; - uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; - uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; - unsigned long sysclk = CONFIG_SYS_CLK_FREQ; - int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS; - u32 c_pll_sel, cplx_pll; - void *offset; - - sys_info->freq_systembus = sysclk; -#ifdef CONFIG_DDR_CLK_FREQ - sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; - sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ; -#else - sys_info->freq_ddrbus = sysclk; - sys_info->freq_ddrbus2 = sysclk; -#endif - - sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >> - FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) & - FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK; - /* Platform clock is half of platform PLL */ - sys_info->freq_systembus /= 2; - sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >> - FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & - FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; - sys_info->freq_ddrbus2 *= (in_le32(&gur->rcwsr[0]) >> - FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) & - FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK; - - for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { - /* - * fixme: prefer to combine the following into one line, but - * cannot pass compiling without warning about in_le32. - */ - offset = (void *)((size_t)clk_grp[i/3] + - offsetof(struct ccsr_clk_cluster_group, - pllngsr[i%3].gsr)); - ratio[i] = (in_le32(offset) >> 1) & 0x3f; - freq_c_pll[i] = sysclk * ratio[i]; - } - - for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { - cluster = fsl_qoriq_core_to_cluster(cpu); - c_pll_sel = (in_le32(&clk_ctrl->clkcncsr[cluster].csr) >> 27) - & 0xf; - cplx_pll = core_cplx_pll[c_pll_sel]; - cplx_pll += cc_group[cluster] - 1; - sys_info->freq_processor[cpu] = - freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; - } - -#if defined(CONFIG_FSL_IFC) - ccr = in_le32(&ifc_regs.gregs->ifc_ccr); - ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; - - sys_info->freq_localbus = sys_info->freq_systembus / ccr; -#endif -} - - -int get_clocks(void) -{ - struct sys_info sys_info; - get_sys_info(&sys_info); - gd->cpu_clk = sys_info.freq_processor[0]; - gd->bus_clk = sys_info.freq_systembus; - gd->mem_clk = sys_info.freq_ddrbus; - gd->arch.mem2_clk = sys_info.freq_ddrbus2; -#if defined(CONFIG_FSL_ESDHC) - gd->arch.sdhc_clk = gd->bus_clk / 2; -#endif /* defined(CONFIG_FSL_ESDHC) */ - - if (gd->cpu_clk != 0) - return 0; - else - return 1; -} - -/******************************************** - * get_bus_freq - * return system bus freq in Hz - *********************************************/ -ulong get_bus_freq(ulong dummy) -{ - if (!gd->bus_clk) - get_clocks(); - - return gd->bus_clk; -} - -/******************************************** - * get_ddr_freq - * return ddr bus freq in Hz - *********************************************/ -ulong get_ddr_freq(ulong ctrl_num) -{ - if (!gd->mem_clk) - get_clocks(); - - /* - * DDR controller 0 & 1 are on memory complex 0 - * DDR controler 2 is on memory complext 1 - */ - if (ctrl_num >= 2) - return gd->arch.mem2_clk; - - return gd->mem_clk; -} - -unsigned int mxc_get_clock(enum mxc_clock clk) -{ - switch (clk) { - case MXC_I2C_CLK: - return get_bus_freq(0) / 2; - case MXC_DSPI_CLK: - return get_bus_freq(0) / 2; - default: - printf("Unsupported clock\n"); - } - return 0; -} diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.h b/arch/arm/cpu/armv8/fsl-lsch3/speed.h deleted file mode 100644 index 15af5b9..0000000 --- a/arch/arm/cpu/armv8/fsl-lsch3/speed.h +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright 2014, Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -void get_sys_info(struct sys_info *sys_info); diff --git a/arch/arm/include/asm/arch-fsl-layerscape/clock.h b/arch/arm/include/asm/arch-fsl-layerscape/clock.h new file mode 100644 index 0000000..6935913 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/clock.h @@ -0,0 +1,24 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ +#define __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ + +#include + +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_BUS_CLK, + MXC_UART_CLK, + MXC_ESDHC_CLK, + MXC_I2C_CLK, + MXC_DSPI_CLK, +}; + +unsigned int mxc_get_clock(enum mxc_clock clk); + +#endif /* __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h new file mode 100644 index 0000000..dd7203f --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -0,0 +1,96 @@ +/* + * Copyright 2015, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ +#define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ + +#include + +#ifdef CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_FSL_DDRC_GEN4 +#else +#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */ +#endif +#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 + +#if defined(CONFIG_LS2085A) +#define CONFIG_MAX_CPUS 16 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define CONFIG_NUM_DDR_CONTROLLERS 3 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } +#define SRDS_MAX_LANES 8 +#define CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_FSL_SRDS_2 +#define CONFIG_SYS_PAGE_SIZE 0x10000 +#define CONFIG_SYS_CACHELINE_SIZE 64 +#ifndef L1_CACHE_BYTES +#define L1_CACHE_SHIFT 6 +#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) +#endif + +#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ + +/* DDR */ +#define CONFIG_SYS_FSL_DDR_LE +#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE + +#define CONFIG_SYS_FSL_CCSR_GUR_LE +#define CONFIG_SYS_FSL_CCSR_SCFG_LE +#define CONFIG_SYS_FSL_ESDHC_LE +#define CONFIG_SYS_FSL_IFC_LE + +#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x06000000 +#define GICR_BASE 0x06100000 + +/* SMMU Defintions */ +#define SMMU_BASE 0x05000000 /* GR0 Base */ + +/* Cache Coherent Interconnect */ +#define CCI_MN_BASE 0x04000000 +#define CCI_MN_RNF_NODEID_LIST 0x180 +#define CCI_MN_DVM_DOMAIN_CTL 0x200 +#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 + +#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) +#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) +#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) +#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000) +#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000) +#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000) + +#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10) +#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) +#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) + +/* TZ Protection Controller Definitions */ +#define TZPC_BASE 0x02200000 +#define TZPCR0SIZE_BASE (TZPC_BASE) +#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) +#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) +#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) +#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) +#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) +#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) +#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) +#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) +#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) + +#define CONFIG_SYS_FSL_ERRATUM_A008336 +#define CONFIG_SYS_FSL_ERRATUM_A008511 +#define CONFIG_SYS_FSL_ERRATUM_A008514 +#define CONFIG_SYS_FSL_ERRATUM_A008585 +#define CONFIG_SYS_FSL_ERRATUM_A008751 +#else +#error SoC not defined +#endif + +#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h new file mode 100644 index 0000000..b7b8e5d --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -0,0 +1,165 @@ +/* + * Copyright 2014-2015, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FSL_LAYERSCAPE_CPU_H +#define _FSL_LAYERSCAPE_CPU_H + +static struct cpu_type cpu_type_list[] = { + CPU_TYPE_ENTRY(LS2085, LS2085, 8), + CPU_TYPE_ENTRY(LS2080, LS2080, 8), + CPU_TYPE_ENTRY(LS2045, LS2045, 4), +}; + +#ifndef CONFIG_SYS_DCACHE_OFF + +#define SECTION_SHIFT_L0 39UL +#define SECTION_SHIFT_L1 30UL +#define SECTION_SHIFT_L2 21UL +#define BLOCK_SIZE_L0 0x8000000000 +#define BLOCK_SIZE_L1 0x40000000 +#define BLOCK_SIZE_L2 0x200000 +#define NUM_OF_ENTRY 512 +#define TCR_EL2_PS_40BIT (2 << 16) + +#define LAYERSCAPE_VA_BITS (40) +#define LAYERSCAPE_TCR (TCR_TG0_4K | \ + TCR_EL2_PS_40BIT | \ + TCR_SHARED_NON | \ + TCR_ORGN_NC | \ + TCR_IRGN_NC | \ + TCR_T0SZ(LAYERSCAPE_VA_BITS)) +#define LAYERSCAPE_TCR_FINAL (TCR_TG0_4K | \ + TCR_EL2_PS_40BIT | \ + TCR_SHARED_OUTER | \ + TCR_ORGN_WBWA | \ + TCR_IRGN_WBWA | \ + TCR_T0SZ(LAYERSCAPE_VA_BITS)) + +#ifdef CONFIG_FSL_LSCH3 +#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000 +#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 +#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000 +#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000 +#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000 +#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000 +#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000 +#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 +#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 +#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000 +#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000 +#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000 +#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000 +#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000 +#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000 +#define CONFIG_SYS_FSL_MC_BASE 0x80c000000 +#define CONFIG_SYS_FSL_MC_SIZE 0x4000000 +#define CONFIG_SYS_FSL_NI_BASE 0x810000000 +#define CONFIG_SYS_FSL_NI_SIZE 0x8000000 +#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000 +#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000 +#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000 +#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000 +#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000 +#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000 +#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 +#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000 +#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000 +#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000 +#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 +#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 +#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 +#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000 +#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 +#endif + +struct sys_mmu_table { + u64 virt_addr; + u64 phys_addr; + u64 size; + u64 memory_type; + u64 share; +}; + +struct table_info { + u64 *ptr; + u64 table_base; + u64 entry_size; +}; + +static const struct sys_mmu_table early_mmu_table[] = { +#ifdef CONFIG_FSL_LSCH3 + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, + /* For IFC Region #1, only the first 4MB is cache-enabled */ + { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, + CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, + CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, + CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, + MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, + CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, +#endif +}; + +static const struct sys_mmu_table final_mmu_table[] = { +#ifdef CONFIG_FSL_LSCH3 + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, + CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, + CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, + CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, + CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + /* For QBMAN portal, only the first 64MB is cache-enabled */ + { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, + CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, + CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, + CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, + MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, + CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, + CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, + CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, +#ifdef CONFIG_LS2085A + { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, + CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, +#endif + { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, + CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, + CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, + CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, +#endif +}; +#endif + +int fsl_qoriq_core_to_cluster(unsigned int core); +u32 cpu_mask(void); +#endif /* _FSL_LAYERSCAPE_CPU_H */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fdt.h b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h new file mode 100644 index 0000000..4da73ab --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h @@ -0,0 +1,14 @@ +/* + * Copyright 2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ +#define _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ + +void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt); +void append_mmu_masters(void *blob, const char *smmu_path, + const char *master_name, u32 *stream_ids, int count); +void fdt_fixup_smmu_pcie(void *blob); +#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h new file mode 100644 index 0000000..730c2b2 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -0,0 +1,66 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_SERDES_H__ +#define __FSL_SERDES_H__ + +#include + +#if defined(CONFIG_LS2085A) +enum srds_prtcl { + NONE = 0, + PCIE1, + PCIE2, + PCIE3, + PCIE4, + SATA1, + SATA2, + XAUI1, + XAUI2, + XFI1, + XFI2, + XFI3, + XFI4, + XFI5, + XFI6, + XFI7, + XFI8, + SGMII1, + SGMII2, + SGMII3, + SGMII4, + SGMII5, + SGMII6, + SGMII7, + SGMII8, + SGMII9, + SGMII10, + SGMII11, + SGMII12, + SGMII13, + SGMII14, + SGMII15, + SGMII16, + QSGMII_A, /* A indicates MACs 1-4 */ + QSGMII_B, /* B indicates MACs 5-8 */ + QSGMII_C, /* C indicates MACs 9-12 */ + QSGMII_D, /* D indicates MACs 12-16 */ + SERDES_PRCTL_COUNT +}; + +enum srds { + FSL_SRDS_1 = 0, + FSL_SRDS_2 = 1, +}; +#endif + +int is_serdes_configured(enum srds_prtcl device); +void fsl_serdes_init(void); +int serdes_get_first_lane(u32 sd, enum srds_prtcl device); +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); +int is_serdes_prtcl_valid(int serdes, u32 prtcl); + +#endif /* __FSL_SERDES_H__ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h new file mode 100644 index 0000000..6a70d44 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -0,0 +1,268 @@ +/* + * LayerScape Internal Memory Map + * + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_FSL_LSCH3_IMMAP_H_ +#define __ARCH_FSL_LSCH3_IMMAP_H_ + +#define CONFIG_SYS_IMMR 0x01000000 +#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) +#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000) +#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 +#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) +#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) +#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000) +#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) +#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) +#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) +#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) +#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) +#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000 +#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ + 0x18A0) + +#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000) +#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000) +#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000) +#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000) + +/* SP (Cortex-A5) related */ +#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000) +#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR) +#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR) +#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \ + (CONFIG_SYS_FSL_SP_ADDR + 0x0008) +#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \ + (CONFIG_SYS_FSL_SP_ADDR + 0x1000) + +#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL +#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL +#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL +#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL + +#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) +#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) +#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) +#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) + +#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) + +/* TZ Address Space Controller Definitions */ +#define TZASC1_BASE 0x01100000 /* as per CCSR map. */ +#define TZASC2_BASE 0x01110000 /* as per CCSR map. */ +#define TZASC3_BASE 0x01120000 /* as per CCSR map. */ +#define TZASC4_BASE 0x01130000 /* as per CCSR map. */ +#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) +#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) +#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) +#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) +#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) +#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) +#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) +#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) +#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) + +/* PCIe */ +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) +#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) +#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000) +#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL +#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL +#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL +#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL + +/* Device Configuration */ +#define DCFG_BASE 0x01e00000 +#define DCFG_PORSR1 0x000 +#define DCFG_PORSR1_RCW_SRC 0xff800000 +#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 +#define DCFG_RCWSR13 0x130 +#define DCFG_RCWSR13_DSPI (0 << 8) + +#define DCFG_DCSR_BASE 0X700100000ULL +#define DCFG_DCSR_PORCR1 0x000 + +/* Supplemental Configuration */ +#define SCFG_BASE 0x01fc0000 +#define SCFG_USB3PRM1CR 0x000 + +#define TP_ITYP_AV 0x00000001 /* Initiator available */ +#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ +#define TP_ITYP_TYPE_ARM 0x0 +#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ +#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ +#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ +#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ +#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ +#define TY_ITYP_VER_A7 0x1 +#define TY_ITYP_VER_A53 0x2 +#define TY_ITYP_VER_A57 0x3 + +#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */ +#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ +#define TP_INIT_PER_CLUSTER 4 +/* This is chassis generation 3 */ + +struct sys_info { + unsigned long freq_processor[CONFIG_MAX_CPUS]; + unsigned long freq_systembus; + unsigned long freq_ddrbus; + unsigned long freq_ddrbus2; + unsigned long freq_localbus; + unsigned long freq_qe; +#ifdef CONFIG_SYS_DPAA_FMAN + unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; +#endif +#ifdef CONFIG_SYS_DPAA_QBMAN + unsigned long freq_qman; +#endif +#ifdef CONFIG_SYS_DPAA_PME + unsigned long freq_pme; +#endif +}; + +/* Global Utilities Block */ +struct ccsr_gur { + u32 porsr1; /* POR status 1 */ + u32 porsr2; /* POR status 2 */ + u8 res_008[0x20-0x8]; + u32 gpporcr1; /* General-purpose POR configuration */ + u32 gpporcr2; /* General-purpose POR configuration 2 */ + u32 dcfg_fusesr; /* Fuse status register */ + u32 gpporcr3; + u32 gpporcr4; + u8 res_034[0x70-0x34]; + u32 devdisr; /* Device disable control */ + u32 devdisr2; /* Device disable control 2 */ + u32 devdisr3; /* Device disable control 3 */ + u32 devdisr4; /* Device disable control 4 */ + u32 devdisr5; /* Device disable control 5 */ + u32 devdisr6; /* Device disable control 6 */ + u32 devdisr7; /* Device disable control 7 */ +#define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x00000001 +#define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x00000002 +#define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x00000004 +#define FSL_CHASSIS3_DEVDISR2_DPMAC4 0x00000008 +#define FSL_CHASSIS3_DEVDISR2_DPMAC5 0x00000010 +#define FSL_CHASSIS3_DEVDISR2_DPMAC6 0x00000020 +#define FSL_CHASSIS3_DEVDISR2_DPMAC7 0x00000040 +#define FSL_CHASSIS3_DEVDISR2_DPMAC8 0x00000080 +#define FSL_CHASSIS3_DEVDISR2_DPMAC9 0x00000100 +#define FSL_CHASSIS3_DEVDISR2_DPMAC10 0x00000200 +#define FSL_CHASSIS3_DEVDISR2_DPMAC11 0x00000400 +#define FSL_CHASSIS3_DEVDISR2_DPMAC12 0x00000800 +#define FSL_CHASSIS3_DEVDISR2_DPMAC13 0x00001000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC14 0x00002000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC15 0x00004000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC16 0x00008000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC17 0x00010000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC18 0x00020000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC19 0x00040000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC20 0x00080000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC21 0x00100000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x00200000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x00400000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x00800000 + u8 res_08c[0x90-0x8c]; + u32 coredisru; /* uppper portion for support of 64 cores */ + u32 coredisrl; /* lower portion for support of 64 cores */ + u8 res_098[0xa0-0x98]; + u32 pvr; /* Processor version */ + u32 svr; /* System version */ + u32 mvr; /* Manufacturing version */ + u8 res_0ac[0x100-0xac]; + u32 rcwsr[32]; /* Reset control word status */ + +#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2 +#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f +#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10 +#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f +#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18 +#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f +#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000 +#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 +#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000 +#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24 + + u8 res_180[0x200-0x180]; + u32 scratchrw[32]; /* Scratch Read/Write */ + u8 res_280[0x300-0x280]; + u32 scratchw1r[4]; /* Scratch Read (Write once) */ + u8 res_310[0x400-0x310]; + u32 bootlocptrl; /* Boot location pointer low-order addr */ + u32 bootlocptrh; /* Boot location pointer high-order addr */ + u8 res_408[0x500-0x408]; + u8 res_500[0x740-0x500]; /* add more registers when needed */ + u32 tp_ityp[64]; /* Topology Initiator Type Register */ + struct { + u32 upper; + u32 lower; + } tp_cluster[3]; /* Core Cluster n Topology Register */ + u8 res_858[0x1000-0x858]; +}; + + +struct ccsr_clk_cluster_group { + struct { + u8 res_00[0x10]; + u32 csr; + u8 res_14[0x20-0x14]; + } hwncsr[3]; + u8 res_60[0x80-0x60]; + struct { + u32 gsr; + u8 res_84[0xa0-0x84]; + } pllngsr[3]; + u8 res_e0[0x100-0xe0]; +}; + +struct ccsr_clk_ctrl { + struct { + u32 csr; /* core cluster n clock control status */ + u8 res_04[0x20-0x04]; + } clkcncsr[8]; +}; + +struct ccsr_reset { + u32 rstcr; /* 0x000 */ + u32 rstcrsp; /* 0x004 */ + u8 res_008[0x10-0x08]; /* 0x008 */ + u32 rstrqmr1; /* 0x010 */ + u32 rstrqmr2; /* 0x014 */ + u32 rstrqsr1; /* 0x018 */ + u32 rstrqsr2; /* 0x01c */ + u32 rstrqwdtmrl; /* 0x020 */ + u32 rstrqwdtmru; /* 0x024 */ + u8 res_028[0x30-0x28]; /* 0x028 */ + u32 rstrqwdtsrl; /* 0x030 */ + u32 rstrqwdtsru; /* 0x034 */ + u8 res_038[0x60-0x38]; /* 0x038 */ + u32 brrl; /* 0x060 */ + u32 brru; /* 0x064 */ + u8 res_068[0x80-0x68]; /* 0x068 */ + u32 pirset; /* 0x080 */ + u32 pirclr; /* 0x084 */ + u8 res_088[0x90-0x88]; /* 0x088 */ + u32 brcorenbr; /* 0x090 */ + u8 res_094[0x100-0x94]; /* 0x094 */ + u32 rcw_reqr; /* 0x100 */ + u32 rcw_completion; /* 0x104 */ + u8 res_108[0x110-0x108]; /* 0x108 */ + u32 pbi_reqr; /* 0x110 */ + u32 pbi_completion; /* 0x114 */ + u8 res_118[0xa00-0x118]; /* 0x118 */ + u32 qmbm_warmrst; /* 0xa00 */ + u32 soc_warmrst; /* 0xa04 */ + u8 res_a08[0xbf8-0xa08]; /* 0xa08 */ + u32 ip_rev1; /* 0xbf8 */ + u32 ip_rev2; /* 0xbfc */ +}; +#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h new file mode 100644 index 0000000..57e417b --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h @@ -0,0 +1,55 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ +#define __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ + +#define I2C_QUIRK_REG /* enable 8-bit driver */ + +#ifdef CONFIG_FSL_LPUART +#ifdef CONFIG_LPUART_32B_REG +struct lpuart_fsl { + u32 baud; + u32 stat; + u32 ctrl; + u32 data; + u32 match; + u32 modir; + u32 fifo; + u32 water; +}; +#else +struct lpuart_fsl { + u8 ubdh; + u8 ubdl; + u8 uc1; + u8 uc2; + u8 us1; + u8 us2; + u8 uc3; + u8 ud; + u8 uma1; + u8 uma2; + u8 uc4; + u8 uc5; + u8 ued; + u8 umodem; + u8 uir; + u8 reserved; + u8 upfifo; + u8 ucfifo; + u8 usfifo; + u8 utwfifo; + u8 utcfifo; + u8 urwfifo; + u8 urcfifo; + u8 rsvd[28]; +}; +#endif +#endif /* CONFIG_FSL_LPUART */ + +#endif /* __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ls2085a_stream_id.h b/arch/arm/include/asm/arch-fsl-layerscape/ls2085a_stream_id.h new file mode 100644 index 0000000..5c94530 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/ls2085a_stream_id.h @@ -0,0 +1,64 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ +#ifndef __FSL_STREAM_ID_H +#define __FSL_STREAM_ID_H + +/* Stream IDs on ls2085a devices are not hardwired and are + * programmed by sw. There are a limited number of stream IDs + * available, and the partitioning of them is scenario dependent. + * This header defines the partitioning between legacy, PCI, + * and DPAA2 devices. + * + * This partitiong can be customized in this file depending + * on the specific hardware config-- e.g. perhaps not all + * PEX controllers are in use. + * + * On LS2085 stream IDs are programmed in AMQ registers (32-bits) for + * each of the different bus masters. The relationship between + * the AMQ registers and stream IDs is defined in the table below: + * AMQ bit streamID bit + * --------------------------- + * PL[18] 9 + * BMT[17] 8 + * VA[16] 7 + * [15] - + * ICID[14:7] - + * ICID[6:0] 6-0 + * ---------------------------- + */ + +#define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */ +#define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */ + +#define FSL_INVALID_STREAM_ID 0 + +#define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK) + +/* legacy devices */ +#define FSL_USB1_STREAM_ID 1 +#define FSL_USB2_STREAM_ID 2 +#define FSL_SDMMC_STREAM_ID 3 +#define FSL_SATA1_STREAM_ID 4 +#define FSL_SATA2_STREAM_ID 5 +#define FSL_DMA_STREAM_ID 6 + +/* PCI - programmed in PEXn_LUT by OS */ +/* 4 IDs per controller */ +#define FSL_PEX1_STREAM_ID_START 7 +#define FSL_PEX1_STREAM_ID_END 10 +#define FSL_PEX2_STREAM_ID_START 11 +#define FSL_PEX2_STREAM_ID_END 14 +#define FSL_PEX3_STREAM_ID_START 15 +#define FSL_PEX3_STREAM_ID_END 18 +#define FSL_PEX4_STREAM_ID_START 19 +#define FSL_PEX4_STREAM_ID_END 22 + +/* DPAA2 - set in MC DPC and alloced by MC */ +#define FSL_DPAA2_STREAM_ID_START 23 +#define FSL_DPAA2_STREAM_ID_END 63 + +#endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mmu.h b/arch/arm/include/asm/arch-fsl-layerscape/mmu.h new file mode 100644 index 0000000..d54eacd --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/mmu.h @@ -0,0 +1,10 @@ +/* + * Copyright 2015, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ +#define _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ +#include +#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h new file mode 100644 index 0000000..e46e076 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h @@ -0,0 +1,38 @@ +/* + * Copyright 2014-2015, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FSL_LAYERSCAPE_MP_H +#define _FSL_LAYERSCAPE_MP_H + +/* +* Each spin table element is defined as +* struct { +* uint64_t entry_addr; +* uint64_t status; +* uint64_t lpid; +* }; +* we pad this struct to 64 bytes so each entry is in its own cacheline +* the actual spin table is an array of these structures +*/ +#define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0 +#define SPIN_TABLE_ELEM_STATUS_IDX 1 +#define SPIN_TABLE_ELEM_LPID_IDX 2 +#define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */ +#define SPIN_TABLE_ELEM_SIZE 64 + +#define id_to_core(x) ((x & 3) | (x >> 6)) +#ifndef __ASSEMBLY__ +extern u64 __spin_table[]; +extern u64 __real_cntfrq; +extern u64 *secondary_boot_code; +extern size_t __secondary_boot_code_size; +int fsl_layerscape_wake_seconday_cores(void); +void *get_spin_tbl_addr(void); +phys_addr_t determine_mp_bootpg(void); +void secondary_boot_func(void); +int is_core_online(u64 cpu_id); +#endif +#endif /* _FSL_LAYERSCAPE_MP_H */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h new file mode 100644 index 0000000..f131f57 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -0,0 +1,47 @@ +/* + * Copyright 2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ +#define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ + +#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE +#define gur_in32(a) in_le32(a) +#define gur_out32(a, v) out_le32(a, v) +#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE) +#define gur_in32(a) in_be32(a) +#define gur_out32(a, v) out_be32(a, v) +#endif + +#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE +#define scfg_in32(a) in_le32(a) +#define scfg_out32(a, v) out_le32(a, v) +#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE) +#define scfg_in32(a) in_be32(a) +#define scfg_out32(a, v) out_be32(a, v) +#endif + +struct cpu_type { + char name[15]; + u32 soc_ver; + u32 num_cores; +}; + +#define CPU_TYPE_ENTRY(n, v, nc) \ + { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} + +#define SVR_WO_E 0xFFFFFE +#define SVR_LS2045 0x870120 +#define SVR_LS2080 0x870110 +#define SVR_LS2085 0x870100 + +#define SVR_MAJ(svr) (((svr) >> 4) & 0xf) +#define SVR_MIN(svr) (((svr) >> 0) & 0xf) +#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) +#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) + +void fsl_lsch3_early_init_f(void); +void cpu_name(char *name); +#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/speed.h b/arch/arm/include/asm/arch-fsl-layerscape/speed.h new file mode 100644 index 0000000..de795f6 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/speed.h @@ -0,0 +1,10 @@ +/* + * Copyright 2014-2015, Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FSL_LAYERSCAPE_SPEED_H +#define _FSL_LAYERSCAPE_SPEED_H +void get_sys_info(struct sys_info *sys_info); +#endif /* _FSL_LAYERSCAPE_SPEED_H */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/clock.h b/arch/arm/include/asm/arch-fsl-lsch3/clock.h deleted file mode 100644 index 62bc53c..0000000 --- a/arch/arm/include/asm/arch-fsl-lsch3/clock.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - */ - -#ifndef __ASM_ARCH_FSL_LSCH3_CLOCK_H_ -#define __ASM_ARCH_FSL_LSCH3_CLOCK_H_ - -#include - -enum mxc_clock { - MXC_ARM_CLK = 0, - MXC_BUS_CLK, - MXC_UART_CLK, - MXC_ESDHC_CLK, - MXC_I2C_CLK, - MXC_DSPI_CLK, -}; - -unsigned int mxc_get_clock(enum mxc_clock clk); - -#endif /* __ASM_ARCH_FSL_LSCH3_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h deleted file mode 100644 index 96d6c98..0000000 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright 2014, Freescale Semiconductor - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARMV8_FSL_LSCH3_CONFIG_ -#define _ASM_ARMV8_FSL_LSCH3_CONFIG_ - -#include - -#define CONFIG_SYS_PAGE_SIZE 0x10000 -#define CONFIG_SYS_CACHELINE_SIZE 64 - -#ifndef L1_CACHE_BYTES -#define L1_CACHE_SHIFT 6 -#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) -#endif - -#define CONFIG_MP -#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ -#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ -/* Link Definitions */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) - -#define CONFIG_SYS_IMMR 0x01000000 -#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) -#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000) -#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 -#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) -#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) -#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000) -#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) -#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) -#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) -#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) -#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) -#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000 -#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ - 0x18A0) - -#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000) -#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000) -#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000) -#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000) - -/* SP (Cortex-A5) related */ -#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000) -#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR) -#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR) -#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \ - (CONFIG_SYS_FSL_SP_ADDR + 0x0008) -#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \ - (CONFIG_SYS_FSL_SP_ADDR + 0x1000) - -#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL -#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL -#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL -#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL - -#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) -#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) -#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) -#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) - -#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) -#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) - -/* TZ Protection Controller Definitions */ -#define TZPC_BASE 0x02200000 -#define TZPCR0SIZE_BASE (TZPC_BASE) -#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) -#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) -#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) -#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) -#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) -#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) -#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) -#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) -#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) - -/* TZ Address Space Controller Definitions */ -#define TZASC1_BASE 0x01100000 /* as per CCSR map. */ -#define TZASC2_BASE 0x01110000 /* as per CCSR map. */ -#define TZASC3_BASE 0x01120000 /* as per CCSR map. */ -#define TZASC4_BASE 0x01130000 /* as per CCSR map. */ -#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) -#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) -#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) -#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) -#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) -#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) -#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) -#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) -#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) - -/* Generic Interrupt Controller Definitions */ -#define GICD_BASE 0x06000000 -#define GICR_BASE 0x06100000 - -/* SMMU Defintions */ -#define SMMU_BASE 0x05000000 /* GR0 Base */ - -/* DDR */ -#define CONFIG_SYS_FSL_DDR_LE -#define CONFIG_VERY_BIG_RAM -#ifdef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_FSL_DDRC_GEN4 -#else -#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */ -#endif -#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ -#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE -#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 - -#define CONFIG_SYS_FSL_ESDHC_LE -/* IFC */ -#define CONFIG_SYS_FSL_IFC_LE -#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN - -/* PCIe */ -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) -#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000) -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL -#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL - -/* Cache Coherent Interconnect */ -#define CCI_MN_BASE 0x04000000 -#define CCI_MN_RNF_NODEID_LIST 0x180 -#define CCI_MN_DVM_DOMAIN_CTL 0x200 -#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 - -#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) -#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) -#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) -#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000) -#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000) -#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000) - -#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10) -#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) -#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) - -/* Device Configuration */ -#define DCFG_BASE 0x01e00000 -#define DCFG_PORSR1 0x000 -#define DCFG_PORSR1_RCW_SRC 0xff800000 -#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 -#define DCFG_RCWSR13 0x130 -#define DCFG_RCWSR13_DSPI (0 << 8) - -#define DCFG_DCSR_BASE 0X700100000ULL -#define DCFG_DCSR_PORCR1 0x000 - -/* Supplemental Configuration */ -#define SCFG_BASE 0x01fc0000 -#define SCFG_USB3PRM1CR 0x000 - -#ifdef CONFIG_LS2085A -#define CONFIG_MAX_CPUS 16 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_NUM_DDR_CONTROLLERS 3 -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } -#define CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_FSL_SRDS_2 -#else -#error SoC not defined -#endif - -#ifdef CONFIG_LS2085A -#define CONFIG_SYS_FSL_ERRATUM_A008336 -#define CONFIG_SYS_FSL_ERRATUM_A008511 -#define CONFIG_SYS_FSL_ERRATUM_A008514 -#define CONFIG_SYS_FSL_ERRATUM_A008585 -#define CONFIG_SYS_FSL_ERRATUM_A008751 -#endif - -#endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/fdt.h b/arch/arm/include/asm/arch-fsl-lsch3/fdt.h deleted file mode 100644 index 21d20fb..0000000 --- a/arch/arm/include/asm/arch-fsl-lsch3/fdt.h +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Copyright 2015 Freescale Semiconductor - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt); -void append_mmu_masters(void *blob, const char *smmu_path, - const char *master_name, u32 *stream_ids, int count); -void fdt_fixup_smmu_pcie(void *blob); diff --git a/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h deleted file mode 100644 index 2810f3f..0000000 --- a/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __FSL_SERDES_H -#define __FSL_SERDES_H - -#include - -#define SRDS_MAX_LANES 8 - -enum srds_prtcl { - NONE = 0, - PCIE1, - PCIE2, - PCIE3, - PCIE4, - SATA1, - SATA2, - XAUI1, - XAUI2, - XFI1, - XFI2, - XFI3, - XFI4, - XFI5, - XFI6, - XFI7, - XFI8, - SGMII1, - SGMII2, - SGMII3, - SGMII4, - SGMII5, - SGMII6, - SGMII7, - SGMII8, - SGMII9, - SGMII10, - SGMII11, - SGMII12, - SGMII13, - SGMII14, - SGMII15, - SGMII16, - QSGMII_A, /* A indicates MACs 1-4 */ - QSGMII_B, /* B indicates MACs 5-8 */ - QSGMII_C, /* C indicates MACs 9-12 */ - QSGMII_D, /* D indicates MACs 12-16 */ - SERDES_PRCTL_COUNT -}; - -enum srds { - FSL_SRDS_1 = 0, - FSL_SRDS_2 = 1, -}; - -int is_serdes_configured(enum srds_prtcl device); -void fsl_serdes_init(void); - -int serdes_get_first_lane(u32 sd, enum srds_prtcl device); -enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); -int is_serdes_prtcl_valid(int serdes, u32 prtcl); - -#endif /* __FSL_SERDES_H */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/gpio.h b/arch/arm/include/asm/arch-fsl-lsch3/gpio.h deleted file mode 100644 index f23a78c..0000000 --- a/arch/arm/include/asm/arch-fsl-lsch3/gpio.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright 2014, Freescale Semiconductor - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARMV8_FSL_LSCH3_GPIO_H_ -#define _ASM_ARMV8_FSL_LSCH3_GPIO_H_ -#endif /* _ASM_ARMV8_FSL_LSCH3_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h deleted file mode 100644 index d6bee60..0000000 --- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h +++ /dev/null @@ -1,183 +0,0 @@ -/* - * LayerScape Internal Memory Map - * - * Copyright 2014 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ARCH_FSL_LSCH3_IMMAP_H -#define __ARCH_FSL_LSCH3_IMMAP_H_ - -/* This is chassis generation 3 */ - -struct sys_info { - unsigned long freq_processor[CONFIG_MAX_CPUS]; - unsigned long freq_systembus; - unsigned long freq_ddrbus; - unsigned long freq_ddrbus2; - unsigned long freq_localbus; - unsigned long freq_qe; -#ifdef CONFIG_SYS_DPAA_FMAN - unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; -#endif -#ifdef CONFIG_SYS_DPAA_QBMAN - unsigned long freq_qman; -#endif -#ifdef CONFIG_SYS_DPAA_PME - unsigned long freq_pme; -#endif -}; - -/* Global Utilities Block */ -struct ccsr_gur { - u32 porsr1; /* POR status 1 */ - u32 porsr2; /* POR status 2 */ - u8 res_008[0x20-0x8]; - u32 gpporcr1; /* General-purpose POR configuration */ - u32 gpporcr2; /* General-purpose POR configuration 2 */ - u32 dcfg_fusesr; /* Fuse status register */ - u32 gpporcr3; - u32 gpporcr4; - u8 res_034[0x70-0x34]; - u32 devdisr; /* Device disable control */ - u32 devdisr2; /* Device disable control 2 */ - u32 devdisr3; /* Device disable control 3 */ - u32 devdisr4; /* Device disable control 4 */ - u32 devdisr5; /* Device disable control 5 */ - u32 devdisr6; /* Device disable control 6 */ - u32 devdisr7; /* Device disable control 7 */ -#define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x00000001 -#define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x00000002 -#define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x00000004 -#define FSL_CHASSIS3_DEVDISR2_DPMAC4 0x00000008 -#define FSL_CHASSIS3_DEVDISR2_DPMAC5 0x00000010 -#define FSL_CHASSIS3_DEVDISR2_DPMAC6 0x00000020 -#define FSL_CHASSIS3_DEVDISR2_DPMAC7 0x00000040 -#define FSL_CHASSIS3_DEVDISR2_DPMAC8 0x00000080 -#define FSL_CHASSIS3_DEVDISR2_DPMAC9 0x00000100 -#define FSL_CHASSIS3_DEVDISR2_DPMAC10 0x00000200 -#define FSL_CHASSIS3_DEVDISR2_DPMAC11 0x00000400 -#define FSL_CHASSIS3_DEVDISR2_DPMAC12 0x00000800 -#define FSL_CHASSIS3_DEVDISR2_DPMAC13 0x00001000 -#define FSL_CHASSIS3_DEVDISR2_DPMAC14 0x00002000 -#define FSL_CHASSIS3_DEVDISR2_DPMAC15 0x00004000 -#define FSL_CHASSIS3_DEVDISR2_DPMAC16 0x00008000 -#define FSL_CHASSIS3_DEVDISR2_DPMAC17 0x00010000 -#define FSL_CHASSIS3_DEVDISR2_DPMAC18 0x00020000 -#define FSL_CHASSIS3_DEVDISR2_DPMAC19 0x00040000 -#define FSL_CHASSIS3_DEVDISR2_DPMAC20 0x00080000 -#define FSL_CHASSIS3_DEVDISR2_DPMAC21 0x00100000 -#define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x00200000 -#define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x00400000 -#define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x00800000 - u8 res_08c[0x90-0x8c]; - u32 coredisru; /* uppper portion for support of 64 cores */ - u32 coredisrl; /* lower portion for support of 64 cores */ - u8 res_098[0xa0-0x98]; - u32 pvr; /* Processor version */ - u32 svr; /* System version */ - u32 mvr; /* Manufacturing version */ - u8 res_0ac[0x100-0xac]; - u32 rcwsr[32]; /* Reset control word status */ - -#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2 -#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f -#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10 -#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f -#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18 -#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f -#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000 -#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 -#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000 -#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24 - - u8 res_180[0x200-0x180]; - u32 scratchrw[32]; /* Scratch Read/Write */ - u8 res_280[0x300-0x280]; - u32 scratchw1r[4]; /* Scratch Read (Write once) */ - u8 res_310[0x400-0x310]; - u32 bootlocptrl; /* Boot location pointer low-order addr */ - u32 bootlocptrh; /* Boot location pointer high-order addr */ - u8 res_408[0x500-0x408]; - u8 res_500[0x740-0x500]; /* add more registers when needed */ - u32 tp_ityp[64]; /* Topology Initiator Type Register */ - struct { - u32 upper; - u32 lower; - } tp_cluster[3]; /* Core Cluster n Topology Register */ - u8 res_858[0x1000-0x858]; -}; - -#define TP_ITYP_AV 0x00000001 /* Initiator available */ -#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ -#define TP_ITYP_TYPE_ARM 0x0 -#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ -#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ -#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ -#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ -#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ -#define TY_ITYP_VER_A7 0x1 -#define TY_ITYP_VER_A53 0x2 -#define TY_ITYP_VER_A57 0x3 - -#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */ -#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ -#define TP_INIT_PER_CLUSTER 4 - -struct ccsr_clk_cluster_group { - struct { - u8 res_00[0x10]; - u32 csr; - u8 res_14[0x20-0x14]; - } hwncsr[3]; - u8 res_60[0x80-0x60]; - struct { - u32 gsr; - u8 res_84[0xa0-0x84]; - } pllngsr[3]; - u8 res_e0[0x100-0xe0]; -}; - -struct ccsr_clk_ctrl { - struct { - u32 csr; /* core cluster n clock control status */ - u8 res_04[0x20-0x04]; - } clkcncsr[8]; -}; - -struct ccsr_reset { - u32 rstcr; /* 0x000 */ - u32 rstcrsp; /* 0x004 */ - u8 res_008[0x10-0x08]; /* 0x008 */ - u32 rstrqmr1; /* 0x010 */ - u32 rstrqmr2; /* 0x014 */ - u32 rstrqsr1; /* 0x018 */ - u32 rstrqsr2; /* 0x01c */ - u32 rstrqwdtmrl; /* 0x020 */ - u32 rstrqwdtmru; /* 0x024 */ - u8 res_028[0x30-0x28]; /* 0x028 */ - u32 rstrqwdtsrl; /* 0x030 */ - u32 rstrqwdtsru; /* 0x034 */ - u8 res_038[0x60-0x38]; /* 0x038 */ - u32 brrl; /* 0x060 */ - u32 brru; /* 0x064 */ - u8 res_068[0x80-0x68]; /* 0x068 */ - u32 pirset; /* 0x080 */ - u32 pirclr; /* 0x084 */ - u8 res_088[0x90-0x88]; /* 0x088 */ - u32 brcorenbr; /* 0x090 */ - u8 res_094[0x100-0x94]; /* 0x094 */ - u32 rcw_reqr; /* 0x100 */ - u32 rcw_completion; /* 0x104 */ - u8 res_108[0x110-0x108]; /* 0x108 */ - u32 pbi_reqr; /* 0x110 */ - u32 pbi_completion; /* 0x114 */ - u8 res_118[0xa00-0x118]; /* 0x118 */ - u32 qmbm_warmrst; /* 0xa00 */ - u32 soc_warmrst; /* 0xa04 */ - u8 res_a08[0xbf8-0xa08]; /* 0xa08 */ - u32 ip_rev1; /* 0xbf8 */ - u32 ip_rev2; /* 0xbfc */ -}; -#endif /* __ARCH_FSL_LSCH3_IMMAP_H */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h b/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h deleted file mode 100644 index 8f00535..0000000 --- a/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - */ - -#ifndef __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_ -#define __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_ - -#define I2C_QUIRK_REG /* enable 8-bit driver */ - -#endif /* __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h b/arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h deleted file mode 100644 index 5c94530..0000000 --- a/arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - */ -#ifndef __FSL_STREAM_ID_H -#define __FSL_STREAM_ID_H - -/* Stream IDs on ls2085a devices are not hardwired and are - * programmed by sw. There are a limited number of stream IDs - * available, and the partitioning of them is scenario dependent. - * This header defines the partitioning between legacy, PCI, - * and DPAA2 devices. - * - * This partitiong can be customized in this file depending - * on the specific hardware config-- e.g. perhaps not all - * PEX controllers are in use. - * - * On LS2085 stream IDs are programmed in AMQ registers (32-bits) for - * each of the different bus masters. The relationship between - * the AMQ registers and stream IDs is defined in the table below: - * AMQ bit streamID bit - * --------------------------- - * PL[18] 9 - * BMT[17] 8 - * VA[16] 7 - * [15] - - * ICID[14:7] - - * ICID[6:0] 6-0 - * ---------------------------- - */ - -#define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */ -#define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */ - -#define FSL_INVALID_STREAM_ID 0 - -#define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK) - -/* legacy devices */ -#define FSL_USB1_STREAM_ID 1 -#define FSL_USB2_STREAM_ID 2 -#define FSL_SDMMC_STREAM_ID 3 -#define FSL_SATA1_STREAM_ID 4 -#define FSL_SATA2_STREAM_ID 5 -#define FSL_DMA_STREAM_ID 6 - -/* PCI - programmed in PEXn_LUT by OS */ -/* 4 IDs per controller */ -#define FSL_PEX1_STREAM_ID_START 7 -#define FSL_PEX1_STREAM_ID_END 10 -#define FSL_PEX2_STREAM_ID_START 11 -#define FSL_PEX2_STREAM_ID_END 14 -#define FSL_PEX3_STREAM_ID_START 15 -#define FSL_PEX3_STREAM_ID_END 18 -#define FSL_PEX4_STREAM_ID_START 19 -#define FSL_PEX4_STREAM_ID_END 22 - -/* DPAA2 - set in MC DPC and alloced by MC */ -#define FSL_DPAA2_STREAM_ID_START 23 -#define FSL_DPAA2_STREAM_ID_END 63 - -#endif diff --git a/arch/arm/include/asm/arch-fsl-lsch3/soc.h b/arch/arm/include/asm/arch-fsl-lsch3/soc.h deleted file mode 100644 index 9a29272..0000000 --- a/arch/arm/include/asm/arch-fsl-lsch3/soc.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright 2015 Freescale Semiconductor - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -struct cpu_type { - char name[15]; - u32 soc_ver; - u32 num_cores; -}; - -#define CPU_TYPE_ENTRY(n, v, nc) \ - { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} - -#define SVR_WO_E 0xFFFFFE -#define SVR_LS2045 0x870120 -#define SVR_LS2080 0x870110 -#define SVR_LS2085 0x870100 - -#define SVR_MAJ(svr) (((svr) >> 4) & 0xf) -#define SVR_MIN(svr) (((svr) >> 0) & 0xf) -#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) -#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) - -void fsl_lsch3_early_init_f(void); -void cpu_name(char *name); - diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h index 22fff02..435fc45 100644 --- a/arch/arm/include/asm/config.h +++ b/arch/arm/include/asm/config.h @@ -15,14 +15,11 @@ #define CONFIG_STATIC_RELA #endif -#ifdef CONFIG_FSL_LSCH3 -#include -#endif - #if defined(CONFIG_LS102XA) || \ defined(CONFIG_CPU_PXA27X) || \ defined(CONFIG_CPU_MONAHANS) || \ - defined(CONFIG_CPU_PXA25X) + defined(CONFIG_CPU_PXA25X) || \ + defined(CONFIG_FSL_LAYERSCAPE) #include #endif -- cgit v1.1 From 8281c58fd46d095e28e60b2fb0ce84b4444896f8 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Mon, 26 Oct 2015 19:47:51 +0800 Subject: armv8/fsl_lsch2: Add fsl_lsch2 SoC Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang Signed-off-by: Hou Zhiqiang Signed-off-by: Mingkai Hu Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 5 + arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 | 10 + arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 13 + .../cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c | 117 +++++ .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 137 +++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 17 + arch/arm/include/asm/arch-fsl-layerscape/config.h | 47 ++ arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 64 +++ .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 91 ++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 555 +++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/ns_access.h | 158 ++++++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 6 + arch/arm/include/asm/armv8/mmu.h | 1 + 13 files changed, 1221 insertions(+) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/ns_access.h (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index ccb3aa5..4754e59 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -14,6 +14,11 @@ obj-$(CONFIG_SPL) += spl.o ifneq ($(CONFIG_FSL_LSCH3),) obj-y += fsl_lsch3_speed.o obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o +else +ifneq ($(CONFIG_FSL_LSCH2),) +obj-y += fsl_lsch2_speed.o +obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o +endif endif ifneq ($(CONFIG_LS2085A),) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 new file mode 100644 index 0000000..a6ef830 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 @@ -0,0 +1,10 @@ +# +# Copyright 2015 Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +Freescale LayerScape with Chassis Generation 2 + +This architecture supports Freescale ARMv8 SoCs with Chassis generation 2, +for example LS1043A. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index be7442d..fe9d982 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -180,6 +180,8 @@ static inline void early_mmu_setup(void) set_pgtable_table(level1_table0, CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1, level2_table1); +#elif defined(CONFIG_FSL_LSCH2) + set_pgtable_table(level1_table0, 1, level2_table1); #endif /* Find the table and fill in the block entries */ for (i = 0; i < ARRAY_SIZE(early_mmu_table); i++) { @@ -215,6 +217,9 @@ static inline void early_mmu_setup(void) * * For LSCH3: * Level 2 table 1 contains 512 entries for each 2MB from 32GB to 33GB. + * For LSCH2: + * Level 2 table 1 contains 512 entries for each 2MB from 1GB to 2GB. + * Level 2 table 2 contains 512 entries for each 2MB from 20GB to 21GB. */ static inline void final_mmu_setup(void) { @@ -225,6 +230,9 @@ static inline void final_mmu_setup(void) u64 *level2_table0 = (u64 *)(gd->arch.tlb_addr + 0x3000); #ifdef CONFIG_FSL_LSCH3 u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000); +#elif defined(CONFIG_FSL_LSCH2) + u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000); + u64 *level2_table2 = (u64 *)(gd->arch.tlb_addr + 0x5000); #endif struct table_info table = {level0_table, 0, BLOCK_SIZE_L0}; @@ -239,6 +247,11 @@ static inline void final_mmu_setup(void) set_pgtable_table(level1_table0, CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1, level2_table1); +#elif defined(CONFIG_FSL_LSCH2) + set_pgtable_table(level1_table0, 1, level2_table1); + set_pgtable_table(level1_table0, + CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1, + level2_table2); #endif /* Find the table and fill in the block entries */ diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c new file mode 100644 index 0000000..f7178d1 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c @@ -0,0 +1,117 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_SYS_FSL_SRDS_1 +static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT]; +#endif + +int is_serdes_configured(enum srds_prtcl device) +{ + int ret = 0; + +#ifdef CONFIG_SYS_FSL_SRDS_1 + ret |= serdes1_prtcl_map[device]; +#endif + + return !!ret; +} + +int serdes_get_first_lane(u32 sd, enum srds_prtcl device) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 cfg = gur_in32(&gur->rcwsr[4]); + int i; + + switch (sd) { +#ifdef CONFIG_SYS_FSL_SRDS_1 + case FSL_SRDS_1: + cfg &= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + break; +#endif + default: + printf("invalid SerDes%d\n", sd); + break; + } + + /* Is serdes enabled at all? */ + if (unlikely(cfg == 0)) + return -ENODEV; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_get_prtcl(sd, cfg, i) == device) + return i; + } + + return -ENODEV; +} + +int get_serdes_protocol(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 cfg = gur_in32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; + + return cfg; +} + +const char *serdes_clock_to_string(u32 clock) +{ + switch (clock) { + case SRDS_PLLCR0_RFCK_SEL_100: + return "100"; + case SRDS_PLLCR0_RFCK_SEL_125: + return "125"; + case SRDS_PLLCR0_RFCK_SEL_156_25: + return "156.25"; + default: + return "100"; + } +} + +void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, + u8 serdes_prtcl_map[SERDES_PRCTL_COUNT]) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 cfg; + int lane; + + memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map)); + + cfg = gur_in32(&gur->rcwsr[4]) & sd_prctl_mask; + cfg >>= sd_prctl_shift; + printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); + + if (!is_serdes_prtcl_valid(sd, cfg)) + printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg); + + for (lane = 0; lane < SRDS_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); + + if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT)) + debug("Unknown SerDes lane protocol %d\n", lane_prtcl); + else + serdes_prtcl_map[lane_prtcl] = 1; + } +} + +void fsl_serdes_init(void) +{ +#ifdef CONFIG_SYS_FSL_SRDS_1 + serdes_init(FSL_SRDS_1, + CONFIG_SYS_FSL_SERDES_ADDR, + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK, + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT, + serdes1_prtcl_map); +#endif +} diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c new file mode 100644 index 0000000..ea3723f --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -0,0 +1,137 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 +#endif + +void get_sys_info(struct sys_info *sys_info) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); +#ifdef CONFIG_FSL_IFC + struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; + u32 ccr; +#endif + struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR); + unsigned int cpu; + const u8 core_cplx_pll[8] = { + [0] = 0, /* CC1 PPL / 1 */ + [1] = 0, /* CC1 PPL / 2 */ + [4] = 1, /* CC2 PPL / 1 */ + [5] = 1, /* CC2 PPL / 2 */ + }; + + const u8 core_cplx_pll_div[8] = { + [0] = 1, /* CC1 PPL / 1 */ + [1] = 2, /* CC1 PPL / 2 */ + [4] = 1, /* CC2 PPL / 1 */ + [5] = 2, /* CC2 PPL / 2 */ + }; + + uint i; + uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; + uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; + unsigned long sysclk = CONFIG_SYS_CLK_FREQ; + + sys_info->freq_systembus = sysclk; +#ifdef CONFIG_DDR_CLK_FREQ + sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; +#else + sys_info->freq_ddrbus = sysclk; +#endif + + sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> + FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) & + FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK; + sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> + FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) & + FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK; + + for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { + ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff; + if (ratio[i] > 4) + freq_c_pll[i] = sysclk * ratio[i]; + else + freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; + } + + for (cpu = 0; cpu < CONFIG_MAX_CPUS; cpu++) { + u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27) + & 0xf; + u32 cplx_pll = core_cplx_pll[c_pll_sel]; + + sys_info->freq_processor[cpu] = + freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; + } + +#define HWA_CGA_M1_CLK_SEL 0xe0000000 +#define HWA_CGA_M1_CLK_SHIFT 29 + +#define HWA_CGA_M2_CLK_SEL 0x00000007 +#define HWA_CGA_M2_CLK_SHIFT 0 + +#if defined(CONFIG_FSL_IFC) + ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr); + ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; + + sys_info->freq_localbus = sys_info->freq_systembus / ccr; +#endif +} + +int get_clocks(void) +{ + struct sys_info sys_info; + + get_sys_info(&sys_info); + gd->cpu_clk = sys_info.freq_processor[0]; + gd->bus_clk = sys_info.freq_systembus; + gd->mem_clk = sys_info.freq_ddrbus; + + if (gd->cpu_clk != 0) + return 0; + else + return 1; +} + +ulong get_bus_freq(ulong dummy) +{ + return gd->bus_clk; +} + +ulong get_ddr_freq(ulong dummy) +{ + return gd->mem_clk; +} + +int get_serial_clock(void) +{ + return gd->bus_clk; +} + +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_I2C_CLK: + return get_bus_freq(0); + case MXC_DSPI_CLK: + return get_bus_freq(0); + case MXC_UART_CLK: + return get_bus_freq(0); + default: + printf("Unsupported clock\n"); + } + return 0; +} diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 73e48a7..637853d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -76,6 +76,23 @@ void fsl_lsch3_early_init_f(void) init_early_memctl_regs(); /* tighten IFC timing */ erratum_a009203(); } + +#elif defined(CONFIG_LS1043A) +void fsl_lsch2_early_init_f(void) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + +#ifdef CONFIG_FSL_IFC + init_early_memctl_regs(); /* tighten IFC timing */ +#endif + + /* + * Enable snoop requests and DVM message requests for + * Slave insterface S4 (A53 core cluster) + */ + out_le32(&cci->slave[4].snoop_ctrl, + CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); +} #endif #ifdef CONFIG_BOARD_LATE_INIT diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index dd7203f..87bb937 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -89,6 +89,53 @@ #define CONFIG_SYS_FSL_ERRATUM_A008514 #define CONFIG_SYS_FSL_ERRATUM_A008585 #define CONFIG_SYS_FSL_ERRATUM_A008751 +#elif defined(CONFIG_LS1043A) +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 7 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000 +#define CONFIG_SYS_FSL_SEC_COMPAT 5 +#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */ +#define CONFIG_SYS_FSL_DDR_BE +#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE + +#define CONFIG_SYS_FSL_CCSR_GUR_BE +#define CONFIG_SYS_FSL_CCSR_SCFG_BE +#define CONFIG_SYS_FSL_IFC_BE +#define CONFIG_SYS_FSL_ESDHC_BE +#define CONFIG_SYS_FSL_WDOG_BE +#define CONFIG_SYS_FSL_DSPI_BE +#define CONFIG_SYS_FSL_QSPI_BE + +#define QE_MURAM_SIZE 0x6000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 + +#define SRDS_MAX_LANES 4 +#define CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" + +#define CONFIG_SYS_FSL_SFP_VER_3_2 +#define CONFIG_SYS_FSL_SNVS_LE +#define CONFIG_SYS_FSL_SEC_LE +#define CONFIG_SYS_FSL_SFP_BE +#define CONFIG_SYS_FSL_SRK_LE +#define CONFIG_KEY_REVOCATION + +/* SMMU Defintions */ +#define SMMU_BASE 0x09000000 + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x01401000 +#define GICC_BASE 0x01402000 + #else #error SoC not defined #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index b7b8e5d..2903996 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -11,6 +11,7 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LS2085, LS2085, 8), CPU_TYPE_ENTRY(LS2080, LS2080, 8), CPU_TYPE_ENTRY(LS2045, LS2045, 4), + CPU_TYPE_ENTRY(LS1043, LS1043, 4), }; #ifndef CONFIG_SYS_DCACHE_OFF @@ -73,6 +74,28 @@ static struct cpu_type cpu_type_list[] = { #define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 #define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 +#elif defined(CONFIG_FSL_LSCH2) +#define CONFIG_SYS_FSL_BOOTROM_BASE 0x0 +#define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000 +#define CONFIG_SYS_FSL_CCSR_BASE 0x1000000 +#define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000 +#define CONFIG_SYS_FSL_DCSR_BASE 0x20000000 +#define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000 +#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 +#define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000 +#define CONFIG_SYS_FSL_IFC_BASE 0x60000000 +#define CONFIG_SYS_FSL_IFC_SIZE 0x20000000 +#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 +#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 +#define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000 +#define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000 +#define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000 +#define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */ +#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000 +#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 +#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 +#define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000 +#define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */ #endif struct sys_mmu_table { @@ -110,6 +133,19 @@ static const struct sys_mmu_table early_mmu_table[] = { CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, +#elif defined(CONFIG_FSL_LSCH2) + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, + CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, #endif }; @@ -156,6 +192,34 @@ static const struct sys_mmu_table final_mmu_table[] = { CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, +#elif defined(CONFIG_FSL_LSCH2) + { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, + CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, + CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, + CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, + CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, + CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, + CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, + PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, + { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, + CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, + CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, + CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, + CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, + CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE }, #endif }; #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index 730c2b2..e1043b5 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -55,6 +55,92 @@ enum srds { FSL_SRDS_1 = 0, FSL_SRDS_2 = 1, }; +#elif defined(CONFIG_LS1043A) +enum srds_prtcl { + NONE = 0, + PCIE1, + PCIE2, + PCIE3, + PCIE4, + SATA1, + SATA2, + SRIO1, + SRIO2, + SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, + SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, + SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC10, + SGMII_FM2_DTSEC1, + SGMII_FM2_DTSEC2, + SGMII_FM2_DTSEC3, + SGMII_FM2_DTSEC4, + SGMII_FM2_DTSEC5, + SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC10, + SGMII_TSEC1, + SGMII_TSEC2, + SGMII_TSEC3, + SGMII_TSEC4, + XAUI_FM1, + XAUI_FM2, + AURORA, + CPRI1, + CPRI2, + CPRI3, + CPRI4, + CPRI5, + CPRI6, + CPRI7, + CPRI8, + XAUI_FM1_MAC9, + XAUI_FM1_MAC10, + XAUI_FM2_MAC9, + XAUI_FM2_MAC10, + HIGIG_FM1_MAC9, + HIGIG_FM1_MAC10, + HIGIG_FM2_MAC9, + HIGIG_FM2_MAC10, + QSGMII_FM1_A, /* A indicates MACs 1,2,5,6 */ + QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */ + QSGMII_FM2_A, + QSGMII_FM2_B, + XFI_FM1_MAC1, + XFI_FM1_MAC2, + XFI_FM1_MAC9, + XFI_FM1_MAC10, + XFI_FM2_MAC9, + XFI_FM2_MAC10, + INTERLAKEN, + QSGMII_SW1_A, /* Indicates ports on L2 Switch */ + QSGMII_SW1_B, + SGMII_2500_FM1_DTSEC1, + SGMII_2500_FM1_DTSEC2, + SGMII_2500_FM1_DTSEC3, + SGMII_2500_FM1_DTSEC4, + SGMII_2500_FM1_DTSEC5, + SGMII_2500_FM1_DTSEC6, + SGMII_2500_FM1_DTSEC9, + SGMII_2500_FM1_DTSEC10, + SGMII_2500_FM2_DTSEC1, + SGMII_2500_FM2_DTSEC2, + SGMII_2500_FM2_DTSEC3, + SGMII_2500_FM2_DTSEC4, + SGMII_2500_FM2_DTSEC5, + SGMII_2500_FM2_DTSEC6, + SGMII_2500_FM2_DTSEC9, + SGMII_2500_FM2_DTSEC10, + SERDES_PRCTL_COUNT +}; + +enum srds { + FSL_SRDS_1 = 0, +}; + #endif int is_serdes_configured(enum srds_prtcl device); @@ -63,4 +149,9 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device); enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); int is_serdes_prtcl_valid(int serdes, u32 prtcl); +#ifdef CONFIG_LS1043A +const char *serdes_clock_to_string(u32 clock); +int get_serdes_protocol(void); +#endif + #endif /* __FSL_SERDES_H__ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h new file mode 100644 index 0000000..d941437 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -0,0 +1,555 @@ +/* + * Copyright 2013-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_FSL_LSCH2_IMMAP_H__ +#define __ARCH_FSL_LSCH2_IMMAP_H__ + +#include + +#define CONFIG_SYS_IMMR 0x01000000 +#define CONFIG_SYS_DCSRBAR 0x20000000 +#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000) + +#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) +#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000) +#define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000) +#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) +#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) +#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) +#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) +#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0) +#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) +#define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000) +#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) +#define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) +#define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) +#define CONFIG_SYS_FSL_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) +#define CONFIG_SYS_FSL_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) +#define CONFIG_SYS_FSL_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) +#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) +#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) +#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) +#define CONFIG_SYS_SNVS_ADDR (CONFIG_SYS_IMMR + 0xe90000) +#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) + +#define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000 + +#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) +#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000) +#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000) +#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x011b0000) + +#define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000) + +#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) +#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) + +#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) + +#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) + +#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL +#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL +#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL + +/* TZ Address Space Controller Definitions */ +#define TZASC1_BASE 0x01100000 /* as per CCSR map. */ +#define TZASC2_BASE 0x01110000 /* as per CCSR map. */ +#define TZASC3_BASE 0x01120000 /* as per CCSR map. */ +#define TZASC4_BASE 0x01130000 /* as per CCSR map. */ +#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) +#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) +#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) +#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) +#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) +#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) +#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) +#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) +#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) + +#define TP_ITYP_AV 0x00000001 /* Initiator available */ +#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ +#define TP_ITYP_TYPE_ARM 0x0 +#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ +#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ +#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ +#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ +#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ +#define TY_ITYP_VER_A7 0x1 +#define TY_ITYP_VER_A53 0x2 +#define TY_ITYP_VER_A57 0x3 + +#define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */ +#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ +#define TP_INIT_PER_CLUSTER 4 + +/* + * Define default values for some CCSR macros to make header files cleaner* + * + * To completely disable CCSR relocation in a board header file, define + * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS + * to a value that is the same as CONFIG_SYS_CCSRBAR. + */ + +#ifdef CONFIG_SYS_CCSRBAR_PHYS +#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \ +CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." +#endif + +#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#undef CONFIG_SYS_CCSRBAR_PHYS_LOW +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#endif + +#ifndef CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT +#endif + +#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#endif + +#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT +#endif + +#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ + CONFIG_SYS_CCSRBAR_PHYS_LOW) + +struct sys_info { + unsigned long freq_processor[CONFIG_MAX_CPUS]; + unsigned long freq_systembus; + unsigned long freq_ddrbus; + unsigned long freq_localbus; + unsigned long freq_sdhc; +#ifdef CONFIG_SYS_DPAA_FMAN + unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; +#endif + unsigned long freq_qman; +}; + +#define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000 +#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0xa88000 +#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0xa89000 +#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0xa8a000 +#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0xa8b000 +#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0xa8c000 +#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0xa8d000 + +#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000 +#define CONFIG_SYS_FSL_FM1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET) +#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) + +/* Device Configuration and Pin Control */ +struct ccsr_gur { + u32 porsr1; /* POR status 1 */ +#define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000 + u32 porsr2; /* POR status 2 */ + u8 res_008[0x20-0x8]; + u32 gpporcr1; /* General-purpose POR configuration */ + u32 gpporcr2; +#define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT 25 +#define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK 0x1F +#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT 20 +#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK 0x1F + u32 dcfg_fusesr; /* Fuse status register */ + u8 res_02c[0x70-0x2c]; + u32 devdisr; /* Device disable control */ +#define FSL_CHASSIS2_DEVDISR2_DTSEC1_1 0x80000000 +#define FSL_CHASSIS2_DEVDISR2_DTSEC1_2 0x40000000 +#define FSL_CHASSIS2_DEVDISR2_DTSEC1_3 0x20000000 +#define FSL_CHASSIS2_DEVDISR2_DTSEC1_4 0x10000000 +#define FSL_CHASSIS2_DEVDISR2_DTSEC1_5 0x08000000 +#define FSL_CHASSIS2_DEVDISR2_DTSEC1_6 0x04000000 +#define FSL_CHASSIS2_DEVDISR2_DTSEC1_9 0x00800000 +#define FSL_CHASSIS2_DEVDISR2_DTSEC1_10 0x00400000 +#define FSL_CHASSIS2_DEVDISR2_10GEC1_1 0x00800000 +#define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x00400000 +#define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x80000000 +#define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x40000000 + u32 devdisr2; /* Device disable control 2 */ + u32 devdisr3; /* Device disable control 3 */ + u32 devdisr4; /* Device disable control 4 */ + u32 devdisr5; /* Device disable control 5 */ + u32 devdisr6; /* Device disable control 6 */ + u32 devdisr7; /* Device disable control 7 */ + u8 res_08c[0x94-0x8c]; + u32 coredisru; /* uppper portion for support of 64 cores */ + u32 coredisrl; /* lower portion for support of 64 cores */ + u8 res_09c[0xa0-0x9c]; + u32 pvr; /* Processor version */ + u32 svr; /* System version */ + u32 mvr; /* Manufacturing version */ + u8 res_0ac[0xb0-0xac]; + u32 rstcr; /* Reset control */ + u32 rstrqpblsr; /* Reset request preboot loader status */ + u8 res_0b8[0xc0-0xb8]; + u32 rstrqmr1; /* Reset request mask */ + u8 res_0c4[0xc8-0xc4]; + u32 rstrqsr1; /* Reset request status */ + u8 res_0cc[0xd4-0xcc]; + u32 rstrqwdtmrl; /* Reset request WDT mask */ + u8 res_0d8[0xdc-0xd8]; + u32 rstrqwdtsrl; /* Reset request WDT status */ + u8 res_0e0[0xe4-0xe0]; + u32 brrl; /* Boot release */ + u8 res_0e8[0x100-0xe8]; + u32 rcwsr[16]; /* Reset control word status */ +#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25 +#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f +#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16 +#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f +#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000 +#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16 + u8 res_140[0x200-0x140]; + u32 scratchrw[4]; /* Scratch Read/Write */ + u8 res_210[0x300-0x210]; + u32 scratchw1r[4]; /* Scratch Read (Write once) */ + u8 res_310[0x400-0x310]; + u32 crstsr[12]; + u8 res_430[0x500-0x430]; + + /* PCI Express n Logical I/O Device Number register */ + u32 dcfg_ccsr_pex1liodnr; + u32 dcfg_ccsr_pex2liodnr; + u32 dcfg_ccsr_pex3liodnr; + u32 dcfg_ccsr_pex4liodnr; + /* RIO n Logical I/O Device Number register */ + u32 dcfg_ccsr_rio1liodnr; + u32 dcfg_ccsr_rio2liodnr; + u32 dcfg_ccsr_rio3liodnr; + u32 dcfg_ccsr_rio4liodnr; + /* USB Logical I/O Device Number register */ + u32 dcfg_ccsr_usb1liodnr; + u32 dcfg_ccsr_usb2liodnr; + u32 dcfg_ccsr_usb3liodnr; + u32 dcfg_ccsr_usb4liodnr; + /* SD/MMC Logical I/O Device Number register */ + u32 dcfg_ccsr_sdmmc1liodnr; + u32 dcfg_ccsr_sdmmc2liodnr; + u32 dcfg_ccsr_sdmmc3liodnr; + u32 dcfg_ccsr_sdmmc4liodnr; + /* RIO Message Unit Logical I/O Device Number register */ + u32 dcfg_ccsr_riomaintliodnr; + + u8 res_544[0x550-0x544]; + u32 sataliodnr[4]; + u8 res_560[0x570-0x560]; + + u32 dcfg_ccsr_misc1liodnr; + u32 dcfg_ccsr_misc2liodnr; + u32 dcfg_ccsr_misc3liodnr; + u32 dcfg_ccsr_misc4liodnr; + u32 dcfg_ccsr_dma1liodnr; + u32 dcfg_ccsr_dma2liodnr; + u32 dcfg_ccsr_dma3liodnr; + u32 dcfg_ccsr_dma4liodnr; + u32 dcfg_ccsr_spare1liodnr; + u32 dcfg_ccsr_spare2liodnr; + u32 dcfg_ccsr_spare3liodnr; + u32 dcfg_ccsr_spare4liodnr; + u8 res_5a0[0x600-0x5a0]; + u32 dcfg_ccsr_pblsr; + + u32 pamubypenr; + u32 dmacr1; + + u8 res_60c[0x610-0x60c]; + u32 dcfg_ccsr_gensr1; + u32 dcfg_ccsr_gensr2; + u32 dcfg_ccsr_gensr3; + u32 dcfg_ccsr_gensr4; + u32 dcfg_ccsr_gencr1; + u32 dcfg_ccsr_gencr2; + u32 dcfg_ccsr_gencr3; + u32 dcfg_ccsr_gencr4; + u32 dcfg_ccsr_gencr5; + u32 dcfg_ccsr_gencr6; + u32 dcfg_ccsr_gencr7; + u8 res_63c[0x658-0x63c]; + u32 dcfg_ccsr_cgensr1; + u32 dcfg_ccsr_cgensr0; + u8 res_660[0x678-0x660]; + u32 dcfg_ccsr_cgencr1; + + u32 dcfg_ccsr_cgencr0; + u8 res_680[0x700-0x680]; + u32 dcfg_ccsr_sriopstecr; + u32 dcfg_ccsr_dcsrcr; + + u8 res_708[0x740-0x708]; /* add more registers when needed */ + u32 tp_ityp[64]; /* Topology Initiator Type Register */ + struct { + u32 upper; + u32 lower; + } tp_cluster[16]; + u8 res_8c0[0xa00-0x8c0]; /* add more registers when needed */ + u32 dcfg_ccsr_qmbm_warmrst; + u8 res_a04[0xa20-0xa04]; /* add more registers when needed */ + u32 dcfg_ccsr_reserved0; + u32 dcfg_ccsr_reserved1; +}; + +#define SCFG_QSPI_CLKSEL 0x40100000 +#define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000 +#define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001 +#define SCFG_USBDRVVBUS_SELCR_USB3 0x00000002 +#define SCFG_USBPWRFAULT_INACTIVE 0x00000000 +#define SCFG_USBPWRFAULT_SHARED 0x00000001 +#define SCFG_USBPWRFAULT_DEDICATED 0x00000002 +#define SCFG_USBPWRFAULT_USB3_SHIFT 4 +#define SCFG_USBPWRFAULT_USB2_SHIFT 2 +#define SCFG_USBPWRFAULT_USB1_SHIFT 0 + +#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 +#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 + +/* Supplemental Configuration Unit */ +struct ccsr_scfg { + u8 res_000[0x100-0x000]; + u32 usb2_icid; + u32 usb3_icid; + u8 res_108[0x114-0x108]; + u32 dma_icid; + u32 sata_icid; + u32 usb1_icid; + u32 qe_icid; + u32 sdhc_icid; + u32 edma_icid; + u32 etr_icid; + u32 core_sft_rst[4]; + u8 res_140[0x158-0x140]; + u32 altcbar; + u32 qspi_cfg; + u8 res_160[0x180-0x160]; + u32 dmamcr; + u8 res_184[0x18c-0x184]; + u32 debug_icid; + u8 res_190[0x1a4-0x190]; + u32 snpcnfgcr; + u8 res_1a8[0x1ac-0x1a8]; + u32 intpcr; + u8 res_1b0[0x204-0x1b0]; + u32 coresrencr; + u8 res_208[0x220-0x208]; + u32 rvbar0_0; + u32 rvbar0_1; + u32 rvbar1_0; + u32 rvbar1_1; + u32 rvbar2_0; + u32 rvbar2_1; + u32 rvbar3_0; + u32 rvbar3_1; + u32 lpmcsr; + u8 res_244[0x400-0x244]; + u32 qspidqscr; + u32 ecgtxcmcr; + u32 sdhciovselcr; + u32 rcwpmuxcr0; + u32 usbdrvvbus_selcr; + u32 usbpwrfault_selcr; + u32 usb_refclk_selcr1; + u32 usb_refclk_selcr2; + u32 usb_refclk_selcr3; + u8 res_424[0x600-0x424]; + u32 scratchrw[4]; + u8 res_610[0x680-0x610]; + u32 corebcr; + u8 res_684[0x1000-0x684]; + u32 pex1msiir; + u32 pex1msir; + u8 res_1008[0x2000-0x1008]; + u32 pex2; + u32 pex2msir; + u8 res_2008[0x3000-0x2008]; + u32 pex3msiir; + u32 pex3msir; +}; + +/* Clocking */ +struct ccsr_clk { + struct { + u32 clkcncsr; /* core cluster n clock control status */ + u8 res_004[0x0c]; + u32 clkcghwacsr; /* Clock generator n hardware accelerator */ + u8 res_014[0x0c]; + } clkcsr[4]; + u8 res_040[0x780]; /* 0x100 */ + struct { + u32 pllcngsr; + u8 res_804[0x1c]; + } pllcgsr[2]; + u8 res_840[0x1c0]; + u32 clkpcsr; /* 0xa00 Platform clock domain control/status */ + u8 res_a04[0x1fc]; + u32 pllpgsr; /* 0xc00 Platform PLL General Status */ + u8 res_c04[0x1c]; + u32 plldgsr; /* 0xc20 DDR PLL General Status */ + u8 res_c24[0x3dc]; +}; + +/* System Counter */ +struct sctr_regs { + u32 cntcr; + u32 cntsr; + u32 cntcv1; + u32 cntcv2; + u32 resv1[4]; + u32 cntfid0; + u32 cntfid1; + u32 resv2[1002]; + u32 counterid[12]; +}; + +#define SRDS_MAX_LANES 4 +struct ccsr_serdes { + struct { + u32 rstctl; /* Reset Control Register */ +#define SRDS_RSTCTL_RST 0x80000000 +#define SRDS_RSTCTL_RSTDONE 0x40000000 +#define SRDS_RSTCTL_RSTERR 0x20000000 +#define SRDS_RSTCTL_SWRST 0x10000000 +#define SRDS_RSTCTL_SDEN 0x00000020 +#define SRDS_RSTCTL_SDRST_B 0x00000040 +#define SRDS_RSTCTL_PLLRST_B 0x00000080 + u32 pllcr0; /* PLL Control Register 0 */ +#define SRDS_PLLCR0_POFF 0x80000000 +#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 +#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 +#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 +#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 +#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 +#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 +#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 +#define SRDS_PLLCR0_PLL_LCK 0x00800000 +#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 +#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 +#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 +#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 +#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 +#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 +#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 + u32 pllcr1; /* PLL Control Register 1 */ +#define SRDS_PLLCR1_PLL_BWSEL 0x08000000 + u32 res_0c; /* 0x00c */ + u32 pllcr3; + u32 pllcr4; + u8 res_18[0x20-0x18]; + } bank[2]; + u8 res_40[0x90-0x40]; + u32 srdstcalcr; /* 0x90 TX Calibration Control */ + u8 res_94[0xa0-0x94]; + u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ + u8 res_a4[0xb0-0xa4]; + u32 srdsgr0; /* 0xb0 General Register 0 */ + u8 res_b4[0xe0-0xb4]; + u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */ + u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */ + u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */ + u32 srdspccr3; /* 0xec Protocol Converter Config 3 */ + u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */ + u8 res_f4[0x100-0xf4]; + struct { + u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */ + u8 res_104[0x120-0x104]; + } srdslnpssr[4]; + u8 res_180[0x300-0x180]; + u32 srdspexeqcr; + u32 srdspexeqpcr[11]; + u8 res_330[0x400-0x330]; + u32 srdspexapcr; + u8 res_404[0x440-0x404]; + u32 srdspexbpcr; + u8 res_444[0x800-0x444]; + struct { + u32 gcr0; /* 0x800 General Control Register 0 */ + u32 gcr1; /* 0x804 General Control Register 1 */ + u32 gcr2; /* 0x808 General Control Register 2 */ + u32 sscr0; + u32 recr0; /* 0x810 Receive Equalization Control */ + u32 recr1; + u32 tecr0; /* 0x818 Transmit Equalization Control */ + u32 sscr1; + u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ + u8 res_824[0x83c-0x824]; + u32 tcsr3; + } lane[4]; /* Lane A, B, C, D, E, F, G, H */ + u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ +}; + +#define CCI400_CTRLORD_TERM_BARRIER 0x00000008 +#define CCI400_CTRLORD_EN_BARRIER 0 +#define CCI400_SHAORD_NON_SHAREABLE 0x00000002 +#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002 +#define CCI400_SNOOP_REQ_EN 0x00000001 + +/* CCI-400 registers */ +struct ccsr_cci400 { + u32 ctrl_ord; /* Control Override */ + u32 spec_ctrl; /* Speculation Control */ + u32 secure_access; /* Secure Access */ + u32 status; /* Status */ + u32 impr_err; /* Imprecise Error */ + u8 res_14[0x100 - 0x14]; + u32 pmcr; /* Performance Monitor Control */ + u8 res_104[0xfd0 - 0x104]; + u32 pid[8]; /* Peripheral ID */ + u32 cid[4]; /* Component ID */ + struct { + u32 snoop_ctrl; /* Snoop Control */ + u32 sha_ord; /* Shareable Override */ + u8 res_1008[0x1100 - 0x1008]; + u32 rc_qos_ord; /* read channel QoS Value Override */ + u32 wc_qos_ord; /* read channel QoS Value Override */ + u8 res_1108[0x110c - 0x1108]; + u32 qos_ctrl; /* QoS Control */ + u32 max_ot; /* Max OT */ + u8 res_1114[0x1130 - 0x1114]; + u32 target_lat; /* Target Latency */ + u32 latency_regu; /* Latency Regulation */ + u32 qos_range; /* QoS Range */ + u8 res_113c[0x2000 - 0x113c]; + } slave[5]; /* Slave Interface */ + u8 res_6000[0x9004 - 0x6000]; + u32 cycle_counter; /* Cycle counter */ + u32 count_ctrl; /* Count Control */ + u32 overflow_status; /* Overflow Flag Status */ + u8 res_9010[0xa000 - 0x9010]; + struct { + u32 event_select; /* Event Select */ + u32 event_count; /* Event Count */ + u32 counter_ctrl; /* Counter Control */ + u32 overflow_status; /* Overflow Flag Status */ + u8 res_a010[0xb000 - 0xa010]; + } pcounter[4]; /* Performance Counter */ + u8 res_e004[0x10000 - 0xe004]; +}; + +/* MMU 500 */ +#define SMMU_SCR0 (SMMU_BASE + 0x0) +#define SMMU_SCR1 (SMMU_BASE + 0x4) +#define SMMU_SCR2 (SMMU_BASE + 0x8) +#define SMMU_SACR (SMMU_BASE + 0x10) +#define SMMU_IDR0 (SMMU_BASE + 0x20) +#define SMMU_IDR1 (SMMU_BASE + 0x24) + +#define SMMU_NSCR0 (SMMU_BASE + 0x400) +#define SMMU_NSCR2 (SMMU_BASE + 0x408) +#define SMMU_NSACR (SMMU_BASE + 0x410) + +#define SCR0_CLIENTPD_MASK 0x00000001 +#define SCR0_USFCFG_MASK 0x00000400 + +#endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h new file mode 100644 index 0000000..a3ccdb0 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h @@ -0,0 +1,158 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_NS_ACCESS_H_ +#define __FSL_NS_ACCESS_H_ + +enum csu_cslx_ind { + CSU_CSLX_PCIE2_IO = 0, + CSU_CSLX_PCIE1_IO, + CSU_CSLX_MG2TPR_IP, + CSU_CSLX_IFC_MEM, + CSU_CSLX_OCRAM, + CSU_CSLX_GIC, + CSU_CSLX_PCIE1, + CSU_CSLX_OCRAM2, + CSU_CSLX_QSPI_MEM, + CSU_CSLX_PCIE2, + CSU_CSLX_SATA, + CSU_CSLX_USB1, + CSU_CSLX_QM_BM_SWPORTAL, + CSU_CSLX_PCIE3 = 16, + CSU_CSLX_PCIE3_IO, + CSU_CSLX_USB3 = 20, + CSU_CSLX_USB2, + CSU_CSLX_SERDES = 32, + CSU_CSLX_QDMA, + CSU_CSLX_LPUART2, + CSU_CSLX_LPUART1, + CSU_CSLX_LPUART4, + CSU_CSLX_LPUART3, + CSU_CSLX_LPUART6, + CSU_CSLX_LPUART5, + CSU_CSLX_DSPI1 = 41, + CSU_CSLX_QSPI, + CSU_CSLX_ESDHC, + CSU_CSLX_IFC = 45, + CSU_CSLX_I2C1, + CSU_CSLX_I2C3 = 48, + CSU_CSLX_I2C2, + CSU_CSLX_DUART2 = 50, + CSU_CSLX_DUART1, + CSU_CSLX_WDT2, + CSU_CSLX_WDT1, + CSU_CSLX_EDMA, + CSU_CSLX_SYS_CNT, + CSU_CSLX_DMA_MUX2, + CSU_CSLX_DMA_MUX1, + CSU_CSLX_DDR, + CSU_CSLX_QUICC, + CSU_CSLX_DCFG_CCU_RCPM = 60, + CSU_CSLX_SECURE_BOOTROM, + CSU_CSLX_SFP, + CSU_CSLX_TMU, + CSU_CSLX_SECURE_MONITOR, + CSU_CSLX_SCFG, + CSU_CSLX_FM = 66, + CSU_CSLX_SEC5_5, + CSU_CSLX_BM, + CSU_CSLX_QM, + CSU_CSLX_GPIO2 = 70, + CSU_CSLX_GPIO1, + CSU_CSLX_GPIO4, + CSU_CSLX_GPIO3, + CSU_CSLX_PLATFORM_CONT, + CSU_CSLX_CSU, + CSU_CSLX_IIC4 = 77, + CSU_CSLX_WDT4, + CSU_CSLX_WDT3, + CSU_CSLX_WDT5 = 81, + CSU_CSLX_FTM2 = 86, + CSU_CSLX_FTM1, + CSU_CSLX_FTM4, + CSU_CSLX_FTM3, + CSU_CSLX_FTM6 = 90, + CSU_CSLX_FTM5, + CSU_CSLX_FTM8, + CSU_CSLX_FTM7, + CSU_CSLX_DSCR = 121, +}; + +static struct csu_ns_dev ns_dev[] = { + {CSU_CSLX_PCIE2_IO, CSU_ALL_RW}, + {CSU_CSLX_PCIE1_IO, CSU_ALL_RW}, + {CSU_CSLX_MG2TPR_IP, CSU_ALL_RW}, + {CSU_CSLX_IFC_MEM, CSU_ALL_RW}, + {CSU_CSLX_OCRAM, CSU_ALL_RW}, + {CSU_CSLX_GIC, CSU_ALL_RW}, + {CSU_CSLX_PCIE1, CSU_ALL_RW}, + {CSU_CSLX_OCRAM2, CSU_ALL_RW}, + {CSU_CSLX_QSPI_MEM, CSU_ALL_RW}, + {CSU_CSLX_PCIE2, CSU_ALL_RW}, + {CSU_CSLX_SATA, CSU_ALL_RW}, + {CSU_CSLX_USB1, CSU_ALL_RW}, + {CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW}, + {CSU_CSLX_PCIE3, CSU_ALL_RW}, + {CSU_CSLX_PCIE3_IO, CSU_ALL_RW}, + {CSU_CSLX_USB3, CSU_ALL_RW}, + {CSU_CSLX_USB2, CSU_ALL_RW}, + {CSU_CSLX_SERDES, CSU_ALL_RW}, + {CSU_CSLX_QDMA, CSU_ALL_RW}, + {CSU_CSLX_LPUART2, CSU_ALL_RW}, + {CSU_CSLX_LPUART1, CSU_ALL_RW}, + {CSU_CSLX_LPUART4, CSU_ALL_RW}, + {CSU_CSLX_LPUART3, CSU_ALL_RW}, + {CSU_CSLX_LPUART6, CSU_ALL_RW}, + {CSU_CSLX_LPUART5, CSU_ALL_RW}, + {CSU_CSLX_DSPI1, CSU_ALL_RW}, + {CSU_CSLX_QSPI, CSU_ALL_RW}, + {CSU_CSLX_ESDHC, CSU_ALL_RW}, + {CSU_CSLX_IFC, CSU_ALL_RW}, + {CSU_CSLX_I2C1, CSU_ALL_RW}, + {CSU_CSLX_I2C3, CSU_ALL_RW}, + {CSU_CSLX_I2C2, CSU_ALL_RW}, + {CSU_CSLX_DUART2, CSU_ALL_RW}, + {CSU_CSLX_DUART1, CSU_ALL_RW}, + {CSU_CSLX_WDT2, CSU_ALL_RW}, + {CSU_CSLX_WDT1, CSU_ALL_RW}, + {CSU_CSLX_EDMA, CSU_ALL_RW}, + {CSU_CSLX_SYS_CNT, CSU_ALL_RW}, + {CSU_CSLX_DMA_MUX2, CSU_ALL_RW}, + {CSU_CSLX_DMA_MUX1, CSU_ALL_RW}, + {CSU_CSLX_DDR, CSU_ALL_RW}, + {CSU_CSLX_QUICC, CSU_ALL_RW}, + {CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW}, + {CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW}, + {CSU_CSLX_SFP, CSU_ALL_RW}, + {CSU_CSLX_TMU, CSU_ALL_RW}, + {CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW}, + {CSU_CSLX_SCFG, CSU_ALL_RW}, + {CSU_CSLX_FM, CSU_ALL_RW}, + {CSU_CSLX_SEC5_5, CSU_ALL_RW}, + {CSU_CSLX_BM, CSU_ALL_RW}, + {CSU_CSLX_QM, CSU_ALL_RW}, + {CSU_CSLX_GPIO2, CSU_ALL_RW}, + {CSU_CSLX_GPIO1, CSU_ALL_RW}, + {CSU_CSLX_GPIO4, CSU_ALL_RW}, + {CSU_CSLX_GPIO3, CSU_ALL_RW}, + {CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW}, + {CSU_CSLX_CSU, CSU_ALL_RW}, + {CSU_CSLX_IIC4, CSU_ALL_RW}, + {CSU_CSLX_WDT4, CSU_ALL_RW}, + {CSU_CSLX_WDT3, CSU_ALL_RW}, + {CSU_CSLX_WDT5, CSU_ALL_RW}, + {CSU_CSLX_FTM2, CSU_ALL_RW}, + {CSU_CSLX_FTM1, CSU_ALL_RW}, + {CSU_CSLX_FTM4, CSU_ALL_RW}, + {CSU_CSLX_FTM3, CSU_ALL_RW}, + {CSU_CSLX_FTM6, CSU_ALL_RW}, + {CSU_CSLX_FTM5, CSU_ALL_RW}, + {CSU_CSLX_FTM8, CSU_ALL_RW}, + {CSU_CSLX_FTM7, CSU_ALL_RW}, + {CSU_CSLX_DSCR, CSU_ALL_RW}, +}; + +#endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index f131f57..5ed456e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -33,6 +33,7 @@ struct cpu_type { { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} #define SVR_WO_E 0xFFFFFE +#define SVR_LS1043 0x879204 #define SVR_LS2045 0x870120 #define SVR_LS2080 0x870110 #define SVR_LS2085 0x870100 @@ -42,6 +43,11 @@ struct cpu_type { #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) +#ifdef CONFIG_FSL_LSCH3 void fsl_lsch3_early_init_f(void); +#elif defined(CONFIG_FSL_LSCH2) +void fsl_lsch2_early_init_f(void); +#endif + void cpu_name(char *name); #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 587ee39..d8d9af4 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -65,6 +65,7 @@ /* * Section */ +#define PMD_SECT_NS (1 << 5) #define PMD_SECT_NON_SHARE (0 << 8) #define PMD_SECT_OUTER_SHARE (2 << 8) #define PMD_SECT_INNER_SHARE (3 << 8) -- cgit v1.1 From f3a8e2b7d41ca9039e934b5a59899dd57c577fa3 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Mon, 26 Oct 2015 19:47:52 +0800 Subject: armv8/ls1043ardb: Add LS1043ARDB board support LS1043ARDB Specification: ------------------------- Memory subsystem: * 2GByte DDR4 SDRAM (32bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 16 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * XFI 10G port * QSGMII with 4x 1G ports * Two RGMII ports PCIe: * PCIe2 (Lanes C) to mini-PCIe slot * PCIe3 (Lanes D) to PCIe slot USB 3.0: two super speed USB 3.0 type A ports UART: supports two UARTs up to 115200 bps for console Signed-off-by: Hou Zhiqiang Signed-off-by: Li Yang Signed-off-by: Mingkai Hu Signed-off-by: York Sun Signed-off-by: Gong Qianyu --- arch/arm/Kconfig | 7 ++ arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 + arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c | 86 ++++++++++++++++++++++ 3 files changed, 97 insertions(+) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2632099..26c87df 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -627,6 +627,12 @@ config TARGET_LS1021ATWR select CPU_V7 select SUPPORT_SPL +config TARGET_LS1043ARDB + bool "Support ls1043ardb" + select ARM64 + help + Support for Freescale LS1043ARDB platform. + config TARGET_H2200 bool "Support h2200" select CPU_PXA @@ -743,6 +749,7 @@ source "board/freescale/ls2085aqds/Kconfig" source "board/freescale/ls2085ardb/Kconfig" source "board/freescale/ls1021aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" +source "board/freescale/ls1043ardb/Kconfig" source "board/freescale/mx23evk/Kconfig" source "board/freescale/mx25pdk/Kconfig" source "board/freescale/mx28evk/Kconfig" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 4754e59..6fa08c8 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -23,4 +23,8 @@ endif ifneq ($(CONFIG_LS2085A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls2085a_serdes.o +else +ifneq ($(CONFIG_LS1043A),) +obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o +endif endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c new file mode 100644 index 0000000..e54d389 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c @@ -0,0 +1,86 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct serdes_config { + u32 protocol; + u8 lanes[SRDS_MAX_LANES]; +}; + +static struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3} }, + {0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3} }, + {0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3} }, + {0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA1} }, + {0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} }, + {0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} }, + {0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, + PCIE3} }, + {0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} }, + {0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA1} }, + {0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3} }, + {0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA1} }, + {0x7000, {PCIE1, PCIE1, PCIE1, PCIE1} }, + {0x9998, {PCIE1, PCIE2, PCIE3, SATA1} }, + {0x6058, {PCIE1, PCIE1, PCIE2, SATA1} }, + {0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3} }, + {0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3} }, + {0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3} }, + {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, + SGMII_FM1_DTSEC6} }, + {} +}; + +static struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} -- cgit v1.1 From 3ad447292304657aaf9c4a36f7eae34f449c5dbd Mon Sep 17 00:00:00 2001 From: Gong Qianyu Date: Mon, 26 Oct 2015 19:47:53 +0800 Subject: armv8/ls1043ardb: Add nand boot support Signed-off-by: Gong Qianyu Signed-off-by: Hou Zhiqiang Signed-off-by: Shaohui Xie Signed-off-by: Mingkai Hu Reviewed-by: York Sun --- arch/arm/Kconfig | 1 + arch/arm/cpu/armv8/fsl-layerscape/spl.c | 3 +++ 2 files changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 26c87df..10d7c14 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -630,6 +630,7 @@ config TARGET_LS1021ATWR config TARGET_LS1043ARDB bool "Support ls1043ardb" select ARM64 + select SUPPORT_SPL help Support for Freescale LS1043ARDB platform. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 2f30d4b..ba551aa 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -71,6 +71,9 @@ void board_init_f(ulong dummy) /* Clear the BSS */ memset(__bss_start, 0, __bss_end - __bss_start); +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif board_init_r(NULL, 0); } #endif -- cgit v1.1 From e82973414da105c1b14c822f12cb296f69ca2001 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Mon, 26 Oct 2015 19:47:54 +0800 Subject: armv8/ls1043a: Add Fman support Signed-off-by: Hou Zhiqiang Signed-off-by: Shaohui Xie Signed-off-by: Mingkai Hu Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 12 +++++++++++ arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 6 ++++++ .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 23 ++++++++++++++++++++++ 3 files changed, 41 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index fe9d982..0cb0afa 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -274,6 +274,9 @@ static inline void final_mmu_setup(void) flush_dcache_range(gd->arch.tlb_addr, gd->arch.tlb_addr + gd->arch.tlb_size); +#ifdef CONFIG_SYS_DPAA_FMAN + flush_dcache_all(); +#endif /* point TTBR to the new table */ el = current_el(); @@ -432,6 +435,9 @@ int print_cpuinfo(void) printf("\n Bus: %-4s MHz ", strmhz(buf, sysinfo.freq_systembus)); printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus)); +#ifdef CONFIG_SYS_DPAA_FMAN + printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0])); +#endif #ifdef CONFIG_FSL_LSCH3 printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2)); #endif @@ -468,6 +474,9 @@ int cpu_eth_init(bd_t *bis) #ifdef CONFIG_FSL_MC_ENET error = fsl_mc_ldpaa_init(bis); #endif +#ifdef CONFIG_FMAN_ENET + fm_standard_init(bis); +#endif return error; } @@ -484,6 +493,9 @@ int arch_early_init_r(void) #ifdef CONFIG_SYS_HAS_SERDES fsl_serdes_init(); #endif +#ifdef CONFIG_FMAN_ENET + fman_enet_init(); +#endif return 0; } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 4839e33..47599c1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -18,6 +18,12 @@ #include #endif +int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) +{ + return fdt_setprop_string(blob, offset, "phy-connection-type", + phy_string_for_interface(phyc)); +} + #ifdef CONFIG_MP void ft_fixup_cpu(void *blob) { diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index ea3723f..9d5bbe7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -25,6 +25,9 @@ void get_sys_info(struct sys_info *sys_info) struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; u32 ccr; #endif +#ifdef CONFIG_SYS_DPAA_FMAN + u32 rcw_tmp; +#endif struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR); unsigned int cpu; const u8 core_cplx_pll[8] = { @@ -79,6 +82,26 @@ void get_sys_info(struct sys_info *sys_info) #define HWA_CGA_M1_CLK_SEL 0xe0000000 #define HWA_CGA_M1_CLK_SHIFT 29 +#ifdef CONFIG_SYS_DPAA_FMAN + rcw_tmp = in_be32(&gur->rcwsr[7]); + switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) { + case 2: + sys_info->freq_fman[0] = freq_c_pll[0] / 2; + break; + case 3: + sys_info->freq_fman[0] = freq_c_pll[0] / 3; + break; + case 6: + sys_info->freq_fman[0] = freq_c_pll[1] / 2; + break; + case 7: + sys_info->freq_fman[0] = freq_c_pll[1] / 3; + break; + default: + printf("Error: Unknown FMan1 clock select!\n"); + break; + } +#endif #define HWA_CGA_M2_CLK_SEL 0x00000007 #define HWA_CGA_M2_CLK_SHIFT 0 -- cgit v1.1 From 8ef0d5c43841bccc9112e160e96d6498aa94871b Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Mon, 26 Oct 2015 19:47:55 +0800 Subject: armv8/ls1043ardb: esdhc: Add esdhc support for ls1043ardb This patch adds esdhc support for ls1043ardb. Signed-off-by: Yangbo Lu Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 9d5bbe7..6f6a588 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -25,7 +25,7 @@ void get_sys_info(struct sys_info *sys_info) struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; u32 ccr; #endif -#ifdef CONFIG_SYS_DPAA_FMAN +#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_SYS_DPAA_FMAN) u32 rcw_tmp; #endif struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR); @@ -105,6 +105,11 @@ void get_sys_info(struct sys_info *sys_info) #define HWA_CGA_M2_CLK_SEL 0x00000007 #define HWA_CGA_M2_CLK_SHIFT 0 +#ifdef CONFIG_FSL_ESDHC + rcw_tmp = in_be32(&gur->rcwsr[15]); + rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT; + sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp; +#endif #if defined(CONFIG_FSL_IFC) ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr); @@ -123,6 +128,10 @@ int get_clocks(void) gd->bus_clk = sys_info.freq_systembus; gd->mem_clk = sys_info.freq_ddrbus; +#ifdef CONFIG_FSL_ESDHC + gd->arch.sdhc_clk = sys_info.freq_sdhc; +#endif + if (gd->cpu_clk != 0) return 0; else @@ -139,6 +148,13 @@ ulong get_ddr_freq(ulong dummy) return gd->mem_clk; } +#ifdef CONFIG_FSL_ESDHC +int get_sdhc_freq(ulong dummy) +{ + return gd->arch.sdhc_clk; +} +#endif + int get_serial_clock(void) { return gd->bus_clk; @@ -149,6 +165,10 @@ unsigned int mxc_get_clock(enum mxc_clock clk) switch (clk) { case MXC_I2C_CLK: return get_bus_freq(0); +#if defined(CONFIG_FSL_ESDHC) + case MXC_ESDHC_CLK: + return get_sdhc_freq(0); +#endif case MXC_DSPI_CLK: return get_bus_freq(0); case MXC_UART_CLK: -- cgit v1.1 From 831c068fcfe7d32e48a8b9052a137701b41c7d86 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Mon, 26 Oct 2015 19:47:57 +0800 Subject: armv8/ls1043a: Enable secondary cores After the secondary cores enter U-Boot, use CONFIG_ARMV8_MULTIENTRY to make secondary cores excute in spin loop. Signed-off-by: Hou Zhiqiang Signed-off-by: Mingkai Hu Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- arch/arm/Kconfig | 1 + arch/arm/cpu/armv8/fsl-layerscape/mp.c | 14 ++++++++++++++ 2 files changed, 15 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 10d7c14..3992f69 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -630,6 +630,7 @@ config TARGET_LS1021ATWR config TARGET_LS1043ARDB bool "Support ls1043ardb" select ARM64 + select ARMV8_MULTIENTRY select SUPPORT_SPL help Support for Freescale LS1043ARDB platform. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index 1b13d32..0d600db 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -25,7 +25,11 @@ phys_addr_t determine_mp_bootpg(void) int fsl_layerscape_wake_seconday_cores(void) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); +#ifdef CONFIG_FSL_LSCH3 struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR); +#elif defined(CONFIG_FSL_LSCH2) + struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR); +#endif u32 cores, cpu_up_mask = 1; int i, timeout = 10; u64 *table = get_spin_tbl_addr(); @@ -48,13 +52,23 @@ int fsl_layerscape_wake_seconday_cores(void) printf("Waking secondary cores to start from %lx\n", gd->relocaddr); +#ifdef CONFIG_FSL_LSCH3 gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32)); gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr); gur_out32(&gur->scratchrw[6], 1); asm volatile("dsb st" : : : "memory"); rst->brrl = cores; asm volatile("dsb st" : : : "memory"); +#elif defined(CONFIG_FSL_LSCH2) + scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32)); + scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr); + asm volatile("dsb st" : : : "memory"); + gur_out32(&gur->brrl, cores); + asm volatile("dsb st" : : : "memory"); + /* Bootup online cores */ + scfg_out32(&scfg->corebcr, cores); +#endif /* This is needed as a precautionary measure. * If some code before this has accidentally released the secondary * cores then the pre-bootloader code will trap them in a "wfe" unless -- cgit v1.1 From 4632ad773ed31f4dd6aeb859de148402f8932111 Mon Sep 17 00:00:00 2001 From: tang yuantian Date: Fri, 16 Oct 2015 16:06:05 +0800 Subject: arm: ls1021a: Add sata support on qds and twr board Freescale ARM-based Layerscape LS102xA contain a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls1021aqds and ls1021atwr boards. Signed-off-by: Tang Yuantian Reviewed-by: York Sun --- arch/arm/cpu/armv7/ls102xa/Makefile | 1 + arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c | 42 +++++++++++++++++++++++ arch/arm/include/asm/arch-ls102xa/config.h | 15 ++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 24 +++++++++++++ arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h | 11 ++++++ 5 files changed, 93 insertions(+) create mode 100644 arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c create mode 100644 arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile index 2d55782..2311468 100644 --- a/arch/arm/cpu/armv7/ls102xa/Makefile +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -9,6 +9,7 @@ obj-y += clock.o obj-y += timer.o obj-y += fsl_epu.o +obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o obj-$(CONFIG_SPL) += spl.o diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c new file mode 100644 index 0000000..deeb674 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c @@ -0,0 +1,42 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include + +/* port register default value */ +#define AHCI_PORT_PHY_1_CFG 0xa003fffe +#define AHCI_PORT_PHY_2_CFG 0x28183411 +#define AHCI_PORT_PHY_3_CFG 0x0e081004 +#define AHCI_PORT_PHY_4_CFG 0x00480811 +#define AHCI_PORT_PHY_5_CFG 0x192c96a4 +#define AHCI_PORT_TRANS_CFG 0x08000025 + +#define SATA_ECC_REG_ADDR 0x20220520 +#define SATA_ECC_DISABLE 0x00020000 + +int ls1021a_sata_init(void) +{ + struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 + out_le32((void *)SATA_ECC_REG_ADDR, SATA_ECC_DISABLE); +#endif + + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); + out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); + out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); + out_le32(&ccsr_ahci->pp4c, AHCI_PORT_PHY_4_CFG); + out_le32(&ccsr_ahci->pp5c, AHCI_PORT_PHY_5_CFG); + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + + ahci_init((void __iomem *)AHCI_BASE_ADDR); + scsi_scan(0); + + return 0; +} diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index bcaf7bf..f066480 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -79,6 +79,21 @@ #define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \ CONFIG_SYS_PCIE2_VIRT_ADDR) +/* SATA */ +#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_CMD_SCSI +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_FSL_ERRATUM_A008407 + #ifdef CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR_BE #define CONFIG_VERY_BIG_RAM diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index fbd06ba..09ed980 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -398,4 +398,28 @@ struct ccsr_cci400 { u8 res_e004[0x10000 - 0xe004]; }; +/* AHCI (sata) register map */ +struct ccsr_ahci { + u32 res1[0xa4/4]; /* 0x0 - 0xa4 */ + u32 pcfg; /* port config */ + u32 ppcfg; /* port phy1 config */ + u32 pp2c; /* port phy2 config */ + u32 pp3c; /* port phy3 config */ + u32 pp4c; /* port phy4 config */ + u32 pp5c; /* port phy5 config */ + u32 paxic; /* port AXI config */ + u32 axicc; /* AXI cache control */ + u32 axipc; /* AXI PROT control */ + u32 ptc; /* port Trans Config */ + u32 pts; /* port Trans Status */ + u32 plc; /* port link config */ + u32 plc1; /* port link config1 */ + u32 plc2; /* port link config2 */ + u32 pls; /* port link status */ + u32 pls1; /* port link status1 */ + u32 pcmdc; /* port CMD config */ + u32 ppcs; /* port phy control status */ + u32 pberr; /* port 0/1 BIST error */ + u32 cmds; /* port 0/1 CMD status error */ +}; #endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h new file mode 100644 index 0000000..d097a6a --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h @@ -0,0 +1,11 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_SATA_H_ +#define __FSL_SATA_H_ + +int ls1021a_sata_init(void); +#endif -- cgit v1.1 From 478ec83489dea9e27b59eeaf77eed52a6d1185f5 Mon Sep 17 00:00:00 2001 From: Josh Wu Date: Fri, 23 Oct 2015 17:23:57 +0800 Subject: at91: simplify spl board_init_f function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit crt0.S do both memset the bss section and call board_init_r for us, so remove them from board_init_f(). Signed-off-by: Josh Wu Reviewed-by: Simon Glass Reviewed-by: Andreas Bießmann --- arch/arm/mach-at91/spl_atmel.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c index 8ac5335..b2fb51d 100644 --- a/arch/arm/mach-at91/spl_atmel.c +++ b/arch/arm/mach-at91/spl_atmel.c @@ -98,9 +98,4 @@ void board_init_f(ulong dummy) preloader_console_init(); mem_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - board_init_r(NULL, 0); } -- cgit v1.1 From fdbb740d7c3fd701ca3af1f6033060cfd358c2bc Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Tue, 27 Oct 2015 13:07:55 +0100 Subject: s5p: cpu_info: print "cpu-model" if exists in dts The CPU name for Exynos was concatenated with cpu id, but for new Exynos platforms, like Chromebook Peach Pi based on Exynos5800, the name of SoC variant does not include the real SoC cpu id (0x5422). For such case, the CPU name should be defined in device tree. This commit introduces new device-tree property for Exynos: - "cpu-model" - with cpu name string If defined, then the cpu id is not printed. Signed-off-by: Przemyslaw Marczak Cc: Minkyu Kang Cc: Simon Glass Reviewed-by: Simon Glass Tested-by: Anand Moon Signed-off-by: Minkyu Kang --- arch/arm/cpu/armv7/s5p-common/cpu_info.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/s5p-common/cpu_info.c b/arch/arm/cpu/armv7/s5p-common/cpu_info.c index 154d674..764c661 100644 --- a/arch/arm/cpu/armv7/s5p-common/cpu_info.c +++ b/arch/arm/cpu/armv7/s5p-common/cpu_info.c @@ -5,9 +5,12 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include +#include #include #include +DECLARE_GLOBAL_DATA_PTR; + /* Default is s5pc100 */ unsigned int s5p_cpu_id = 0xC100; /* Default is EVT1 */ @@ -30,7 +33,16 @@ u32 get_device_type(void) #ifdef CONFIG_DISPLAY_CPUINFO int print_cpuinfo(void) { - printf("CPU: %s%X @ ", s5p_get_cpu_name(), s5p_cpu_id); + const char *cpu_model; + int len; + + /* For SoC with no real CPU ID in naming convention. */ + cpu_model = fdt_getprop(gd->fdt_blob, 0, "cpu-model", &len); + if (cpu_model) + printf("CPU: %.*s @ ", len, cpu_model); + else + printf("CPU: %s%X @ ", s5p_get_cpu_name(), s5p_cpu_id); + print_freq(get_arm_clk(), "\n"); return 0; -- cgit v1.1 From 3b72b60099b87dedcc49cd6881d311515f23ac14 Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Tue, 27 Oct 2015 13:07:56 +0100 Subject: Peach-Pi: dts: add cpu-model string This platform is based on Exynos5800 but the cpu id is 0x5422. This doesn't fit the common Exynos SoC name convention, so now, the CPU name is defined by device tree string, to be printed properly. Signed-off-by: Przemyslaw Marczak Cc: Minkyu Kang Cc: Simon Glass Reviewed-by: Simon Glass Tested-by: Anand Moon Signed-off-by: Minkyu Kang --- arch/arm/dts/exynos5800-peach-pi.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts index 1d7ff23..76826dc 100644 --- a/arch/arm/dts/exynos5800-peach-pi.dts +++ b/arch/arm/dts/exynos5800-peach-pi.dts @@ -12,6 +12,7 @@ / { model = "Samsung/Google Peach Pi board based on Exynos5800"; + cpu-model = "Exynos5800"; compatible = "google,pit-rev#", "google,pit", "google,peach", "samsung,exynos5800", "samsung,exynos5"; -- cgit v1.1 From d64c8adedc6df41165ca08973a0057645ef72139 Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Tue, 27 Oct 2015 13:07:57 +0100 Subject: Exynos5422/5800: set cpu id to 0x5422 The proper CPU ID for those Exynos variants is 0x5422, but before the 0x5800 was set. This commit fix this back. Changes: - set cpu id to 0x5422 instead of 0x5800 - remove macro proid_is_exynos5800() - add macro proid_is_exynos5422() - change the calls to proid_is_exynos5800() with new macro Signed-off-by: Przemyslaw Marczak Cc: Minkyu Kang Cc: Simon Glass Tested-by: Anand Moon Signed-off-by: Minkyu Kang --- arch/arm/mach-exynos/clock.c | 16 ++++++++-------- arch/arm/mach-exynos/clock_init_exynos5.c | 2 +- arch/arm/mach-exynos/common_setup.h | 4 ++-- arch/arm/mach-exynos/include/mach/cpu.h | 6 +++--- arch/arm/mach-exynos/include/mach/gpio.h | 4 ++-- arch/arm/mach-exynos/pinmux.c | 2 +- arch/arm/mach-exynos/power.c | 2 +- 7 files changed, 18 insertions(+), 18 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c index 18eadf5..3d31f9d 100644 --- a/arch/arm/mach-exynos/clock.c +++ b/arch/arm/mach-exynos/clock.c @@ -159,8 +159,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) div = PLL_DIV_1024; else if (proid_is_exynos4412()) div = PLL_DIV_65535; - else if (proid_is_exynos5250() || proid_is_exynos5420() - || proid_is_exynos5800()) + else if (proid_is_exynos5250() || proid_is_exynos5420() || + proid_is_exynos5422()) div = PLL_DIV_65536; else return 0; @@ -346,7 +346,7 @@ static struct clk_bit_info *get_clk_bit_info(int peripheral) int i; struct clk_bit_info *info; - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420() || proid_is_exynos5422()) info = exynos542x_bit_info; else info = exynos5_bit_info; @@ -558,7 +558,7 @@ static unsigned long exynos542x_get_periph_rate(int peripheral) unsigned long clock_get_periph_rate(int peripheral) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420() || proid_is_exynos5422()) return exynos542x_get_periph_rate(peripheral); return exynos5_get_periph_rate(peripheral); } else { @@ -1576,7 +1576,7 @@ static unsigned long exynos4_get_i2c_clk(void) unsigned long get_pll_clk(int pllreg) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420() || proid_is_exynos5422()) return exynos542x_get_pll_clk(pllreg); return exynos5_get_pll_clk(pllreg); } else if (cpu_is_exynos4()) { @@ -1692,7 +1692,7 @@ void set_mmc_clk(int dev_index, unsigned int div) div -= 1; if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420() || proid_is_exynos5422()) exynos5420_set_mmc_clk(dev_index, div); else exynos5_set_mmc_clk(dev_index, div); @@ -1708,7 +1708,7 @@ unsigned long get_lcd_clk(void) } else if (cpu_is_exynos5()) { if (proid_is_exynos5420()) return exynos5420_get_lcd_clk(); - else if (proid_is_exynos5800()) + else if (proid_is_exynos5422()) return exynos5800_get_lcd_clk(); else return exynos5_get_lcd_clk(); @@ -1740,7 +1740,7 @@ void set_mipi_clk(void) int set_spi_clk(int periph_id, unsigned int rate) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420() || proid_is_exynos5422()) return exynos5420_set_spi_clk(periph_id, rate); return exynos5_set_spi_clk(periph_id, rate); } diff --git a/arch/arm/mach-exynos/clock_init_exynos5.c b/arch/arm/mach-exynos/clock_init_exynos5.c index 0200fd1..1b7498d 100644 --- a/arch/arm/mach-exynos/clock_init_exynos5.c +++ b/arch/arm/mach-exynos/clock_init_exynos5.c @@ -971,7 +971,7 @@ static void exynos5420_system_clock_init(void) void system_clock_init(void) { - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420() || proid_is_exynos5422()) exynos5420_system_clock_init(); else exynos5250_system_clock_init(); diff --git a/arch/arm/mach-exynos/common_setup.h b/arch/arm/mach-exynos/common_setup.h index 67aac2d..2829fb2 100644 --- a/arch/arm/mach-exynos/common_setup.h +++ b/arch/arm/mach-exynos/common_setup.h @@ -78,7 +78,7 @@ static inline void configure_l2_ctlr(void) CACHE_TAG_RAM_LATENCY_2_CYCLES | CACHE_DATA_RAM_LATENCY_2_CYCLES; - if (proid_is_exynos5420() || proid_is_exynos5800()) { + if (proid_is_exynos5420() || proid_is_exynos5422()) { val |= CACHE_ECC_AND_PARITY | CACHE_TAG_RAM_LATENCY_3_CYCLES | CACHE_DATA_RAM_LATENCY_3_CYCLES; @@ -97,7 +97,7 @@ static inline void configure_l2_actlr(void) { uint32_t val; - if (proid_is_exynos5420() || proid_is_exynos5800()) { + if (proid_is_exynos5420() || proid_is_exynos5422()) { mrc_l2_aux_ctlr(val); val |= CACHE_ENABLE_FORCE_L2_LOGIC | CACHE_DISABLE_CLEAN_EVICT; diff --git a/arch/arm/mach-exynos/include/mach/cpu.h b/arch/arm/mach-exynos/include/mach/cpu.h index cb3d2cc..14a1692 100644 --- a/arch/arm/mach-exynos/include/mach/cpu.h +++ b/arch/arm/mach-exynos/include/mach/cpu.h @@ -237,7 +237,7 @@ static inline void s5p_set_cpu_id(void) * Exynos5800 is a variant of Exynos5420 * and has product id 0x5422 */ - s5p_cpu_id = 0x5800; + s5p_cpu_id = 0x5422; break; } } @@ -267,7 +267,7 @@ IS_EXYNOS_TYPE(exynos4210, 0x4210) IS_EXYNOS_TYPE(exynos4412, 0x4412) IS_EXYNOS_TYPE(exynos5250, 0x5250) IS_EXYNOS_TYPE(exynos5420, 0x5420) -IS_EXYNOS_TYPE(exynos5800, 0x5800) +IS_EXYNOS_TYPE(exynos5422, 0x5422) #define SAMSUNG_BASE(device, base) \ static inline unsigned int __attribute__((no_instrument_function)) \ @@ -278,7 +278,7 @@ static inline unsigned int __attribute__((no_instrument_function)) \ return EXYNOS4X12_##base; \ return EXYNOS4_##base; \ } else if (cpu_is_exynos5()) { \ - if (proid_is_exynos5420() || proid_is_exynos5800()) \ + if (proid_is_exynos5420() || proid_is_exynos5422()) \ return EXYNOS5420_##base; \ return EXYNOS5_##base; \ } \ diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h index 9699954..7fc8e61 100644 --- a/arch/arm/mach-exynos/include/mach/gpio.h +++ b/arch/arm/mach-exynos/include/mach/gpio.h @@ -1398,7 +1398,7 @@ static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = { static inline struct gpio_info *get_gpio_data(void) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420() || proid_is_exynos5422()) return exynos5420_gpio_data; else return exynos5_gpio_data; @@ -1415,7 +1415,7 @@ static inline struct gpio_info *get_gpio_data(void) static inline unsigned int get_bank_num(void) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420() || proid_is_exynos5422()) return EXYNOS5420_GPIO_NUM_PARTS; else return EXYNOS5_GPIO_NUM_PARTS; diff --git a/arch/arm/mach-exynos/pinmux.c b/arch/arm/mach-exynos/pinmux.c index 179b294..a556e4a 100644 --- a/arch/arm/mach-exynos/pinmux.c +++ b/arch/arm/mach-exynos/pinmux.c @@ -858,7 +858,7 @@ static int exynos4x12_pinmux_config(int peripheral, int flags) int exynos_pinmux_config(int peripheral, int flags) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420() || proid_is_exynos5422()) return exynos5420_pinmux_config(peripheral, flags); else if (proid_is_exynos5250()) return exynos5_pinmux_config(peripheral, flags); diff --git a/arch/arm/mach-exynos/power.c b/arch/arm/mach-exynos/power.c index 1b12051..cd2d661 100644 --- a/arch/arm/mach-exynos/power.c +++ b/arch/arm/mach-exynos/power.c @@ -125,7 +125,7 @@ static void exynos5420_set_usbdev_phy_ctrl(unsigned int enable) void set_usbdrd_phy_ctrl(unsigned int enable) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420() || proid_is_exynos5422()) exynos5420_set_usbdev_phy_ctrl(enable); else exynos5_set_usbdrd_phy_ctrl(enable); -- cgit v1.1 From 3b3ad9015e95ccad1a06e2eed1f182c8ddc36b21 Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Tue, 27 Oct 2015 13:08:01 +0100 Subject: dm: adc: add Exynos54xx compatible ADC driver This commit adds driver for Exynos54xx ADC subsystem. The driver is implemented using driver model, amd provides ADC uclass's methods for ADC single channel operations: - adc_start_channel() - adc_channel_data() - adc_stop() The basic parameters of ADC conversion, are: - sample rate: 600KSPS - output the data as average of 8 time conversion ADC features: - sample rate: 600KSPS - resolution: 12-bit - channels: 10 (analog multiplexer) Signed-off-by: Przemyslaw Marczak Cc: Minkyu Kang Cc: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/mach-exynos/include/mach/adc.h | 44 +++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-exynos/include/mach/adc.h b/arch/arm/mach-exynos/include/mach/adc.h index a0e26d7..9af51ab 100644 --- a/arch/arm/mach-exynos/include/mach/adc.h +++ b/arch/arm/mach-exynos/include/mach/adc.h @@ -9,6 +9,39 @@ #ifndef __ASM_ARM_ARCH_ADC_H_ #define __ASM_ARM_ARCH_ADC_H_ +#define ADC_V2_CON1_SOFT_RESET (0x2 << 1) +#define ADC_V2_CON1_STC_EN 0x1 + +#define ADC_V2_CON2_OSEL(x) (((x) & 0x1) << 10) +#define OSEL_2S 0x0 +#define OSEL_BINARY 0x1 +#define ADC_V2_CON2_ESEL(x) (((x) & 0x1) << 9) +#define ESEL_ADC_EVAL_TIME_40CLK 0x0 +#define ESEL_ADC_EVAL_TIME_20CLK 0x1 +#define ADC_V2_CON2_HIGHF(x) (((x) & 0x1) << 8) +#define HIGHF_CONV_RATE_30KSPS 0x0 +#define HIGHF_CONV_RATE_600KSPS 0x1 +#define ADC_V2_CON2_C_TIME(x) (((x) & 0x7) << 4) +#define ADC_V2_CON2_CHAN_SEL_MASK 0xf +#define ADC_V2_CON2_CHAN_SEL(x) ((x) & ADC_V2_CON2_CHAN_SEL_MASK) + +#define ADC_V2_GET_STATUS_FLAG(x) (((x) >> 2) & 0x1) +#define FLAG_CONV_END 0x1 + +#define ADC_V2_INT_DISABLE 0x0 +#define ADC_V2_INT_ENABLE 0x1 +#define INT_NOT_GENERATED 0x0 +#define INT_GENERATED 0x1 + +#define ADC_V2_VERSION 0x80000008 + +#define ADC_V2_MAX_CHANNEL 9 + +/* For default 8 time convertion with sample rate 600 kSPS - 15us timeout */ +#define ADC_V2_CONV_TIMEOUT_US 15 + +#define ADC_V2_DAT_MASK 0xfff + #ifndef __ASSEMBLY__ struct s5p_adc { unsigned int adccon; @@ -21,6 +54,17 @@ struct s5p_adc { unsigned int adcmux; unsigned int adcclrintpndnup; }; + +struct exynos_adc_v2 { + unsigned int con1; + unsigned int con2; + unsigned int status; + unsigned int dat; + unsigned int int_en; + unsigned int int_status; + unsigned int reserved[2]; + unsigned int version; +}; #endif #endif /* __ASM_ARM_ARCH_ADC_H_ */ -- cgit v1.1 From 4d577e0810ccc10cfb7ea61308061fa7ef832468 Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Tue, 27 Oct 2015 13:08:02 +0100 Subject: Odroid-XU3: enable s2mps11 PMIC support Signed-off-by: Przemyslaw Marczak Cc: Minkyu Kang Cc: Simon Glass Tested-by: Anand Moon Signed-off-by: Minkyu Kang --- arch/arm/dts/exynos5422-odroidxu3.dts | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts index d0a8621..9dec679 100644 --- a/arch/arm/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/dts/exynos5422-odroidxu3.dts @@ -31,6 +31,13 @@ 0xb0000000 0xea00000>; }; + i2c@12CA0000 { + s2mps11_pmic@66 { + compatible = "samsung,s2mps11-pmic"; + reg = <0x66>; + }; + }; + ehci@12110000 { samsung,vbus-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>; }; -- cgit v1.1 From 54b51e6b12f0667848e0d1d994673630d28b219e Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Tue, 27 Oct 2015 13:08:03 +0100 Subject: Exynos54xx: dts: add ADC node This commit adds common ADC node, which is disabled as default. Signed-off-by: Przemyslaw Marczak Cc: Minkyu Kang Cc: Simon Glass Reviewed-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/dts/exynos54xx.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi index bd3619d..daa6a33 100644 --- a/arch/arm/dts/exynos54xx.dtsi +++ b/arch/arm/dts/exynos54xx.dtsi @@ -42,6 +42,13 @@ xhci1 = "/xhci@12400000"; }; + adc@12D10000 { + compatible = "samsung,exynos-adc-v2"; + reg = <0x12D10000 0x100>; + interrupts = <0 106 0>; + status = "disabled"; + }; + i2c@12CA0000 { #address-cells = <1>; #size-cells = <0>; -- cgit v1.1 From 9090d1dd0e379d598b72c7176cf55f3343421dae Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Tue, 27 Oct 2015 13:08:04 +0100 Subject: Odroid-XU3: dts: enable ADC, with request for pre-reloc bind This ADC is required for Odroid's board revision detection. The pre-reloc request is enabled, since board detection will be done in one of early function call. Signed-off-by: Przemyslaw Marczak Cc: Minkyu Kang Cc: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/dts/exynos5422-odroidxu3.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts index 9dec679..690c747 100644 --- a/arch/arm/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/dts/exynos5422-odroidxu3.dts @@ -31,6 +31,11 @@ 0xb0000000 0xea00000>; }; + adc@12D10000 { + u-boot,dm-pre-reloc; + status = "okay"; + }; + i2c@12CA0000 { s2mps11_pmic@66 { compatible = "samsung,s2mps11-pmic"; -- cgit v1.1 From 5d0434315c46a3a038a9842a6627f6a57d1538da Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Wed, 28 Oct 2015 15:41:49 +0100 Subject: Exynos4412: pinmux: disable pull for MMC pins There are 8 pins for SD card in Exynos, but the MUX was configured only for 7, since the one was used for card detection. This caused the pin's pull wrong configuration. This commit fixes this and the card detect can work properly, after call this function. Tested-on: Odroid U3 and Odroid X2. Signed-off-by: Przemyslaw Marczak Cc: Guillaume GARDET Cc: Lukasz Majewski Cc: Jaehoon Chung Cc: Minkyu Kang Cc: Simon Glass Acked-by: Jaehoon Chung Tested-by: Lukasz Majewski Signed-off-by: Minkyu Kang --- arch/arm/mach-exynos/pinmux.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-exynos/pinmux.c b/arch/arm/mach-exynos/pinmux.c index a556e4a..12eb79c 100644 --- a/arch/arm/mach-exynos/pinmux.c +++ b/arch/arm/mach-exynos/pinmux.c @@ -737,10 +737,10 @@ static int exynos4x12_mmc_config(int peripheral, int flags) return -1; } for (i = start; i < (start + 7); i++) { + gpio_set_pull(i, S5P_GPIO_PULL_NONE); if (i == (start + 2)) continue; gpio_cfg_pin(i, func); - gpio_set_pull(i, S5P_GPIO_PULL_NONE); gpio_set_drv(i, S5P_GPIO_DRV_4X); } if (flags & PINMUX_FLAG_8BIT_MODE) { -- cgit v1.1 From 55a70c51acd20d52badbb0683699b7a11fee5f44 Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Thu, 22 Oct 2015 14:51:58 +0900 Subject: arm: exynos: clean up checkpatch issues This patch will fix these checkpatch issues. ERROR: Macros with complex values should be enclosed in parentheses +#define DEFAULT_DQS_X4 (DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \ + || (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0) ERROR: space prohibited before that ',' (ctx:WxW) + writel(val , &drex0->concontrol); ^ ERROR: space prohibited before that ',' (ctx:WxW) + writel(val , &drex1->concontrol); ^ Signed-off-by: Minkyu Kang --- arch/arm/mach-exynos/dmc_init_ddr3.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-exynos/dmc_init_ddr3.c b/arch/arm/mach-exynos/dmc_init_ddr3.c index 7c0b12a..25a9df9 100644 --- a/arch/arm/mach-exynos/dmc_init_ddr3.c +++ b/arch/arm/mach-exynos/dmc_init_ddr3.c @@ -20,8 +20,8 @@ #define TIMEOUT_US 10000 #define NUM_BYTE_LANES 4 #define DEFAULT_DQS 8 -#define DEFAULT_DQS_X4 (DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \ - || (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0) +#define DEFAULT_DQS_X4 ((DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \ + || (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0)) #ifdef CONFIG_EXYNOS5250 static void reset_phy_ctrl(void) @@ -856,10 +856,10 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) */ val = readl(&drex0->concontrol); val |= CONCONTROL_UPDATE_MODE; - writel(val , &drex0->concontrol); + writel(val, &drex0->concontrol); val = readl(&drex1->concontrol); val |= CONCONTROL_UPDATE_MODE; - writel(val , &drex1->concontrol); + writel(val, &drex1->concontrol); return 0; } -- cgit v1.1 From ce39680f7e560236213487ac6bf1baa66b6f74e3 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Tue, 8 Sep 2015 14:38:26 +0800 Subject: arm: at91: Change the Chip ID registers' addresses MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Provide the specific addresses for the Chip ID and Chip ID Extension registers, instead of the offset, which make it use on other chips. Signed-off-by: Wenyou Yang Reviewed-by: Andreas Bießmann --- arch/arm/mach-at91/armv7/cpu.c | 7 ++++--- arch/arm/mach-at91/include/mach/at91_dbu.h | 4 ---- arch/arm/mach-at91/include/mach/sama5d3.h | 3 +++ arch/arm/mach-at91/include/mach/sama5d4.h | 3 +++ 4 files changed, 10 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/armv7/cpu.c b/arch/arm/mach-at91/armv7/cpu.c index 8d86f97..7843aed 100644 --- a/arch/arm/mach-at91/armv7/cpu.c +++ b/arch/arm/mach-at91/armv7/cpu.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -65,12 +64,14 @@ void enable_caches(void) dcache_enable(); } +#define ATMEL_CHIPID_CIDR_VERSION 0x1f + unsigned int get_chip_id(void) { - return readl(ATMEL_BASE_DBGU + AT91_DBU_CIDR) & ~AT91_DBU_CIDR_MASK; + return readl(ATMEL_CHIPID_CIDR) & ~ATMEL_CHIPID_CIDR_VERSION; } unsigned int get_extension_chip_id(void) { - return readl(ATMEL_BASE_DBGU + AT91_DBU_EXID); + return readl(ATMEL_CHIPID_EXID); } diff --git a/arch/arm/mach-at91/include/mach/at91_dbu.h b/arch/arm/mach-at91/include/mach/at91_dbu.h index 7346fc0..3181138 100644 --- a/arch/arm/mach-at91/include/mach/at91_dbu.h +++ b/arch/arm/mach-at91/include/mach/at91_dbu.h @@ -35,8 +35,4 @@ typedef struct at91_dbu { #define AT91_DBU_CID_ARCH_9xx 0x01900000 #define AT91_DBU_CID_ARCH_9XExx 0x02900000 -#define AT91_DBU_CIDR_MASK 0x1f -#define AT91_DBU_CIDR 0x40 -#define AT91_DBU_EXID 0x44 - #endif diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h index b749cb3..33f6c97 100644 --- a/arch/arm/mach-at91/include/mach/sama5d3.h +++ b/arch/arm/mach-at91/include/mach/sama5d3.h @@ -158,6 +158,9 @@ #define ATMEL_BASE_RTC 0xfffffeb0 /* Reserved: 0xfffffee0 - 0xffffffff */ +#define ATMEL_CHIPID_CIDR 0xffffee40 +#define ATMEL_CHIPID_EXID 0xffffee44 + /* * Internal Memory. */ diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h index 7773ace..3da8aff 100644 --- a/arch/arm/mach-at91/include/mach/sama5d4.h +++ b/arch/arm/mach-at91/include/mach/sama5d4.h @@ -144,6 +144,9 @@ #define ATMEL_BASE_PIOE 0xfc06d000 #define ATMEL_BASE_AIC 0xfc06e000 +#define ATMEL_CHIPID_CIDR 0xfc069040 +#define ATMEL_CHIPID_EXID 0xfc069044 + /* * Internal Memory. */ -- cgit v1.1 From c19000556e1d21bc5830464b6b9964a977ab1e32 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Fri, 30 Oct 2015 09:47:02 +0800 Subject: arm: at91: clock: Add the generated clock support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some peripherals may need a second clock source that may be different from the system clock. This second clock is the generated clock (GCK) and is managed by the PMC via PMC_PCR. For simplicity, the clock source of the GCK is fixed to PLLA_CLK. Signed-off-by: Wenyou Yang Reviewed-by: Andreas Bießmann --- arch/arm/mach-at91/armv7/clock.c | 95 ++++++++++++++++++++++++++++++ arch/arm/mach-at91/include/mach/at91_pmc.h | 13 ++++ arch/arm/mach-at91/include/mach/clk.h | 10 ++++ 3 files changed, 118 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c index 0bf453e..41dbf16 100644 --- a/arch/arm/mach-at91/armv7/clock.c +++ b/arch/arm/mach-at91/armv7/clock.c @@ -5,11 +5,13 @@ * Copyright (C) 2005 Ivan Kokshaysky * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD * Copyright (C) 2013 Bo Shen + * Copyright (C) 2015 Wenyou Yang * * SPDX-License-Identifier: GPL-2.0+ */ #include +#include #include #include #include @@ -173,3 +175,96 @@ void at91_periph_clk_disable(int id) writel(regval, &pmc->pcr); } + +int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 regval, status; + u32 timeout = 1000; + + if (id > AT91_PMC_PCR_PID_MASK) + return -EINVAL; + + if (div > 0xff) + return -EINVAL; + + writel(id, &pmc->pcr); + regval = readl(&pmc->pcr); + regval &= ~AT91_PMC_PCR_GCKCSS; + regval &= ~AT91_PMC_PCR_GCKDIV; + + switch (clk_source) { + case GCK_CSS_SLOW_CLK: + regval |= AT91_PMC_PCR_GCKCSS_SLOW_CLK; + break; + case GCK_CSS_MAIN_CLK: + regval |= AT91_PMC_PCR_GCKCSS_MAIN_CLK; + break; + case GCK_CSS_PLLA_CLK: + regval |= AT91_PMC_PCR_GCKCSS_PLLA_CLK; + break; + case GCK_CSS_UPLL_CLK: + regval |= AT91_PMC_PCR_GCKCSS_UPLL_CLK; + break; + case GCK_CSS_MCK_CLK: + regval |= AT91_PMC_PCR_GCKCSS_MCK_CLK; + break; + case GCK_CSS_AUDIO_CLK: + regval |= AT91_PMC_PCR_GCKCSS_AUDIO_CLK; + break; + default: + printf("Error GCK clock source selection!\n"); + return -EINVAL; + } + + regval |= AT91_PMC_PCR_CMD_WRITE | + AT91_PMC_PCR_GCKDIV_(div) | + AT91_PMC_PCR_GCKEN; + + writel(regval, &pmc->pcr); + + do { + udelay(1); + status = readl(&pmc->sr); + } while ((!!(--timeout)) && (!(status & AT91_PMC_GCKRDY))); + + if (!timeout) + printf("Timeout waiting for GCK ready!\n"); + + return 0; +} + +u32 at91_get_periph_generated_clk(u32 id) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 regval, clk_source, div; + u32 freq; + + if (id > AT91_PMC_PCR_PID_MASK) + return 0; + + writel(id, &pmc->pcr); + regval = readl(&pmc->pcr); + + clk_source = regval & AT91_PMC_PCR_GCKCSS; + switch (clk_source) { + case AT91_PMC_PCR_GCKCSS_SLOW_CLK: + freq = CONFIG_SYS_AT91_SLOW_CLOCK; + break; + case AT91_PMC_PCR_GCKCSS_MAIN_CLK: + freq = gd->arch.main_clk_rate_hz; + break; + case AT91_PMC_PCR_GCKCSS_PLLA_CLK: + freq = gd->arch.plla_rate_hz; + break; + default: + printf("Improper GCK clock source selection!\n"); + freq = 0; + break; + } + + div = ((regval & AT91_PMC_PCR_GCKDIV) >> AT91_PMC_PCR_GCKDIV_OFFSET); + div += 1; + + return freq / div; +} diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 8a3fb94..5a51be6 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -153,8 +153,20 @@ typedef struct at91_pmc { #define AT91_PMC_IXR_MOSCSELS 0x00010000 #define AT91_PMC_PCR_PID_MASK (0x3f) +#define AT91_PMC_PCR_GCKCSS (0x7 << 8) +#define AT91_PMC_PCR_GCKCSS_SLOW_CLK (0x0 << 8) +#define AT91_PMC_PCR_GCKCSS_MAIN_CLK (0x1 << 8) +#define AT91_PMC_PCR_GCKCSS_PLLA_CLK (0x2 << 8) +#define AT91_PMC_PCR_GCKCSS_UPLL_CLK (0x3 << 8) +#define AT91_PMC_PCR_GCKCSS_MCK_CLK (0x4 << 8) +#define AT91_PMC_PCR_GCKCSS_AUDIO_CLK (0x5 << 8) #define AT91_PMC_PCR_CMD_WRITE (0x1 << 12) +#define AT91_PMC_PCR_DIV (0x3 << 16) +#define AT91_PMC_PCR_GCKDIV (0xff << 20) +#define AT91_PMC_PCR_GCKDIV_(x) ((x & 0xff) << 20) +#define AT91_PMC_PCR_GCKDIV_OFFSET 20 #define AT91_PMC_PCR_EN (0x1 << 28) +#define AT91_PMC_PCR_GCKEN (0x1 << 29) #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ @@ -236,6 +248,7 @@ typedef struct at91_pmc { #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ +#define AT91_PMC_GCKRDY (1 << 24) #define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ #endif diff --git a/arch/arm/mach-at91/include/mach/clk.h b/arch/arm/mach-at91/include/mach/clk.h index 1d45e2d..ad83927 100644 --- a/arch/arm/mach-at91/include/mach/clk.h +++ b/arch/arm/mach-at91/include/mach/clk.h @@ -13,6 +13,13 @@ #include #include +#define GCK_CSS_SLOW_CLK 0 +#define GCK_CSS_MAIN_CLK 1 +#define GCK_CSS_PLLA_CLK 2 +#define GCK_CSS_UPLL_CLK 3 +#define GCK_CSS_MCK_CLK 4 +#define GCK_CSS_AUDIO_CLK 5 + static inline unsigned long get_cpu_clk_rate(void) { DECLARE_GLOBAL_DATA_PTR; @@ -119,4 +126,7 @@ static inline unsigned long get_pit_clk_rate(void) int at91_clock_init(unsigned long main_clock); void at91_periph_clk_enable(int id); void at91_periph_clk_disable(int id); +int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div); +u32 at91_get_periph_generated_clk(u32 id); + #endif /* __ASM_ARM_ARCH_CLK_H__ */ -- cgit v1.1 From a3b59b1523727da932b284737fbfc93a7f962125 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Mon, 2 Nov 2015 10:57:09 +0800 Subject: mmc: atmel: Add atmel sdhci support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SDHCI is introduced by sama5d2, named as Secure Digital Multimedia Card Controller(SDMMC). It supports the embedded MultiMedia Card (e.MMC) Specification V4.41, the SD Memory Card Specification V3.0, and the SDIO V3.0 specification. It is compliant with the SD Host Controller Standard V3.0 specification. Signed-off-by: Wenyou Yang Reviewed-by: Andreas Bießmann --- arch/arm/mach-at91/include/mach/atmel_sdhci.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 arch/arm/mach-at91/include/mach/atmel_sdhci.h (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/include/mach/atmel_sdhci.h b/arch/arm/mach-at91/include/mach/atmel_sdhci.h new file mode 100644 index 0000000..9652bc2 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/atmel_sdhci.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2015 Atmel Corporation + * Wenyou.Yang + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ATMEL_SDHCI_H +#define __ATMEL_SDHCI_H + +int atmel_sdhci_init(void *regbase, u32 id); + +#endif -- cgit v1.1 From c624d07f3ff7ae7d29672bab189d2aeb99c63a95 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 2 Nov 2015 17:11:21 -0600 Subject: arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit defines The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register, not the mpumodrst. So the bank for these reset bits should be 1, not 0. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/include/mach/reset_manager.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 8e59578..666a2ef 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -69,9 +69,9 @@ struct socfpga_reset_manager { #define RSTMGR_UART0 RSTMGR_DEFINE(1, 16) #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18) #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19) -#define RSTMGR_QSPI RSTMGR_DEFINE(0, 5) -#define RSTMGR_SDMMC RSTMGR_DEFINE(0, 22) -#define RSTMGR_DMA RSTMGR_DEFINE(0, 28) +#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5) +#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22) +#define RSTMGR_DMA RSTMGR_DEFINE(1, 28) #define RSTMGR_SDR RSTMGR_DEFINE(1, 29) /* Create a human-readable reference to SoCFPGA reset. */ -- cgit v1.1 From 44303dfa792b0a4f81d6f6a719467db9a20063b5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 30 Oct 2015 15:39:18 +0100 Subject: ARM: zynqmp: Add DTS for ep108 board Add DTS for ep108 board. Signed-off-by: Michal Simek Series-to: u-boot --- arch/arm/dts/Makefile | 2 + arch/arm/dts/zynqmp-ep108-clk.dtsi | 119 +++++++ arch/arm/dts/zynqmp-ep108.dts | 174 ++++++++++ arch/arm/dts/zynqmp.dtsi | 668 +++++++++++++++++++++++++++++++++++++ 4 files changed, 963 insertions(+) create mode 100644 arch/arm/dts/zynqmp-ep108-clk.dtsi create mode 100644 arch/arm/dts/zynqmp-ep108.dts create mode 100644 arch/arm/dts/zynqmp.dtsi (limited to 'arch/arm') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ddc6a05..910648c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -65,6 +65,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ zynq-zc770-xm011.dtb \ zynq-zc770-xm012.dtb \ zynq-zc770-xm013.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += \ + zynqmp-ep108.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb diff --git a/arch/arm/dts/zynqmp-ep108-clk.dtsi b/arch/arm/dts/zynqmp-ep108-clk.dtsi new file mode 100644 index 0000000..f864526 --- /dev/null +++ b/arch/arm/dts/zynqmp-ep108-clk.dtsi @@ -0,0 +1,119 @@ +/* + * clock specification for Xilinx ZynqMP ep108 development board + * + * (C) Copyright 2015, Xilinx, Inc. + * + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +&amba { + misc_clk: misc_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + i2c_clk: i2c_clk { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <111111111>; + }; + + sata_clk: sata_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <75000000>; + }; + + dp_aclk: clock0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-accuracy = <100>; + }; + + dp_aud_clk: clock1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <22579200>; + clock-accuracy = <100>; + }; +}; + +&can0 { + clocks = <&misc_clk &misc_clk>; +}; + +&gem0 { + clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>; +}; + +&gpio { + clocks = <&misc_clk>; +}; + +&i2c0 { + clocks = <&i2c_clk>; +}; + +&i2c1 { + clocks = <&i2c_clk>; +}; + +&qspi { + clocks = <&misc_clk &misc_clk>; +}; + +&sata { + clocks = <&sata_clk>; +}; + +&sdhci0 { + clocks = <&misc_clk>, <&misc_clk>; +}; + +&sdhci1 { + clocks = <&misc_clk>, <&misc_clk>; +}; + +&spi0 { + clocks = <&misc_clk &misc_clk>; +}; + +&spi1 { + clocks = <&misc_clk &misc_clk>; +}; + +&uart0 { + clocks = <&misc_clk &misc_clk>; +}; + +&usb0 { + clocks = <&misc_clk>, <&misc_clk>; +}; + +&usb1 { + clocks = <&misc_clk>, <&misc_clk>; +}; + +&watchdog0 { + clocks= <&misc_clk>; +}; + +&xilinx_drm { + clocks = <&misc_clk>; +}; + +&xlnx_dp { + clocks = <&dp_aclk>, <&dp_aud_clk>; +}; + +&xlnx_dp_snd_codec0 { + clocks = <&dp_aud_clk>; +}; + +&xlnx_dpdma { + clocks = <&misc_clk>; +}; diff --git a/arch/arm/dts/zynqmp-ep108.dts b/arch/arm/dts/zynqmp-ep108.dts new file mode 100644 index 0000000..4481bd0 --- /dev/null +++ b/arch/arm/dts/zynqmp-ep108.dts @@ -0,0 +1,174 @@ +/* + * dts file for Xilinx ZynqMP ep108 development board + * + * (C) Copyright 2014 - 2015, Xilinx, Inc. + * + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +/include/ "zynqmp.dtsi" +/include/ "zynqmp-ep108-clk.dtsi" + +/ { + model = "ZynqMP EP108"; + + aliases { + serial0 = &uart0; + spi0 = &qspi; + spi1 = &spi0; + spi2 = &spi1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x40000000>; + }; +}; + +&can0 { + status = "okay"; +}; + +&gem0 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@0{ + reg = <0>; + max-speed = <100>; + }; +}; + +&gpio { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + eeprom@54 { + compatible = "at,24c64"; + reg = <0x54>; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + eeprom@55 { + compatible = "at,24c64"; + reg = <0x55>; + }; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "n25q512a11"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <10000000>; + partition@qspi-fsbl-uboot { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + }; +}; + +&sata { + status = "okay"; + ceva,broken-gen2; +}; + +&sdhci0 { + status = "okay"; +}; + +&sdhci1 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + num-cs = <1>; + spi0_flash0: spi0_flash0@0 { + compatible = "m25p80"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + + spi0_flash0@00000000 { + label = "spi0_flash0"; + reg = <0x0 0x100000>; + }; + }; +}; + +&spi1 { + status = "okay"; + num-cs = <1>; + spi1_flash0: spi1_flash0@0 { + compatible = "m25p80"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + + spi1_flash0@00000000 { + label = "spi1_flash0"; + reg = <0x0 0x100000>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "peripheral"; + maximum-speed = "high-speed"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; + maximum-speed = "high-speed"; +}; + +&watchdog0 { + status = "okay"; +}; + +&xlnx_dp { + xlnx,max-pclock-frequency = <200000>; +}; + +&xlnx_dpdma { + xlnx,axi-clock-freq = <200000000>; +}; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi new file mode 100644 index 0000000..24a34e6 --- /dev/null +++ b/arch/arm/dts/zynqmp.dtsi @@ -0,0 +1,668 @@ +/* + * dts file for Xilinx ZynqMP + * + * (C) Copyright 2014 - 2015, Xilinx, Inc. + * + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/ { + compatible = "xlnx,zynqmp"; + #address-cells = <2>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x0>; + }; + + cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x1>; + }; + + cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x2>; + }; + + cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x3>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 143 4>, + <0 144 4>, + <0 145 4>, + <0 146 4>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + firmware { + compatible = "xlnx,zynqmp-pm"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <1 13 0xf01>, + <1 14 0xf01>, + <1 11 0xf01>, + <1 10 0xf01>; + }; + + amba_apu: amba_apu { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + gic: interrupt-controller@f9010000 { + compatible = "arm,gic-400", "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + reg = <0x0 0xf9010000 0x10000>, + <0x0 0xf902f000 0x2000>, + <0x0 0xf9040000 0x20000>, + <0x0 0xf906f000 0x2000>; + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <1 9 0xf04>; + }; + }; + + amba: amba { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + can0: can@ff060000 { + compatible = "xlnx,zynq-can-1.0"; + status = "disabled"; + clock-names = "can_clk", "pclk"; + reg = <0x0 0xff060000 0x1000>; + interrupts = <0 23 4>; + interrupt-parent = <&gic>; + tx-fifo-depth = <0x40>; + rx-fifo-depth = <0x40>; + }; + + can1: can@ff070000 { + compatible = "xlnx,zynq-can-1.0"; + status = "disabled"; + clock-names = "can_clk", "pclk"; + reg = <0x0 0xff070000 0x1000>; + interrupts = <0 24 4>; + interrupt-parent = <&gic>; + tx-fifo-depth = <0x40>; + rx-fifo-depth = <0x40>; + }; + + /* GDMA */ + fpd_dma_chan1: dma@fd500000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xfd500000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 124 4>; + xlnx,id = <0>; + xlnx,bus-width = <128>; + }; + + fpd_dma_chan2: dma@fd510000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xfd510000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 125 4>; + xlnx,id = <1>; + xlnx,bus-width = <128>; + }; + + fpd_dma_chan3: dma@fd520000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xfd520000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 126 4>; + xlnx,id = <2>; + xlnx,bus-width = <128>; + }; + + fpd_dma_chan4: dma@fd530000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xfd530000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 127 4>; + xlnx,id = <3>; + xlnx,bus-width = <128>; + }; + + fpd_dma_chan5: dma@fd540000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xfd540000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 128 4>; + xlnx,id = <4>; + xlnx,bus-width = <128>; + }; + + fpd_dma_chan6: dma@fd550000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xfd550000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 129 4>; + xlnx,id = <5>; + xlnx,bus-width = <128>; + }; + + fpd_dma_chan7: dma@fd560000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xfd560000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 130 4>; + xlnx,id = <6>; + xlnx,bus-width = <128>; + }; + + fpd_dma_chan8: dma@fd570000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xfd570000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 131 4>; + xlnx,id = <7>; + xlnx,bus-width = <128>; + }; + + gpu: gpu@fd4b0000 { + status = "disabled"; + compatible = "arm,mali-400", "arm,mali-utgard"; + reg = <0x0 0xfd4b0000 0x30000>; + interrupt-parent = <&gic>; + interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; + interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; + }; + + /* ADMA */ + lpd_dma_chan1: dma@ffa80000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xffa80000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 77 4>; + xlnx,id = <0>; + xlnx,bus-width = <64>; + }; + + lpd_dma_chan2: dma@ffa90000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xffa90000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 78 4>; + xlnx,id = <1>; + xlnx,bus-width = <64>; + }; + + lpd_dma_chan3: dma@ffaa0000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xffaa0000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 79 4>; + xlnx,id = <2>; + xlnx,bus-width = <64>; + }; + + lpd_dma_chan4: dma@ffab0000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xffab0000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 80 4>; + xlnx,id = <3>; + xlnx,bus-width = <64>; + }; + + lpd_dma_chan5: dma@ffac0000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xffac0000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 81 4>; + xlnx,id = <4>; + xlnx,bus-width = <64>; + }; + + lpd_dma_chan6: dma@ffad0000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xffad0000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 82 4>; + xlnx,id = <5>; + xlnx,bus-width = <64>; + }; + + lpd_dma_chan7: dma@ffae0000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xffae0000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 83 4>; + xlnx,id = <6>; + xlnx,bus-width = <64>; + }; + + lpd_dma_chan8: dma@ffaf0000 { + status = "disabled"; + compatible = "xlnx,zynqmp-dma-1.0"; + reg = <0x0 0xffaf0000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 84 4>; + xlnx,id = <7>; + xlnx,bus-width = <64>; + }; + + nand0: nand@ff100000 { + compatible = "arasan,nfc-v3p10"; + status = "disabled"; + reg = <0x0 0xff100000 0x1000>; + clock-names = "clk_sys", "clk_flash"; + interrupt-parent = <&gic>; + interrupts = <0 14 4>; + #address-cells = <2>; + #size-cells = <1>; + }; + + gem0: ethernet@ff0b0000 { + compatible = "cdns,gem"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 57 4>, <0 57 4>; + reg = <0x0 0xff0b0000 0x1000>; + clock-names = "pclk", "hclk", "tx_clk"; + #address-cells = <1>; + #size-cells = <0>; + jumbo-max-len = <10240>; + jumbo-supported; + }; + + gem1: ethernet@ff0c0000 { + compatible = "cdns,gem"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 59 4>, <0 59 4>; + reg = <0x0 0xff0c0000 0x1000>; + clock-names = "pclk", "hclk", "tx_clk"; + #address-cells = <1>; + #size-cells = <0>; + jumbo-max-len = <10240>; + jumbo-supported; + }; + + gem2: ethernet@ff0d0000 { + compatible = "cdns,gem"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 61 4>, <0 61 4>; + reg = <0x0 0xff0d0000 0x1000>; + clock-names = "pclk", "hclk", "tx_clk"; + #address-cells = <1>; + #size-cells = <0>; + jumbo-max-len = <10240>; + jumbo-supported; + }; + + gem3: ethernet@ff0e0000 { + compatible = "cdns,gem"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 63 4>, <0 63 4>; + reg = <0x0 0xff0e0000 0x1000>; + clock-names = "pclk", "hclk", "tx_clk"; + #address-cells = <1>; + #size-cells = <0>; + jumbo-max-len = <10240>; + jumbo-supported; + }; + + gpio: gpio@ff0a0000 { + compatible = "xlnx,zynqmp-gpio-1.0"; + status = "disabled"; + #gpio-cells = <0x2>; + interrupt-parent = <&gic>; + interrupts = <0 16 4>; + reg = <0x0 0xff0a0000 0x1000>; + }; + + i2c0: i2c@ff020000 { + compatible = "cdns,i2c-r1p10"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 17 4>; + reg = <0x0 0xff020000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@ff030000 { + compatible = "cdns,i2c-r1p10"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 18 4>; + reg = <0x0 0xff030000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + pcie: pcie@fd0e0000 { + compatible = "xlnx,nwl-pcie-2.11"; + status = "disabled"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + interrupt-parent = <&gic>; + interrupts = < 0 118 4>, + < 0 116 4>, + < 0 115 4>, /* MSI_1 [63...32] */ + < 0 114 4 >; /* MSI_0 [31...0] */ + interrupt-names = "misc", "intx", "msi_1", "msi_0"; + reg = <0x0 0xfd0e0000 0x1000>, + <0x0 0xfd480000 0x1000>, + <0x0 0xe0000000 0x1000000>; + reg-names = "breg", "pcireg", "cfg"; + ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>; + }; + + qspi: spi@ff0f0000 { + compatible = "xlnx,zynqmp-qspi-1.0"; + status = "disabled"; + clock-names = "ref_clk", "pclk"; + interrupts = <0 15 4>; + interrupt-parent = <&gic>; + num-cs = <1>; + reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + rtc: rtc@ffa60000 { + compatible = "xlnx,zynqmp-rtc"; + status = "disabled"; + reg = <0x0 0xffa60000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 26 4>, <0 27 4>; + interrupt-names = "alarm", "sec"; + }; + + sata: ahci@fd0c0000 { + compatible = "ceva,ahci-1v84"; + status = "disabled"; + reg = <0x0 0xfd0c0000 0x2000>; + interrupt-parent = <&gic>; + interrupts = <0 133 4>; + }; + + sdhci0: sdhci@ff160000 { + compatible = "arasan,sdhci-8.9a"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 48 4>; + reg = <0x0 0xff160000 0x1000>; + clock-names = "clk_xin", "clk_ahb"; + }; + + sdhci1: sdhci@ff170000 { + compatible = "arasan,sdhci-8.9a"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 49 4>; + reg = <0x0 0xff170000 0x1000>; + clock-names = "clk_xin", "clk_ahb"; + }; + + smmu: smmu@fd800000 { + compatible = "arm,mmu-500"; + reg = <0x0 0xfd800000 0x20000>; + #global-interrupts = <1>; + interrupt-parent = <&gic>; + interrupts = <0 157 4>, + <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, + <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, + <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, + <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>; + }; + + spi0: spi@ff040000 { + compatible = "cdns,spi-r1p6"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 19 4>; + reg = <0x0 0xff040000 0x1000>; + clock-names = "ref_clk", "pclk"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@ff050000 { + compatible = "cdns,spi-r1p6"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 20 4>; + reg = <0x0 0xff050000 0x1000>; + clock-names = "ref_clk", "pclk"; + #address-cells = <1>; + #size-cells = <0>; + }; + + ttc0: timer@ff110000 { + compatible = "cdns,ttc"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 36 4>, <0 37 4>, <0 38 4>; + reg = <0x0 0xff110000 0x1000>; + timer-width = <32>; + }; + + ttc1: timer@ff120000 { + compatible = "cdns,ttc"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 39 4>, <0 40 4>, <0 41 4>; + reg = <0x0 0xff120000 0x1000>; + timer-width = <32>; + }; + + ttc2: timer@ff130000 { + compatible = "cdns,ttc"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 42 4>, <0 43 4>, <0 44 4>; + reg = <0x0 0xff130000 0x1000>; + timer-width = <32>; + }; + + ttc3: timer@ff140000 { + compatible = "cdns,ttc"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 45 4>, <0 46 4>, <0 47 4>; + reg = <0x0 0xff140000 0x1000>; + timer-width = <32>; + }; + + uart0: serial@ff000000 { + compatible = "cdns,uart-r1p8"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 21 4>; + reg = <0x0 0xff000000 0x1000>; + clock-names = "uart_clk", "pclk"; + }; + + uart1: serial@ff010000 { + compatible = "cdns,uart-r1p8"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 22 4>; + reg = <0x0 0xff010000 0x1000>; + clock-names = "uart_clk", "pclk"; + }; + + usb0: usb@fe200000 { + compatible = "snps,dwc3"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 65 4>; + reg = <0x0 0xfe200000 0x40000>; + clock-names = "clk_xin", "clk_ahb"; + }; + + usb1: usb@fe300000 { + compatible = "snps,dwc3"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 70 4>; + reg = <0x0 0xfe300000 0x40000>; + clock-names = "clk_xin", "clk_ahb"; + }; + + watchdog0: watchdog@fd4d0000 { + compatible = "cdns,wdt-r1p2"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 52 1>; + reg = <0x0 0xfd4d0000 0x1000>; + timeout-sec = <10>; + }; + + xilinx_drm: xilinx_drm { + compatible = "xlnx,drm"; + status = "disabled"; + xlnx,encoder-slave = <&xlnx_dp>; + xlnx,connector-type = "DisplayPort"; + xlnx,dp-sub = <&xlnx_dp_sub>; + planes { + xlnx,pixel-format = "rgb565"; + plane0 { + dmas = <&xlnx_dpdma 3>; + dma-names = "dma"; + }; + plane1 { + dmas = <&xlnx_dpdma 0>; + dma-names = "dma"; + }; + }; + }; + + xlnx_dp: dp@43c00000 { + compatible = "xlnx,v-dp"; + status = "disabled"; + reg = <0x0 0xfd4a0000 0x1000>; + interrupts = <0 119 4>; + interrupt-parent = <&gic>; + clock-names = "aclk", "aud_clk"; + xlnx,dp-version = "v1.2"; + xlnx,max-lanes = <2>; + xlnx,max-link-rate = <540000>; + xlnx,max-bpc = <16>; + xlnx,enable-ycrcb; + xlnx,colormetry = "rgb"; + xlnx,bpc = <8>; + xlnx,audio-chan = <2>; + xlnx,dp-sub = <&xlnx_dp_sub>; + }; + + xlnx_dp_snd_card: dp_snd_card { + compatible = "xlnx,dp-snd-card"; + status = "disabled"; + xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>; + xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>; + }; + + xlnx_dp_snd_codec0: dp_snd_codec0 { + compatible = "xlnx,dp-snd-codec"; + status = "disabled"; + clock-names = "aud_clk"; + }; + + xlnx_dp_snd_pcm0: dp_snd_pcm0 { + compatible = "xlnx,dp-snd-pcm"; + status = "disabled"; + dmas = <&xlnx_dpdma 4>; + dma-names = "tx"; + }; + + xlnx_dp_snd_pcm1: dp_snd_pcm1 { + compatible = "xlnx,dp-snd-pcm"; + status = "disabled"; + dmas = <&xlnx_dpdma 5>; + dma-names = "tx"; + }; + + xlnx_dp_sub: dp_sub@43c0a000 { + compatible = "xlnx,dp-sub"; + status = "disabled"; + reg = <0x0 0xfd4aa000 0x1000>, <0x0 0xfd4ab000 0x1000>, <0x0 0xfd4ac000 0x1000>; + reg-names = "blend", "av_buf", "aud"; + xlnx,output-fmt = "rgb"; + }; + + xlnx_dpdma: dma@fd4c0000 { + compatible = "xlnx,dpdma"; + status = "disabled"; + reg = <0x0 0xfd4c0000 0x1000>; + interrupts = <0 122 4>; + interrupt-parent = <&gic>; + clock-names = "axi_clk"; + dma-channels = <6>; + #dma-cells = <1>; + dma-video0channel@43c10000 { + compatible = "xlnx,video0"; + }; + dma-video1channel@43c10000 { + compatible = "xlnx,video1"; + }; + dma-video2channel@43c10000 { + compatible = "xlnx,video2"; + }; + dma-graphicschannel@43c10000 { + compatible = "xlnx,graphics"; + }; + dma-audio0channel@43c10000 { + compatible = "xlnx,audio0"; + }; + dma-audio1channel@43c10000 { + compatible = "xlnx,audio1"; + }; + }; + }; +}; -- cgit v1.1 From bd44758a41b6d38b865e0bc0b1751c6129c1ec2b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 17 Oct 2015 19:41:21 -0600 Subject: arm: zynq: Drop unnecessary code in SPL board_init_f() Move to the new way of starting up SPL. Clearing of BSS and calling board_init_r() is now handled by crt0.S. Also tidy up the header include order. Signed-off-by: Simon Glass Signed-off-by: Michal Simek --- arch/arm/mach-zynq/spl.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c index 7bdac3b..1805455 100644 --- a/arch/arm/mach-zynq/spl.c +++ b/arch/arm/mach-zynq/spl.c @@ -7,8 +7,8 @@ #include #include -#include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -17,11 +17,7 @@ void board_init_f(ulong dummy) { ps7_init(); - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - arch_cpu_init(); - board_init_r(NULL, 0); } #ifdef CONFIG_SPL_BOARD_INIT -- cgit v1.1 From c54c0a4c1c745a009565ceb2a5c564d4d9418476 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 17 Oct 2015 19:41:22 -0600 Subject: arm: zynq: Support the debug UART Add support for the debug UART to assist with early debugging. Enable it for Zybo as an example. Signed-off-by: Simon Glass Signed-off-by: Michal Simek --- arch/arm/mach-zynq/spl.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c index 1805455..723019d 100644 --- a/arch/arm/mach-zynq/spl.c +++ b/arch/arm/mach-zynq/spl.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include +#include #include #include @@ -18,6 +19,11 @@ void board_init_f(ulong dummy) ps7_init(); arch_cpu_init(); + /* + * The debug UART can be used from this point: + * debug_uart_init(); + * printch('x'); + */ } #ifdef CONFIG_SPL_BOARD_INIT -- cgit v1.1 From 71556fbcbfb8918c093bcb0095dcaf12fa29e0dc Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 17 Oct 2015 19:41:23 -0600 Subject: dm: arm: zynq: Enable device tree control in SPL Move to using device tree control in SPL so that we can use the same driver code in both SPL and U-Boot proper. Signed-off-by: Simon Glass Signed-off-by: Michal Simek --- arch/arm/Kconfig | 3 +++ arch/arm/mach-zynq/u-boot-spl.lds | 10 +++++++++- 2 files changed, 12 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3992f69..97b9647 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -543,9 +543,12 @@ config ARCH_ZYNQ select CPU_V7 select SUPPORT_SPL select OF_CONTROL + select SPL_OF_CONTROL select DM + select SPL_DM select DM_SPI select DM_SPI_FLASH + select SPL_SEPARATE_BSS config ARCH_ZYNQMP bool "Support Xilinx ZynqMP Platform" diff --git a/arch/arm/mach-zynq/u-boot-spl.lds b/arch/arm/mach-zynq/u-boot-spl.lds index 0f2f756..ecdf6a0 100644 --- a/arch/arm/mach-zynq/u-boot-spl.lds +++ b/arch/arm/mach-zynq/u-boot-spl.lds @@ -38,10 +38,18 @@ SECTIONS } > .sram . = ALIGN(4); +#ifdef CONFIG_SPL_DM + .u_boot_list : { + KEEP(*(SORT(.u_boot_list_*_driver_*))); + KEEP(*(SORT(.u_boot_list_*_uclass_*))); + } > .sram + + . = ALIGN(4); +#endif . = .; - __image_copy_end = .; + _image_binary_end = .; _end = .; -- cgit v1.1 From 035c6b271dba9cf3b6e389e84e876dea93cda088 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 17 Oct 2015 19:41:24 -0600 Subject: arm: zynq: dts: Add U-Boot device tree additions We need to mark some device tree nodes so that they are available before relocation. This enables driver model to find these automatically. In the case of SPL it ensures that these nodes will be retained in SPL. Signed-off-by: Simon Glass Signed-off-by: Michal Simek --- arch/arm/dts/zynq-7000.dtsi | 1 + arch/arm/dts/zynq-microzed.dts | 5 +++++ arch/arm/dts/zynq-picozed.dts | 5 +++++ arch/arm/dts/zynq-zc702.dts | 1 + arch/arm/dts/zynq-zc706.dts | 1 + arch/arm/dts/zynq-zc770-xm010.dts | 1 + arch/arm/dts/zynq-zc770-xm011.dts | 1 + arch/arm/dts/zynq-zc770-xm012.dts | 1 + arch/arm/dts/zynq-zc770-xm013.dts | 1 + arch/arm/dts/zynq-zed.dts | 1 + arch/arm/dts/zynq-zybo.dts | 1 + 11 files changed, 19 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 84c15b5..83be51a 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -54,6 +54,7 @@ }; amba: amba { + u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts index d5e0050..e841a1d 100644 --- a/arch/arm/dts/zynq-microzed.dts +++ b/arch/arm/dts/zynq-microzed.dts @@ -26,3 +26,8 @@ &qspi { status = "okay"; }; + +&uart1 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/arm/dts/zynq-picozed.dts b/arch/arm/dts/zynq-picozed.dts index 686b98f..3408df8 100644 --- a/arch/arm/dts/zynq-picozed.dts +++ b/arch/arm/dts/zynq-picozed.dts @@ -21,3 +21,8 @@ reg = <0 0x40000000>; }; }; + +&uart1 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index 4d86960..c417236 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -376,6 +376,7 @@ }; &uart1 { + u-boot,dm-pre-reloc; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index fc336ea..5088cfe 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -297,6 +297,7 @@ }; &uart1 { + u-boot,dm-pre-reloc; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index cf56ac8..07e2b7a 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -88,6 +88,7 @@ }; &uart1 { + u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts index f73c0dd..77e3bb0 100644 --- a/arch/arm/dts/zynq-zc770-xm011.dts +++ b/arch/arm/dts/zynq-zc770-xm011.dts @@ -55,6 +55,7 @@ }; &uart1 { + u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts index 4289e31..3e1769a 100644 --- a/arch/arm/dts/zynq-zc770-xm012.dts +++ b/arch/arm/dts/zynq-zc770-xm012.dts @@ -62,5 +62,6 @@ }; &uart1 { + u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index 5124cdc..288e248 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -75,5 +75,6 @@ }; &uart0 { + u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index 3630490..51d67d9 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -54,6 +54,7 @@ }; &uart1 { + u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts index 10f7815..dcfc00e 100644 --- a/arch/arm/dts/zynq-zybo.dts +++ b/arch/arm/dts/zynq-zybo.dts @@ -49,5 +49,6 @@ }; &uart1 { + u-boot,dm-pre-reloc; status = "okay"; }; -- cgit v1.1 From c2490bf546d0312674db2afb4ba117d4e48c9ac1 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Sat, 17 Oct 2015 19:41:25 -0600 Subject: ARM: zynqmp: Enable DM and OF binding SPI requires DM and OF that's why enable DM for ZynqMP and start to use configuration based on embedded OF. Signed-off-by: Michal Simek Signed-off-by: Simon Glass --- arch/arm/Kconfig | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 97b9647..fa51d62 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -553,6 +553,9 @@ config ARCH_ZYNQ config ARCH_ZYNQMP bool "Support Xilinx ZynqMP Platform" select ARM64 + select DM + select OF_CONTROL + select DM_SERIAL config TEGRA bool "NVIDIA Tegra" -- cgit v1.1 From 42800ffa7997082e2466c772bc2395dff0c95e3a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 17 Oct 2015 19:41:27 -0600 Subject: arm: zynq: Move serial driver to driver model Update this driver to use driver model and change all users. Signed-off-by: Simon Glass Signed-off-by: Michal Simek --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fa51d62..0d756cb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -547,6 +547,7 @@ config ARCH_ZYNQ select DM select SPL_DM select DM_SPI + select DM_SERIAL select DM_SPI_FLASH select SPL_SEPARATE_BSS -- cgit v1.1 From 1e370ef7e7a4fb0b801a848e190c01e06a2fbfce Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 30 Oct 2015 15:05:54 +0100 Subject: ARM: zynq: Remove zc70x target Remove zc70x target which was one setting for zc702 and zc706. Currently zc702 and zc706 are separated. Signed-off-by: Michal Simek Reviewed-by: Joe Hershberger --- arch/arm/mach-zynq/Kconfig | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index 7a1aec4..afe6cc3 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -21,13 +21,6 @@ config TARGET_ZYNQ_MICROZED config TARGET_ZYNQ_PICOZED bool "Zynq PicoZed" -config TARGET_ZYNQ_ZC70X - bool "Zynq ZC702/ZC706 Board (deprecated)" - select ZYNQ_CUSTOM_INIT - help - This option is deprecated. Use TARGET_ZYNQ_ZC702 - or TARGET_ZYNQ_706. - config TARGET_ZYNQ_ZC702 bool "Zynq ZC702 Board" @@ -57,8 +50,7 @@ config SYS_CONFIG_NAME default "zynq_zed" if TARGET_ZYNQ_ZED default "zynq_microzed" if TARGET_ZYNQ_MICROZED default "zynq_picozed" if TARGET_ZYNQ_PICOZED - default "zynq_zc70x" if TARGET_ZYNQ_ZC702 || TARGET_ZYNQ_ZC706 \ - || TARGET_ZYNQ_ZC70X + default "zynq_zc70x" if TARGET_ZYNQ_ZC702 || TARGET_ZYNQ_ZC706 default "zynq_zc770" if TARGET_ZYNQ_ZC770 default "zynq_zybo" if TARGET_ZYNQ_ZYBO -- cgit v1.1 From a55f28624e97e1e43ac333c39713b8b9435fcbd3 Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Sat, 17 Oct 2015 08:32:56 -0500 Subject: arm: dts: socfpga: Increase the spi-max-frequency for QSPI flash With a working QSPI calibration, the SCLK can now run up to 100MHz Signed-off-by: Chin Liang See Cc: Dinh Nguyen Cc: Dinh Nguyen Cc: Marek Vasut Cc: Stefan Roese Cc: Vikas Manocha Cc: Jagannadh Teki Cc: Pavel Machek Reviewed-by: Marek Vasut Acked-by: Marek Vasut Reviewed-by: Jagan Teki --- arch/arm/dts/socfpga_cyclone5_socdk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index 5465609..9eb5a22 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -89,7 +89,7 @@ #size-cells = <1>; compatible = "n25q00"; reg = <0>; /* chip select */ - spi-max-frequency = <50000000>; + spi-max-frequency = <100000000>; m25p,fast-read; page-size = <256>; block-size = <16>; /* 2^16, 64KB */ -- cgit v1.1 From 56adb7b30862f1abc2111132376fdb93da6a7563 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 5 Nov 2015 12:43:24 -0200 Subject: ARM: Use the generic bitops headers The generic bitops headers are required when calling logarithmic functions, such as ilog2(). Signed-off-by: Fabio Estevam Reviewed-by: Tom Rini Reviewed-by: Heiko Schocher Reviewed-by: Jagan Teki --- arch/arm/include/asm/bitops.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h index 9b78043..d479a38 100644 --- a/arch/arm/include/asm/bitops.h +++ b/arch/arm/include/asm/bitops.h @@ -190,4 +190,9 @@ found_middle: #endif /* __KERNEL__ */ +#include +#include +#include +#include + #endif /* _ARM_BITOPS_H */ -- cgit v1.1 From f8fdb81f6cbf9387fee7a8ab82b315798a7038ba Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 5 Nov 2015 12:43:39 -0200 Subject: compat: Remove is_power_of_2() definition Use the is_power_of_2() definition from log2.h to align with the kernel implementation. Signed-off-by: Fabio Estevam Reviewed-by: Tom Rini Reviewed-by: Heiko Schocher Reviewed-by: Jagan Teki --- arch/arm/mach-mvebu/mbus.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c index 771cce6..346278e 100644 --- a/arch/arm/mach-mvebu/mbus.c +++ b/arch/arm/mach-mvebu/mbus.c @@ -52,7 +52,7 @@ #include #include #include -#include +#include #include /* DDR target is the same on all platforms */ -- cgit v1.1 From e490ad25eb3dc4f075ed33b4b00b1f97071fcf3d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 5 Nov 2015 17:06:29 +0100 Subject: ARM64: zynqmp: Sync zynq_sdhci_init() declaration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch fix compilation error: drivers/mmc/zynq_sdhci.c:16:5: error: conflicting types for ‘zynq_sdhci_init’ int zynq_sdhci_init(phys_addr_t regbase) ^ In file included from drivers/mmc/zynq_sdhci.c:14:0: ./arch/arm/include/asm/arch/sys_proto.h:16:5: note: previous declaration of ‘zynq_sdhci_init’ was here int zynq_sdhci_init(unsigned long regbase); ^ Signed-off-by: Michal Simek --- arch/arm/include/asm/arch-zynqmp/sys_proto.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index f5c90d1..f1e95a2 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -13,7 +13,7 @@ static inline void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate) { } -int zynq_sdhci_init(unsigned long regbase); +int zynq_sdhci_init(phys_addr_t regbase); int zynq_slcr_get_mio_pin_status(const char *periph); unsigned int zynqmp_get_silicon_version(void); -- cgit v1.1 From 432a6241bdb70b98ead8f58bbf717d3f7fe699a8 Mon Sep 17 00:00:00 2001 From: Vadzim Dambrouski Date: Mon, 19 Oct 2015 19:40:14 +0300 Subject: arm: add support for semihosting for ARMv7M targets If you enable CONFIG_SEMIHOSTING for STM32F429 target, you will get compile error looking like this: arch/arm/lib/semihosting.c: In function 'smh_read': {standard input}: Assembler messages: {standard input}:34: Error: invalid swi expression {standard input}:34: Error: value of 1193046 too large for field of 2 bytes at 0 scripts/Makefile.build:277: recipe for target 'arch/arm/lib/semihosting.o' failed The source of the problem is "svc #0x123456" instruction. This instruction can not be encoded using Thumb2 instruction set used by ARMv7M CPUs. ARM documentation suggests using "bkpt #0xAB" instruction instead [1]. This patch fixes compile errors and adds support for semihosting for STM32F429 or any other ARMv7M target. This change was sested on STM32F429-DISCOVERY board using OpenOCD and "smhload" u-boot command. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471c/Bgbjhiea.html Signed-off-by: Vadzim Dambrouski --- arch/arm/lib/semihosting.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c index c3e964e..ed5e8e4 100644 --- a/arch/arm/lib/semihosting.c +++ b/arch/arm/lib/semihosting.c @@ -31,6 +31,8 @@ static noinline long smh_trap(unsigned int sysnum, void *addr) register long result asm("r0"); #if defined(CONFIG_ARM64) asm volatile ("hlt #0xf000" : "=r" (result) : "0"(sysnum), "r"(addr)); +#elif defined(CONFIG_CPU_V7M) + asm volatile ("bkpt #0xAB" : "=r" (result) : "0"(sysnum), "r"(addr)); #else /* Note - untested placeholder */ asm volatile ("svc #0x123456" : "=r" (result) : "0"(sysnum), "r"(addr)); -- cgit v1.1 From 7bdf75ca5cf253276e3cfcf5af8da9029e50790f Mon Sep 17 00:00:00 2001 From: Vadzim Dambrouski Date: Mon, 19 Oct 2015 19:40:15 +0300 Subject: arm: fix compile warnings when semihosting is enabled on ARMv7M target. This patch fixes compile warnings like this: warning: format '%lu' expects argument of type 'long unsigned int', but argument 5 has type 'size_t' In C99 standard you can use %zu modifier to print size_t values. Signed-off-by: Vadzim Dambrouski --- arch/arm/lib/semihosting.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c index ed5e8e4..e32ad90 100644 --- a/arch/arm/lib/semihosting.c +++ b/arch/arm/lib/semihosting.c @@ -92,7 +92,7 @@ static long smh_read(long fd, void *memp, size_t len) size_t len; } read; - debug("%s: fd %ld, memp %p, len %lu\n", __func__, fd, memp, len); + debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len); read.fd = fd; read.memp = memp; @@ -106,7 +106,7 @@ static long smh_read(long fd, void *memp, size_t len) * hard to maintain partial read loops and such, just fail * with an error message. */ - printf("%s: ERROR ret %ld, fd %ld, len %lu memp %p\n", + printf("%s: ERROR ret %ld, fd %ld, len %zu memp %p\n", __func__, ret, fd, len, memp); return -1; } -- cgit v1.1 From 62e92077a8936e60087d55683538ee386cc673aa Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Fri, 23 Oct 2015 18:06:40 +0200 Subject: arm: support Thumb-1 with CONFIG_SYS_THUMB_BUILD When building a Thumb-1-only target with CONFIG_SYS_THUMB_BUILD, some files fail to build, most of the time because they include mcr instructions, which only exist for Thumb-2. This patch introduces a Kconfig option CONFIG_THUMB2 and uses it to select between Thumb-2 and ARM mode for the aforementioned files. Signed-off-by: Albert ARIBAUD --- arch/arm/Kconfig | 5 ++ arch/arm/cpu/arm926ejs/Makefile | 11 ++++ arch/arm/cpu/arm926ejs/cache.c | 5 ++ arch/arm/include/asm/cache.h | 4 ++ arch/arm/lib/Makefile | 24 +++++++++ arch/arm/lib/cache.c | 11 ++++ arch/arm/lib/memcpy.S | 4 +- arch/arm/lib/memset.S | 2 +- arch/arm/mach-orion5x/Makefile | 10 ++++ arch/arm/thumb1/include/asm/proc-armv/system.h | 69 ++++++++++++++++++++++++++ 10 files changed, 142 insertions(+), 3 deletions(-) create mode 100644 arch/arm/thumb1/include/asm/proc-armv/system.h (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0d756cb..5ab0254 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -10,6 +10,9 @@ config ARM64 config HAS_VBAR bool +config HAS_THUMB2 + bool + config CPU_ARM720T bool @@ -32,9 +35,11 @@ config CPU_ARM1176 config CPU_V7 bool select HAS_VBAR + select HAS_THUMB2 config CPU_V7M bool + select HAS_THUMB2 config CPU_PXA bool diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile index 63fa159..fe78922 100644 --- a/arch/arm/cpu/arm926ejs/Makefile +++ b/arch/arm/cpu/arm926ejs/Makefile @@ -20,3 +20,14 @@ obj-$(CONFIG_MX25) += mx25/ obj-$(CONFIG_MX27) += mx27/ obj-$(if $(filter mxs,$(SOC)),y) += mxs/ obj-$(if $(filter spear,$(SOC)),y) += spear/ + +# some files can only build in ARM or THUMB2, not THUMB1 + +ifdef CONFIG_SYS_THUMB_BUILD +ifndef CONFIG_HAS_THUMB2 + +CFLAGS_cpu.o := -marm +CFLAGS_cache.o := -marm + +endif +endif diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index e5c1a6a..2839c86 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -82,4 +82,9 @@ void flush_dcache_all(void) /* * Stub implementations for l2 cache operations */ + __weak void l2_cache_disable(void) {} + +#if defined CONFIG_SYS_THUMB_BUILD +__weak void invalidate_l2_cache(void) {} +#endif diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index a836e9f..1f63127 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -16,6 +16,9 @@ /* * Invalidate L2 Cache using co-proc instruction */ +#ifdef CONFIG_SYS_THUMB_BUILD +void invalidate_l2_cache(void); +#else static inline void invalidate_l2_cache(void) { unsigned int val=0; @@ -24,6 +27,7 @@ static inline void invalidate_l2_cache(void) : : "r" (val) : "cc"); isb(); } +#endif void l2_cache_enable(void); void l2_cache_disable(void); diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 2bdfaba..f3db7b5 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -60,3 +60,27 @@ obj-$(CONFIG_DEBUG_LL) += debug.o ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS))) extra-y += eabi_compat.o endif + +# some files can only build in ARM or THUMB2, not THUMB1 + +ifdef CONFIG_SYS_THUMB_BUILD +ifndef CONFIG_HAS_THUMB2 + +# for C files, just apend -marm, which will override previous -mthumb* + +CFLAGS_cache.o := -marm +CFLAGS_cache-cp15.o := -marm + +# For .S, drop -mthumb* and other thumb-related options. +# CFLAGS_REMOVE_* would not have an effet, so AFLAGS_REMOVE_* +# was implemented and is used here. +# Also, define ${target}_NO_THUMB_BUILD for these two targets +# so that the code knows it should not use Thumb. + +AFLAGS_REMOVE_memset.o := -mthumb -mthumb-interwork +AFLAGS_REMOVE_memcpy.o := -mthumb -mthumb-interwork +AFLAGS_memset.o := -DMEMSET_NO_THUMB_BUILD +AFLAGS_memcpy.o := -DMEMCPY_NO_THUMB_BUILD + +endif +endif diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index cd13db3..3bd8710 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -88,3 +88,14 @@ phys_addr_t noncached_alloc(size_t size, size_t align) return next; } #endif /* CONFIG_SYS_NONCACHED_MEMORY */ + +#if defined(CONFIG_SYS_THUMB_BUILD) +void invalidate_l2_cache(void) +{ + unsigned int val = 0; + + asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" + : : "r" (val) : "cc"); + isb(); +} +#endif diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S index eeaf003..7d9fc0f 100644 --- a/arch/arm/lib/memcpy.S +++ b/arch/arm/lib/memcpy.S @@ -13,7 +13,7 @@ #include #include -#ifdef CONFIG_SYS_THUMB_BUILD +#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMCPY_NO_THUMB_BUILD) #define W(instr) instr.w #else #define W(instr) instr @@ -62,7 +62,7 @@ /* Prototype: void *memcpy(void *dest, const void *src, size_t n); */ .syntax unified -#ifdef CONFIG_SYS_THUMB_BUILD +#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMCPY_NO_THUMB_BUILD) .thumb .thumb_func #endif diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S index 7208f20..df053a3 100644 --- a/arch/arm/lib/memset.S +++ b/arch/arm/lib/memset.S @@ -16,7 +16,7 @@ .align 5 .syntax unified -#ifdef CONFIG_SYS_THUMB_BUILD +#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMSET_NO_THUMB_BUILD) .thumb .thumb_func #endif diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index 546ebcb..33dcad4 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -16,3 +16,13 @@ obj-y += timer.o ifndef CONFIG_SKIP_LOWLEVEL_INIT obj-y += lowlevel_init.o endif + +# some files can only build in ARM or THUMB2, not THUMB1 + +ifdef CONFIG_SYS_THUMB_BUILD +ifndef CONFIG_HAS_THUMB2 + +CFLAGS_cpu.o := -marm + +endif +endif diff --git a/arch/arm/thumb1/include/asm/proc-armv/system.h b/arch/arm/thumb1/include/asm/proc-armv/system.h new file mode 100644 index 0000000..7dfbf3d --- /dev/null +++ b/arch/arm/thumb1/include/asm/proc-armv/system.h @@ -0,0 +1,69 @@ +/* + * Thumb-1 drop-in for the linux/include/asm-arm/proc-armv/system.h + * + * (C) Copyright 2015 + * Albert ARIBAUD + * + * The original file does not build in Thumb mode. However, in U-Boot + * we don't use interrupt context, so we can redefine these as empty + * memory barriers, which makes Thumb-1 compiler happy. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Use the same macro name as linux/include/asm-arm/proc-armv/system.h + * here, so that if the original ever gets included after us, it won't + * try to re-redefine anything. + */ + +#ifndef __ASM_PROC_SYSTEM_H +#define __ASM_PROC_SYSTEM_H + +/* + * Redefine all original macros with static inline functions containing + * a simple memory barrier, so that they produce the same instruction + * ordering constraints as their original counterparts. + * We use static inline functions rather than macros so that we can tell + * the compiler to not complain about unused arguments. + */ + +static inline void local_irq_save( + unsigned long flags __attribute__((unused))) +{ + __asm__ __volatile__ ("" : : : "memory"); +} + +static inline void local_irq_enable(void) +{ + __asm__ __volatile__ ("" : : : "memory"); +} + +static inline void local_irq_disable(void) +{ + __asm__ __volatile__ ("" : : : "memory"); +} + +static inline void __stf(void) +{ + __asm__ __volatile__ ("" : : : "memory"); +} + +static inline void __clf(void) +{ + __asm__ __volatile__ ("" : : : "memory"); +} + +static inline void local_save_flags( + unsigned long flags __attribute__((unused))) +{ + __asm__ __volatile__ ("" : : : "memory"); +} + +static inline void local_irq_restore( + unsigned long flags __attribute__((unused))) +{ + __asm__ __volatile__ ("" : : : "memory"); +} + +#endif /* __ASM_PROC_SYSTEM_H */ -- cgit v1.1 From e7de61b3e4a7335cd50f52b820d710f8bd50d684 Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Fri, 23 Oct 2015 18:06:42 +0200 Subject: kirkwood: support CONFIG_SYS_THUMB_BUILD Kirkwood files cpu.c and cache.c cannot build in Thumb state; force them in ARM state even under CONFIG_SYS_THUMB_BUILD. Signed-off-by: Albert ARIBAUD --- arch/arm/mach-kirkwood/Makefile | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index df4756e..5abcf70 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile @@ -9,3 +9,9 @@ obj-y = cpu.o obj-y += cache.o obj-y += mpp.o + +# cpu.o and cache.o contain CP15 instructions which cannot be run in +# Thumb state, so build them for ARM state even with CONFIG_SYS_THUMB_BUILD + +CFLAGS_cpu.o := -marm +CFLAGS_cache.o := -marm -- cgit v1.1 From 35629363733a8e68c61f6698eaaeffdf66d3ec65 Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Fri, 23 Oct 2015 18:06:43 +0200 Subject: Revive OpenRD targets Revert commit 7a2c1b13 which dropped OpenRD boards. Assume maintainership of OpenRD. Remove OpenRD from scrapyard. Switch OpenRD to generic board. Switch to Thumb build. Signed-off-by: Albert ARIBAUD --- arch/arm/mach-kirkwood/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index aab5d19..f7737bf 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -4,6 +4,9 @@ choice prompt "Marvell Kirkwood board select" optional +config TARGET_OPENRD + bool "Marvell OpenRD Board" + config TARGET_DREAMPLUG bool "DreamPlug Board" @@ -51,6 +54,7 @@ endchoice config SYS_SOC default "kirkwood" +source "board/Marvell/openrd/Kconfig" source "board/Marvell/dreamplug/Kconfig" source "board/Marvell/guruplug/Kconfig" source "board/Marvell/sheevaplug/Kconfig" -- cgit v1.1 From da58dec866161e8ce73957fea463a8caad695000 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 10 Nov 2015 01:06:16 +0000 Subject: Various Makefiles: Add SPDX-License-Identifier tags After consulting with some of the SPDX team, the conclusion is that Makefiles are worth adding SPDX-License-Identifier tags too, and most of ours have one. This adds tags to ones that lack them and converts a few that had full (or in one case, very partial) license blobs into the equivalent tag. Cc: Kate Stewart Signed-off-by: Tom Rini --- arch/arm/cpu/Makefile | 4 ++++ arch/arm/dts/Makefile | 4 ++++ arch/arm/mach-at91/Makefile | 4 ++++ arch/arm/mach-tegra/tegra114/Makefile | 12 +----------- arch/arm/mach-tegra/tegra30/Makefile | 12 +----------- arch/arm/mach-uniphier/bcu/Makefile | 4 ++++ arch/arm/mach-uniphier/boot-mode/Makefile | 4 ++++ arch/arm/mach-uniphier/clk/Makefile | 4 ++++ arch/arm/mach-uniphier/ddrphy/Makefile | 4 ++++ arch/arm/mach-uniphier/early-clk/Makefile | 4 ++++ arch/arm/mach-uniphier/early-pinctrl/Makefile | 4 ++++ arch/arm/mach-uniphier/init/Makefile | 4 ++++ arch/arm/mach-uniphier/memconf/Makefile | 4 ++++ arch/arm/mach-uniphier/pinctrl/Makefile | 4 ++++ arch/arm/mach-uniphier/pll/Makefile | 4 ++++ arch/arm/mach-uniphier/sbc/Makefile | 4 ++++ arch/arm/mach-uniphier/umc/Makefile | 4 ++++ 17 files changed, 62 insertions(+), 22 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile index 6bea3d3..950e680 100644 --- a/arch/arm/cpu/Makefile +++ b/arch/arm/cpu/Makefile @@ -1 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj- += dummy.o diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 910648c..9542fff 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 313eb47..30f2b49 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o ifneq ($(CONFIG_SPL_BUILD),) obj-$(CONFIG_AT91SAM9260) += sdram.o spl_at91.o diff --git a/arch/arm/mach-tegra/tegra114/Makefile b/arch/arm/mach-tegra/tegra114/Makefile index 7489f5f..ea7f7b7 100644 --- a/arch/arm/mach-tegra/tegra114/Makefile +++ b/arch/arm/mach-tegra/tegra114/Makefile @@ -1,17 +1,7 @@ # # Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. # -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . +# SPDX-License-Identifier: GPL-2.0 # obj-$(CONFIG_SPL_BUILD) += cpu.o diff --git a/arch/arm/mach-tegra/tegra30/Makefile b/arch/arm/mach-tegra/tegra30/Makefile index bc250de..d3d3b6e 100644 --- a/arch/arm/mach-tegra/tegra30/Makefile +++ b/arch/arm/mach-tegra/tegra30/Makefile @@ -1,17 +1,7 @@ # # Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. # -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . +# SPDX-License-Identifier: GPL-2.0 # obj-$(CONFIG_SPL_BUILD) += cpu.o diff --git a/arch/arm/mach-uniphier/bcu/Makefile b/arch/arm/mach-uniphier/bcu/Makefile index 5b95bda..b8b0323 100644 --- a/arch/arm/mach-uniphier/bcu/Makefile +++ b/arch/arm/mach-uniphier/bcu/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += bcu-ph1-sld3.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += bcu-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += bcu-ph1-ld4.o diff --git a/arch/arm/mach-uniphier/boot-mode/Makefile b/arch/arm/mach-uniphier/boot-mode/Makefile index 30c8874..0797d6e 100644 --- a/arch/arm/mach-uniphier/boot-mode/Makefile +++ b/arch/arm/mach-uniphier/boot-mode/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-y += boot-mode.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += boot-mode-ph1-sld3.o diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile index 4f397b9..bc0f27c 100644 --- a/arch/arm/mach-uniphier/clk/Makefile +++ b/arch/arm/mach-uniphier/clk/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += clk-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += clk-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += clk-ph1-pro4.o diff --git a/arch/arm/mach-uniphier/ddrphy/Makefile b/arch/arm/mach-uniphier/ddrphy/Makefile index e2d109d..d0f4bd3 100644 --- a/arch/arm/mach-uniphier/ddrphy/Makefile +++ b/arch/arm/mach-uniphier/ddrphy/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += ddrphy-training.o ddrphy-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += ddrphy-training.o ddrphy-ph1-pro4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += ddrphy-training.o ddrphy-ph1-sld8.o diff --git a/arch/arm/mach-uniphier/early-clk/Makefile b/arch/arm/mach-uniphier/early-clk/Makefile index 393ea96..3e1e1b2 100644 --- a/arch/arm/mach-uniphier/early-clk/Makefile +++ b/arch/arm/mach-uniphier/early-clk/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += early-clk-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += early-clk-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += early-clk-ph1-ld4.o diff --git a/arch/arm/mach-uniphier/early-pinctrl/Makefile b/arch/arm/mach-uniphier/early-pinctrl/Makefile index e497d28..3be71fb 100644 --- a/arch/arm/mach-uniphier/early-pinctrl/Makefile +++ b/arch/arm/mach-uniphier/early-pinctrl/Makefile @@ -1 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += early-pinctrl-ph1-sld3.o diff --git a/arch/arm/mach-uniphier/init/Makefile b/arch/arm/mach-uniphier/init/Makefile index 98833b5..ef80953 100644 --- a/arch/arm/mach-uniphier/init/Makefile +++ b/arch/arm/mach-uniphier/init/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-y += init.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += init-ph1-sld3.o diff --git a/arch/arm/mach-uniphier/memconf/Makefile b/arch/arm/mach-uniphier/memconf/Makefile index 42057a2..a152f61 100644 --- a/arch/arm/mach-uniphier/memconf/Makefile +++ b/arch/arm/mach-uniphier/memconf/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-y += memconf.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += memconf-ph1-sld3.o obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += memconf-proxstream2.o diff --git a/arch/arm/mach-uniphier/pinctrl/Makefile b/arch/arm/mach-uniphier/pinctrl/Makefile index 8517595..80a9cda 100644 --- a/arch/arm/mach-uniphier/pinctrl/Makefile +++ b/arch/arm/mach-uniphier/pinctrl/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += pinctrl-ph1-sld3.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o diff --git a/arch/arm/mach-uniphier/pll/Makefile b/arch/arm/mach-uniphier/pll/Makefile index d33f99e..ca88521 100644 --- a/arch/arm/mach-uniphier/pll/Makefile +++ b/arch/arm/mach-uniphier/pll/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += pll-init-ph1-sld3.o \ pll-spectrum-ph1-sld3.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += pll-init-ph1-ld4.o \ diff --git a/arch/arm/mach-uniphier/sbc/Makefile b/arch/arm/mach-uniphier/sbc/Makefile index db622d2..57eb44b 100644 --- a/arch/arm/mach-uniphier/sbc/Makefile +++ b/arch/arm/mach-uniphier/sbc/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += sbc-ph1-sld3.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += sbc-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += sbc-ph1-pro4.o diff --git a/arch/arm/mach-uniphier/umc/Makefile b/arch/arm/mach-uniphier/umc/Makefile index dd35e77..89b2dec 100644 --- a/arch/arm/mach-uniphier/umc/Makefile +++ b/arch/arm/mach-uniphier/umc/Makefile @@ -1,3 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += umc-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += umc-ph1-pro4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += umc-ph1-sld8.o -- cgit v1.1 From 4cd3246f2a3a3a5032edcaed3cf807dd916f0aea Mon Sep 17 00:00:00 2001 From: Vadzim Dambrouski Date: Fri, 23 Oct 2015 21:14:06 +0300 Subject: arm: stm32f4: fix a bug when only first sector gets erased flash_lock call is inside a for loop, so after the first iteration flash is locked and no more sectors can be erased. Move flash_lock out of the loop. Signed-off-by: Vadzim Dambrouski --- arch/arm/cpu/armv7m/stm32f4/flash.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7m/stm32f4/flash.c b/arch/arm/cpu/armv7m/stm32f4/flash.c index e5c6111..ae63790 100644 --- a/arch/arm/cpu/armv7m/stm32f4/flash.c +++ b/arch/arm/cpu/armv7m/stm32f4/flash.c @@ -114,9 +114,9 @@ int flash_erase(flash_info_t *info, int first, int last) ; clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER); - stm32f4_flash_lock(1); } + stm32f4_flash_lock(1); return 0; } -- cgit v1.1 From 43fb0e3926dc52d4618d172a388cb6750311193d Mon Sep 17 00:00:00 2001 From: Vadzim Dambrouski Date: Fri, 23 Oct 2015 21:14:07 +0300 Subject: arm: stm32f4: fix a bug when a random sector gets erased Old sector number is not being cleared from FLASH_CR register. For example when first erased sector was 001 and then you want to erase sector 010, sector 011 gets erased instead. This patch clears old sector number from FLASH_CR register before a new one is written. Signed-off-by: Vadzim Dambrouski --- arch/arm/cpu/armv7m/stm32f4/flash.c | 3 +++ arch/arm/include/asm/arch-stm32f4/stm32.h | 1 + 2 files changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7m/stm32f4/flash.c b/arch/arm/cpu/armv7m/stm32f4/flash.c index ae63790..dd058bd 100644 --- a/arch/arm/cpu/armv7m/stm32f4/flash.c +++ b/arch/arm/cpu/armv7m/stm32f4/flash.c @@ -97,6 +97,9 @@ int flash_erase(flash_info_t *info, int first, int last) while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY) ; + /* clear old sector number before writing a new one */ + clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SNB_MASK); + if (bank == 0) { setbits_le32(&STM32_FLASH->cr, (i << STM32_FLASH_CR_SNB_OFFSET)); diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h index 3ed3801..7ca6dc3 100644 --- a/arch/arm/include/asm/arch-stm32f4/stm32.h +++ b/arch/arm/include/asm/arch-stm32f4/stm32.h @@ -104,6 +104,7 @@ struct stm32_flash_regs { #define STM32_FLASH_CR_STRT (1 << 16) #define STM32_FLASH_CR_LOCK (1 << 31) #define STM32_FLASH_CR_SNB_OFFSET 3 +#define STM32_FLASH_CR_SNB_MASK (15 << STM32_FLASH_CR_SNB_OFFSET) enum clock { CLOCK_CORE, -- cgit v1.1 From 88f965d720b745431a1fbe9107c561b7f381026c Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 5 Oct 2015 12:08:59 -0600 Subject: armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORY The implementation of noncached_init() uses define MMU_SECTION_SIZE. Define this on ARM64. Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64). Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block size. The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform! Signed-off-by: Stephen Warren --- arch/arm/include/asm/system.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index cfc7834..71b3108 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -17,6 +17,7 @@ #define PGTABLE_SIZE (0x10000) /* 2MB granularity */ #define MMU_SECTION_SHIFT 21 +#define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT) #ifndef __ASSEMBLY__ @@ -278,11 +279,6 @@ enum { */ void mmu_page_table_flush(unsigned long start, unsigned long stop); -#ifdef CONFIG_SYS_NONCACHED_MEMORY -void noncached_init(void); -phys_addr_t noncached_alloc(size_t size, size_t align); -#endif /* CONFIG_SYS_NONCACHED_MEMORY */ - #endif /* __ASSEMBLY__ */ #define arch_align_stack(x) (x) @@ -302,6 +298,11 @@ phys_addr_t noncached_alloc(size_t size, size_t align); void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, enum dcache_option option); +#ifdef CONFIG_SYS_NONCACHED_MEMORY +void noncached_init(void); +phys_addr_t noncached_alloc(size_t size, size_t align); +#endif /* CONFIG_SYS_NONCACHED_MEMORY */ + #endif /* __ASSEMBLY__ */ #endif -- cgit v1.1 From 3c6af3bad4f644e050f67146f4a6e177d5e39e76 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 5 Oct 2015 12:09:00 -0600 Subject: armv8: allow custom MMU setup routines on ARMv8 In order for noncached_init() to operate correctly, SoCs must set up a custom page table with fine-grained (2MiB) sections, which can be configured from noncached_init(). This is currently performed by arch/arm/cpu/armv8/{fsl-lsch3,zynqmp}/cpu.c by cut/pasting and re-implementing mmu_setup, enable_caches(), etc. There are some other reasons for the duplication there though, such as enabling icache early, and enabling dcaching earlier with a different configuration. This change makes mmu_setup() a weak implementation, so that the MMU setup code can be replaced without having to duplicate other code that calls it. Signed-off-by: Stephen Warren --- arch/arm/cpu/armv8/cache_v8.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index b1ea822..1ece6a2 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -32,7 +32,7 @@ inline void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr) } /* to activate the MMU we need to set up virtual memory */ -static void mmu_setup(void) +__weak void mmu_setup(void) { bd_t *bd = gd->bd; u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j; -- cgit v1.1 From 376cb1a4531538a031f3875f0aab21f31f8f8c90 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 5 Oct 2015 12:09:01 -0600 Subject: ARM: tegra: add custom MMU setup on ARMv8 This sets up a fine-grained page table, which is a requirement for noncached_init() to operate correctly. MMU setup code currently exists in a number of places: - A version in the core ARMv8 support code that sets up page tables that use very large block sizes that CONFIG_SYS_NONCACHED_MEMORY doesn't support. - Enhanced versions for fsl-lsch3 and zynmq that set up finer grained page tables. Ideally, rather than duplicating the MMU setup code yet again this patch would instead consolidate all the different routines into the core ARMv8 code so that it supported all use-cases. However, this will require significant effort since there appear to be a number of discrepancies[1] between different versions of the code, and between the defines/values by some copies of the MMU setup code use and the architectural MMU documentation. Some reverse engineering will be required to determine the intent of the current code. [1] For example, in the core ARMv8 MMU setup code, three defines named TCR_EL[123]_IPS_BITS exist, but only one of them sets the IPS field and the others set a different field (T1SZ) in the page tables. As far as I can tell so far, there should be no need to set different values per exception level nor to modify the T1SZ field at all, since TTBR1 shouldn't be enabled anyway. Another example is inconsistent values for *_VA_BITS between the current core ARMv8 MMU setup code and the various SoC- specific MMU setup code. Another example is that asm/armv8/mmu.h's value for SECTION_SHIFT doesn't match asm/system.h's MMU_SECTION_SHIFT; research is needed to determine which code relies on which of those values and why, and whether fixing the incorrect value will cause any regression. Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/Makefile | 1 + arch/arm/mach-tegra/arm64-mmu.c | 131 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 132 insertions(+) create mode 100644 arch/arm/mach-tegra/arm64-mmu.c (limited to 'arch/arm') diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 75924ad..98431a9 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o obj-$(CONFIG_PWM_TEGRA) += pwm.o endif +obj-$(CONFIG_ARM64) += arm64-mmu.o obj-y += ap.o obj-y += board.o board2.o obj-y += cache.o diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c new file mode 100644 index 0000000..c227652 --- /dev/null +++ b/arch/arm/mach-tegra/arm64-mmu.c @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2014 - 2015 Xilinx, Inc. + * Michal Simek + * (This file derived from arch/arm/cpu/armv8/zynqmp/cpu.c) + * + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define SECTION_SHIFT_L1 30UL +#define SECTION_SHIFT_L2 21UL +#define BLOCK_SIZE_L0 0x8000000000UL +#define BLOCK_SIZE_L1 (1 << SECTION_SHIFT_L1) +#define BLOCK_SIZE_L2 (1 << SECTION_SHIFT_L2) + +#define TCR_TG1_4K (1 << 31) +#define TCR_EPD1_DISABLE (1 << 23) +#define TEGRA_VA_BITS 40 +#define TEGRA_TCR TCR_TG1_4K | \ + TCR_EPD1_DISABLE | \ + TCR_SHARED_OUTER | \ + TCR_SHARED_INNER | \ + TCR_IRGN_WBWA | \ + TCR_ORGN_WBWA | \ + TCR_T0SZ(TEGRA_VA_BITS) + +#define MEMORY_ATTR PMD_SECT_AF | PMD_SECT_INNER_SHARE | \ + PMD_ATTRINDX(MT_NORMAL) | \ + PMD_TYPE_SECT +#define DEVICE_ATTR PMD_SECT_AF | PMD_SECT_PXN | \ + PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_NGNRNE) | \ + PMD_TYPE_SECT + +/* 4K size is required to place 512 entries in each level */ +#define TLB_TABLE_SIZE 0x1000 + +/* + * This mmu table looks as below + * Level 0 table contains two entries to 512GB sizes. One is Level1 Table 0 + * and other Level1 Table1. + * Level1 Table0 contains entries for each 1GB from 0 to 511GB. + * Level1 Table1 contains entries for each 1GB from 512GB to 1TB. + * Level2 Table0, Level2 Table1, Level2 Table2 and Level2 Table3 contains + * entries for each 2MB starting from 0GB, 1GB, 2GB and 3GB respectively. + */ +void mmu_setup(void) +{ + int el; + u64 i, section_l1t0, section_l1t1; + u64 section_l2t0, section_l2t1, section_l2t2, section_l2t3; + u64 *level0_table = (u64 *)gd->arch.tlb_addr; + u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + TLB_TABLE_SIZE); + u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + (2 * TLB_TABLE_SIZE)); + u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE)); + u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + (4 * TLB_TABLE_SIZE)); + u64 *level2_table_2 = (u64 *)(gd->arch.tlb_addr + (5 * TLB_TABLE_SIZE)); + u64 *level2_table_3 = (u64 *)(gd->arch.tlb_addr + (6 * TLB_TABLE_SIZE)); + + /* Invalidate all table entries */ + memset(level0_table, 0, PGTABLE_SIZE); + + level0_table[0] = + (u64)level1_table_0 | PMD_TYPE_TABLE; + level0_table[1] = + (u64)level1_table_1 | PMD_TYPE_TABLE; + + /* + * set level 1 table 0, covering 0 to 512GB + * set level 1 table 1, covering 512GB to 1TB + */ + section_l1t0 = 0; + section_l1t1 = BLOCK_SIZE_L0; + + for (i = 0; i < 512; i++) { + level1_table_0[i] = section_l1t0; + if (i >= 4) + level1_table_0[i] |= MEMORY_ATTR; + level1_table_1[i] = section_l1t1; + level1_table_1[i] |= MEMORY_ATTR; + section_l1t0 += BLOCK_SIZE_L1; + section_l1t1 += BLOCK_SIZE_L1; + } + + level1_table_0[0] = + (u64)level2_table_0 | PMD_TYPE_TABLE; + level1_table_0[1] = + (u64)level2_table_1 | PMD_TYPE_TABLE; + level1_table_0[2] = + (u64)level2_table_2 | PMD_TYPE_TABLE; + level1_table_0[3] = + (u64)level2_table_3 | PMD_TYPE_TABLE; + + section_l2t0 = 0; + section_l2t1 = section_l2t0 + BLOCK_SIZE_L1; /* 1GB */ + section_l2t2 = section_l2t1 + BLOCK_SIZE_L1; /* 2GB */ + section_l2t3 = section_l2t2 + BLOCK_SIZE_L1; /* 3GB */ + + for (i = 0; i < 512; i++) { + level2_table_0[i] = section_l2t0 | DEVICE_ATTR; + level2_table_1[i] = section_l2t1 | DEVICE_ATTR; + level2_table_2[i] = section_l2t2 | MEMORY_ATTR; + level2_table_3[i] = section_l2t3 | MEMORY_ATTR; + section_l2t0 += BLOCK_SIZE_L2; + section_l2t1 += BLOCK_SIZE_L2; + section_l2t2 += BLOCK_SIZE_L2; + section_l2t3 += BLOCK_SIZE_L2; + } + + /* flush new MMU table */ + flush_dcache_range(gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + + /* point TTBR to the new table */ + el = current_el(); + set_ttbr_tcr_mair(el, gd->arch.tlb_addr, + TEGRA_TCR, MEMORY_ATTRIBUTES); + + set_sctlr(get_sctlr() | CR_M); +} + +u64 *arch_get_page_table(void) +{ + return (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE)); +} -- cgit v1.1 From 57e2c481c7a5a5a2e3d2831a4f20bd835178d6d7 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 4 Nov 2015 21:56:06 +0900 Subject: ARM: dts: uniphier: fix interrupt number of USB core for PH1-Pro4 The IRQ is not used in U-Boot, but this would be useful to sync device trees between Linux and U-Boot. Signed-off-by: Masahiro Yamada --- arch/arm/dts/uniphier-ph1-pro4.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi index a57f8ae..a11b628 100644 --- a/arch/arm/dts/uniphier-ph1-pro4.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi @@ -221,7 +221,7 @@ reg = <0x65c00000 0x100>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; - interrupts = <0 135 4>; + interrupts = <0 137 4>; }; pinctrl: pinctrl@5f801000 { -- cgit v1.1 From 2610b1362b7a6b7bb880d1aa4f7c960997305bc3 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 4 Nov 2015 21:56:07 +0900 Subject: ARM: dts: uniphier: add USB xHCI nodes for PH1-Pro5 and ProXstream2 This makes USB3.0 available on new SoCs/boards. Signed-off-by: Masahiro Yamada Reviewed-by: Simon Glass --- arch/arm/dts/uniphier-ph1-ld6b-ref.dts | 8 ++++++++ arch/arm/dts/uniphier-ph1-pro5-4kbox.dts | 4 ++++ arch/arm/dts/uniphier-ph1-pro5.dtsi | 18 ++++++++++++++++++ arch/arm/dts/uniphier-proxstream2-gentil.dts | 8 ++++++++ arch/arm/dts/uniphier-proxstream2-vodka.dts | 4 ++++ arch/arm/dts/uniphier-proxstream2.dtsi | 18 ++++++++++++++++++ 6 files changed, 60 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts index bd86f09..ccadd81 100644 --- a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts @@ -54,6 +54,14 @@ status = "okay"; }; +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + /* for U-boot only */ / { soc { diff --git a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts index 912bc27..52dd1f9 100644 --- a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts +++ b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts @@ -44,6 +44,10 @@ status = "okay"; }; +&usb1 { + status = "okay"; +}; + /* for U-boot only */ / { soc { diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi index a15c7b2..6f19bf8 100644 --- a/arch/arm/dts/uniphier-ph1-pro5.dtsi +++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi @@ -210,6 +210,24 @@ reg = <0x60001000 0x1000>, <0x60000100 0x100>; }; + + usb0: usb@65a00000 { + compatible = "socionext,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65a00000 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + interrupts = <0 134 4>; + }; + + usb1: usb@65c00000 { + compatible = "socionext,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65c00000 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>; + interrupts = <0 137 4>; + }; }; }; diff --git a/arch/arm/dts/uniphier-proxstream2-gentil.dts b/arch/arm/dts/uniphier-proxstream2-gentil.dts index 81d2385..d0af8ac 100644 --- a/arch/arm/dts/uniphier-proxstream2-gentil.dts +++ b/arch/arm/dts/uniphier-proxstream2-gentil.dts @@ -42,6 +42,14 @@ status = "okay"; }; +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + /* for U-boot only */ / { soc { diff --git a/arch/arm/dts/uniphier-proxstream2-vodka.dts b/arch/arm/dts/uniphier-proxstream2-vodka.dts index fba7b74..92d7404 100644 --- a/arch/arm/dts/uniphier-proxstream2-vodka.dts +++ b/arch/arm/dts/uniphier-proxstream2-vodka.dts @@ -42,6 +42,10 @@ status = "okay"; }; +&usb0 { + status = "okay"; +}; + /* for U-boot only */ / { soc { diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi index 8b496a7..cd0cf4e 100644 --- a/arch/arm/dts/uniphier-proxstream2.dtsi +++ b/arch/arm/dts/uniphier-proxstream2.dtsi @@ -235,6 +235,24 @@ reg = <0x60001000 0x1000>, <0x60000100 0x100>; }; + + usb0: usb@65a00000 { + compatible = "socionext,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65a00000 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; + interrupts = <0 134 4>; + }; + + usb1: usb@65c00000 { + compatible = "socionext,uniphier-xhci", "generic-xhci"; + status = "disabled"; + reg = <0x65c00000 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; + interrupts = <0 137 4>; + }; }; }; -- cgit v1.1 From b375219e732f044e7f48b676fa4e36e7c29d81e1 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 6 Nov 2015 22:16:30 +0900 Subject: ARM: uniphier: drop UniPhier specific SMP code The latest Linux can directly handle SMP operations for UniPhier SoCs without any help of U-boot. Drop the relevant code from U-boot. See commit b1e4006aeda8c8784029de17d47987c21ea75f6d ("ARM: uniphier: rework SMP operations to use trampoline code") in Linux Kernel. Signed-off-by: Masahiro Yamada Reviewed-by: Tom Rini --- arch/arm/mach-uniphier/Kconfig | 8 ----- arch/arm/mach-uniphier/lowlevel_init.S | 53 ---------------------------------- 2 files changed, 61 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 22ab798..9e6ac3a 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -3,12 +3,8 @@ if ARCH_UNIPHIER config SYS_CONFIG_NAME default "uniphier" -config UNIPHIER_SMP - bool - config ARCH_UNIPHIER_PH1_SLD3 bool "UniPhier PH1-sLD3 SoC" - select UNIPHIER_SMP help This enables support for UniPhier PH1-sLD3 SoC. @@ -20,7 +16,6 @@ config ARCH_UNIPHIER_PH1_LD4 config ARCH_UNIPHIER_PH1_PRO4 bool "UniPhier PH1-Pro4 SoC" - select UNIPHIER_SMP depends on !ARCH_UNIPHIER_PH1_SLD3 && \ !ARCH_UNIPHIER_PH1_LD4 && \ !ARCH_UNIPHIER_PH1_SLD8 @@ -35,7 +30,6 @@ config ARCH_UNIPHIER_PH1_SLD8 config ARCH_UNIPHIER_PH1_PRO5 bool "UniPhier PH1-Pro5 SoC" - select UNIPHIER_SMP depends on !ARCH_UNIPHIER_PH1_SLD3 && \ !ARCH_UNIPHIER_PH1_LD4 && \ !ARCH_UNIPHIER_PH1_SLD8 @@ -44,7 +38,6 @@ config ARCH_UNIPHIER_PH1_PRO5 config ARCH_UNIPHIER_PROXSTREAM2 bool "UniPhier ProXstream2 SoC" - select UNIPHIER_SMP depends on !ARCH_UNIPHIER_PH1_SLD3 && \ !ARCH_UNIPHIER_PH1_LD4 && \ !ARCH_UNIPHIER_PH1_SLD8 @@ -53,7 +46,6 @@ config ARCH_UNIPHIER_PROXSTREAM2 config ARCH_UNIPHIER_PH1_LD6B bool "UniPhier PH1-LD6b SoC" - select UNIPHIER_SMP depends on !ARCH_UNIPHIER_PH1_SLD3 && \ !ARCH_UNIPHIER_PH1_LD4 && \ !ARCH_UNIPHIER_PH1_SLD8 diff --git a/arch/arm/mach-uniphier/lowlevel_init.S b/arch/arm/mach-uniphier/lowlevel_init.S index 66cad42..5936045 100644 --- a/arch/arm/mach-uniphier/lowlevel_init.S +++ b/arch/arm/mach-uniphier/lowlevel_init.S @@ -44,59 +44,6 @@ ENTRY(lowlevel_init) bl enable_mmu -#ifdef CONFIG_UNIPHIER_SMP -secondary_startup: - /* - * Entry point for secondary CPUs - * - * The Boot ROM has already enabled MMU for the secondary CPUs as well - * as for the primary one. The MMU table embedded in the Boot ROM - * prohibits the DRAM access, so it is impossible to bring the - * secondary CPUs into DRAM directly. They must jump here into SPL, - * which is run on L2 cache. - * - * Boot Sequence - * [primary CPU] [secondary CPUs] - * start from Boot ROM start from Boot ROM - * jump to SPL sleep in Boot ROM - * kick secondaries ---(sev)---> jump to SPL - * jump to U-Boot main sleep in SPL - * jump to Linux - * kick secondaries ---(sev)---> jump to Linux - */ - - /* branch by CPU ID */ - mrc p15, 0, r0, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Register) - and r0, r0, #0x3 - cmp r0, #0x0 - beq primary_cpu - /* only for secondary CPUs */ - ldr r1, =ROM_BOOT_ROMRSV2 @ The last data access to L2 cache - mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) - orr r0, r0, #CR_I @ Enable ICache - bic r0, r0, #(CR_C | CR_M) @ MMU and Dcache must be disabled - mcr p15, 0, r0, c1, c0, 0 @ before jumping to Linux - mov r0, #0 - str r0, [r1] - b 1f - /* - * L2 cache is shared among all the CPUs and it might be disabled by - * the primary one. Before that, the following 5 lines must be cached - * on the Icaches of the secondary CPUs. - */ -0: wfe @ kicked by Linux -1: ldr r0, [r1] - cmp r0, #0 - bxne r0 @ r0: Linux entry for secondary CPUs - b 0b -primary_cpu: - ldr r1, =ROM_BOOT_ROMRSV2 - ldr r0, =secondary_startup - str r0, [r1] - ldr r0, [r1] @ make sure str is complete before sev - sev @ kick the secondary CPU -#endif - bl setup_init_ram @ RAM area for temporary stack pointer mov lr, r8 @ restore link -- cgit v1.1