From 586f2004644f441820cff256f3db0530fcb6404d Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 11 Mar 2016 17:28:00 +0800 Subject: ENGR00325255 pcie:enable pcie support on imx6sx sd Enable pcie support in uboot on imx6sx sd boards - enable_pcie_clock should be call before ssp_en is set, since that ssp_en control the phy_ref clk gate, turn on it after the source of the pcie clks are stable. - add debug info - add rx_eq of gpr12 on imx6sx - there are random link down issue on imx6sx. It's pcie ep reset issue. solution:reset ep, then retry link can fix it. (cherry picked from commit ec78595a24b5ff1020baa97b6d6e79a3a3326307) Signed-off-by: Richard Zhu Signed-off-by: Ye Li (cherry picked from commit 81fd30250110d72992758f08b66c07306126892b) --- arch/arm/cpu/armv7/mx6/clock.c | 27 ++++++++++++++++++++++----- arch/arm/cpu/armv7/mx6/soc.c | 10 ++++++++++ arch/arm/include/asm/imx-common/sys_proto.h | 3 +++ 3 files changed, 35 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 51e5211..a334f49 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -1166,6 +1166,15 @@ void disable_sata_clock(void) #endif #ifdef CONFIG_PCIE_IMX +static void ungate_disp_axi_clock(void) +{ + struct mxc_ccm_reg *const imx_ccm = + (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* Enable display axi clock. */ + setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_DISP_AXI_MASK); +} + static void ungate_pcie_clock(void) { struct mxc_ccm_reg *const imx_ccm = @@ -1213,14 +1222,22 @@ int enable_pcie_clock(void) /* PCIe reference clock sourced from AXI. */ clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL); - /* Party time! Ungate the clock to the PCIe. */ + if (!is_cpu_type(MXC_CPU_MX6SX)) { + /* Party time! Ungate the clock to the PCIe. */ #ifdef CONFIG_CMD_SATA - ungate_sata_clock(); + ungate_sata_clock(); #endif - ungate_pcie_clock(); + ungate_pcie_clock(); - return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA | - BM_ANADIG_PLL_ENET_ENABLE_PCIE); + return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA | + BM_ANADIG_PLL_ENET_ENABLE_PCIE); + } else { + /* Party time! Ungate the clock to the PCIe. */ + ungate_disp_axi_clock(); + ungate_pcie_clock(); + + return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_PCIE); + } } #endif diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 5e77d29..0a97f0d 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -406,6 +406,16 @@ void vadc_power_down(void) val &= ~IMX6SX_GPR5_CSI1_MUX_CTRL_MASK, writel(val, &iomux->gpr[5]); } + +void pcie_power_up(void) +{ + set_ldo_voltage(LDO_PU, 1100); /* Set VDDPU to 1.1V */ +} + +void pcie_power_off(void) +{ + set_ldo_voltage(LDO_PU, 0); /* Set VDDPU to 1.1V */ +} #endif static void set_uart_from_osc(void) diff --git a/arch/arm/include/asm/imx-common/sys_proto.h b/arch/arm/include/asm/imx-common/sys_proto.h index 3a58a25..660240a 100644 --- a/arch/arm/include/asm/imx-common/sys_proto.h +++ b/arch/arm/include/asm/imx-common/sys_proto.h @@ -72,4 +72,7 @@ void board_late_mmc_env_init(void); void vadc_power_up(void); void vadc_power_down(void); + +void pcie_power_up(void); +void pcie_power_off(void); #endif -- cgit v1.1