From 5bf1f1ed13a20571a9311a32323097f9fc4f57a7 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 14 Nov 2014 08:10:44 +0100 Subject: arm: socfpga: dts: Move to SPDX license identifiers The socfpga dts files are copied from the Rocketboards.org repository. In U-Boot we usually replace the full-blown license header text with the SPDX license identifiers. Lets do this for these new dts files as well. I just forgot to do this while adding the DT support for socfpga. Signed-off-by: Stefan Roese Cc: Marek Vasut Acked-by: Pavel Machek Cc: Chin Liang See Cc: Dinh Nguyen Cc: Vince Bridgers --- arch/arm/dts/socfpga.dtsi | 13 +------------ arch/arm/dts/socfpga_cyclone5.dtsi | 13 +------------ arch/arm/dts/socfpga_cyclone5_socrates.dts | 13 +------------ 3 files changed, 3 insertions(+), 36 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index 4472fd9..bca6832 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -1,18 +1,7 @@ /* * Copyright (C) 2012 Altera * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * SPDX-License-Identifier: GPL-2.0+ */ #include "skeleton.dtsi" diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi b/arch/arm/dts/socfpga_cyclone5.dtsi index 28c05e7..234a901 100644 --- a/arch/arm/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/dts/socfpga_cyclone5.dtsi @@ -1,18 +1,7 @@ /* * Copyright (C) 2012 Altera Corporation * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index a1814b4..0454108 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -1,18 +1,7 @@ /* * Copyright (C) 2014 Steffen Trumtrar * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * SPDX-License-Identifier: GPL-2.0+ */ #include "socfpga_cyclone5.dtsi" -- cgit v1.1 From 881f6a448fc0005157f85bfc7c4a1d2e26bef90d Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 7 Nov 2014 12:37:50 +0100 Subject: arm: socfpga: dts: Add Cadence QSPI DT node to socfpga.dtsi This DT node is taken from the Rocketboard.org Linux repsitory. And is needed to enable (configure) the Cadence DM SPI driver. Signed-off-by: Stefan Roese Cc: Chin Liang See Cc: Dinh Nguyen Cc: Vince Bridgers Cc: Marek Vasut Cc: Pavel Machek Cc: Simon Glass Cc: Jagannadha Sutradharudu Teki --- arch/arm/dts/socfpga.dtsi | 15 +++++++++++++++ arch/arm/dts/socfpga_cyclone5_socrates.dts | 20 ++++++++++++++++++++ 2 files changed, 35 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index bca6832..145e125 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -628,6 +628,21 @@ clock-names = "biu", "ciu"; }; + qspi: spi@ff705000 { + compatible = "cadence,qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff705000 0x1000>, + <0xffa00000 0x1000>; + interrupts = <0 151 4>; + clocks = <&qspi_clk>; + ext-decoder = <0>; /* external decoder */ + num-chipselect = <4>; + fifo-depth = <128>; + bus-num = <2>; + status = "disabled"; + }; + /* Local timer */ timer@fffec600 { compatible = "arm,cortex-a9-twd-timer"; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index 0454108..00b1830 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -37,3 +37,23 @@ &mmc { status = "okay"; }; + +&qspi { + status = "okay"; + + flash0: n25q00@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00"; + reg = <0>; /* chip select */ + spi-max-frequency = <50000000>; + m25p,fast-read; + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + read-delay = <4>; /* delay value in read data capture register */ + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + }; +}; -- cgit v1.1 From 60896653d5b4baa097b29295dd3f860addfd11bb Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 7 Nov 2014 12:37:51 +0100 Subject: arm: socfpga: dts: Add spi0 alias for Cadence QSPI driver Without this alias, DM based probing does not work. So lets add this alias to get the bus numbering correct. Signed-off-by: Stefan Roese Cc: Chin Liang See Cc: Dinh Nguyen Cc: Vince Bridgers Cc: Marek Vasut Cc: Pavel Machek Cc: Simon Glass Cc: Jagannadha Sutradharudu Teki --- arch/arm/dts/socfpga_cyclone5_socrates.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index 00b1830..7e2a565 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -14,6 +14,10 @@ bootargs = "console=ttyS0,115200"; }; + aliases { + spi0 = "/spi@ff705000"; /* QSPI */ + }; + memory { name = "memory"; device_type = "memory"; -- cgit v1.1 From ae79e2d2982afabd43c2121fe1c40460547a5347 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 7 Nov 2014 13:50:32 +0100 Subject: arm: socfpga: dts: Add spi0/1 dts nodes for the Designware master SPI devices Signed-off-by: Stefan Roese Cc: Chin Liang See Cc: Dinh Nguyen Cc: Vince Bridgers Cc: Marek Vasut Acked-by: Pavel Machek --- arch/arm/dts/socfpga.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index 145e125..969e5ad 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -643,6 +643,34 @@ status = "disabled"; }; + spi0: spi@fff00000 { + compatible = "snps,dw-spi-mmio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfff00000 0x1000>; + interrupts = <0 154 4>; + num-chipselect = <4>; + bus-num = <0>; + tx-dma-channel = <&pdma 16>; + rx-dma-channel = <&pdma 17>; + clocks = <&per_base_clk>; + status = "disabled"; + }; + + spi1: spi@fff01000 { + compatible = "snps,dw-spi-mmio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfff01000 0x1000>; + interrupts = <0 156 4>; + num-chipselect = <4>; + bus-num = <1>; + tx-dma-channel = <&pdma 20>; + rx-dma-channel = <&pdma 21>; + clocks = <&per_base_clk>; + status = "disabled"; + }; + /* Local timer */ timer@fffec600 { compatible = "arm,cortex-a9-twd-timer"; -- cgit v1.1 From 369164042eb80cae88e141866ebba407b00ad2a5 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 7 Nov 2014 13:50:33 +0100 Subject: arm: socfpga: dts: socrates: Add spi1/2 aliases needed DM SPI probing Without this alias, DM based probing does not work. So lets add this alias to get the bus numbering correct for the Designware SPI controllers. Signed-off-by: Stefan Roese Cc: Chin Liang See Cc: Dinh Nguyen Cc: Vince Bridgers Cc: Marek Vasut Acked-by: Pavel Machek --- arch/arm/dts/socfpga_cyclone5_socrates.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index 7e2a565..ea30483 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -16,6 +16,8 @@ aliases { spi0 = "/spi@ff705000"; /* QSPI */ + spi1 = "/spi@fff00000"; + spi2 = "/spi@fff01000"; }; memory { -- cgit v1.1 From c877eaa8a04858c23ce7ebb82c59f7cf838545ef Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sun, 16 Nov 2014 12:46:59 +0100 Subject: arm: socfpga: Use only one clrbits_le32 call to deassert SPI reset bits As suggested by Pavel, lets combine the two calls into one. Signed-off-by: Stefan Roese Cc: Chin Liang See Cc: Dinh Nguyen Cc: Vince Bridgers Cc: Marek Vasut Acked-by: Pavel Machek --- arch/arm/cpu/armv7/socfpga/reset_manager.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c index af9db85..25921e7 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -110,6 +110,6 @@ void socfpga_spim_enable(void) { const void *reset = &reset_manager_base->per_mod_reset; - clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB); - clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB); + clrbits_le32(reset, (1 << RSTMGR_PERMODRST_SPIM0_LSB) | + (1 << RSTMGR_PERMODRST_SPIM1_LSB)); } -- cgit v1.1 From 481549f8c1fa3a40729d0ff15c25380a043b6d41 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sun, 16 Nov 2014 12:47:00 +0100 Subject: arm: socfpga: Add missing DW master SPI clock prototyp to clock_manager.h Signed-off-by: Stefan Roese Cc: Chin Liang See Cc: Dinh Nguyen Cc: Vince Bridgers Cc: Marek Vasut Acked-by: Pavel Machek --- arch/arm/include/asm/arch-socfpga/clock_manager.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/arch-socfpga/clock_manager.h b/arch/arm/include/asm/arch-socfpga/clock_manager.h index fa49f6a..5449726 100644 --- a/arch/arm/include/asm/arch-socfpga/clock_manager.h +++ b/arch/arm/include/asm/arch-socfpga/clock_manager.h @@ -14,6 +14,7 @@ unsigned long cm_get_sdram_clk_hz(void); unsigned int cm_get_l4_sp_clk_hz(void); unsigned int cm_get_mmc_controller_clk_hz(void); unsigned int cm_get_qspi_controller_clk_hz(void); +unsigned int cm_get_spi_controller_clk_hz(void); #endif typedef struct { -- cgit v1.1 From 5d2f930de0e5222957e103c8eb5df2b7238dd4b4 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 26 Nov 2014 12:14:32 -0600 Subject: socfpga: add missing struct member fifo_triple_byte socfpga_scan_manager structure was missing a data member. Signed-off-by: Dinh Nguyen Cc: Vince Bridgers Cc: Chin Liang See Cc: Marek Vasut Acked-by: Pavel Machek Cc: Wolfgang Denk --- arch/arm/include/asm/arch-socfpga/scan_manager.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/arch-socfpga/scan_manager.h b/arch/arm/include/asm/arch-socfpga/scan_manager.h index b2686d3..1155fd3 100644 --- a/arch/arm/include/asm/arch-socfpga/scan_manager.h +++ b/arch/arm/include/asm/arch-socfpga/scan_manager.h @@ -13,6 +13,7 @@ struct socfpga_scan_manager { u32 padding[2]; u32 fifo_single_byte; u32 fifo_double_byte; + u32 fifo_triple_byte; u32 fifo_quad_byte; }; -- cgit v1.1 From b9b5cf0ea3c5c141f31cc0c4c8edebbfd9ff5866 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 26 Nov 2014 12:14:33 -0600 Subject: socfpga: correctly increment freeze_controller_base address Correctly increment the base address of the freeze controller. And since SYSMGR_FRZCTRL_VIOCTRL_SHIFT is not needed, remove it from the include file. Signed-off-by: Dinh Nguyen Cc: Vince Bridgers Cc: Chin Liang See Cc: Marek Vasut Acked-by: Pavel Machek Cc: Wolfgang Denk --- arch/arm/cpu/armv7/socfpga/freeze_controller.c | 6 ++---- arch/arm/include/asm/arch-socfpga/freeze_controller.h | 1 - 2 files changed, 2 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/socfpga/freeze_controller.c b/arch/arm/cpu/armv7/socfpga/freeze_controller.c index b8c9bce..0be643c 100644 --- a/arch/arm/cpu/armv7/socfpga/freeze_controller.c +++ b/arch/arm/cpu/armv7/socfpga/freeze_controller.c @@ -38,8 +38,7 @@ void sys_mgr_frzctrl_freeze_req(void) /* Freeze channel 0 to 2 */ for (channel_id = 0; channel_id <= 2; channel_id++) { ioctrl_reg_offset = (u32)( - &freeze_controller_base->vioctrl + - (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT)); + &freeze_controller_base->vioctrl + channel_id); /* * Assert active low enrnsl, plniotri @@ -120,8 +119,7 @@ void sys_mgr_frzctrl_thaw_req(void) /* Thaw channel 0 to 2 */ for (channel_id = 0; channel_id <= 2; channel_id++) { ioctrl_reg_offset - = (u32)(&freeze_controller_base->vioctrl - + (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT)); + = (u32)(&freeze_controller_base->vioctrl + channel_id); /* * Assert active low bhniotri signal and diff --git a/arch/arm/include/asm/arch-socfpga/freeze_controller.h b/arch/arm/include/asm/arch-socfpga/freeze_controller.h index 120f20e..f19ad87 100644 --- a/arch/arm/include/asm/arch-socfpga/freeze_controller.h +++ b/arch/arm/include/asm/arch-socfpga/freeze_controller.h @@ -42,7 +42,6 @@ typedef enum { #define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001 #define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2 #define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1 -#define SYSMGR_FRZCTRL_VIOCTRL_SHIFT 0x2 void sys_mgr_frzctrl_freeze_req(void); void sys_mgr_frzctrl_thaw_req(void); -- cgit v1.1