From 8475c869c30cbeef1695396b43bc240cc0d35f5a Mon Sep 17 00:00:00 2001
From: Przemyslaw Marczak
Date: Wed, 22 Jan 2014 11:24:10 +0100
Subject: s5p: gpio: change gpio coding method for s5p gpio.
Old s5p gpio coding method was not clean and was not working properly
for all parts and banks. New method is clean and easy to extend.
Gpio coding mask:
0x000000ff - pin number
0x00ffff00 - bank offset
0xff000000 - part number
Signed-off-by: Przemyslaw Marczak
Signed-off-by: Minkyu Kang
---
arch/arm/include/asm/arch-exynos/gpio.h | 245 +++++++++----------------------
arch/arm/include/asm/arch-s5pc1xx/gpio.h | 47 ++++--
2 files changed, 109 insertions(+), 183 deletions(-)
(limited to 'arch/arm')
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h
index 2a19852..d6868fa 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -247,180 +247,81 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
/* GPIO pins per bank */
#define GPIO_PER_BANK 8
-
-#define exynos4_gpio_part1_get_nr(bank, pin) \
- ((((((unsigned int) &(((struct exynos4_gpio_part1 *) \
- EXYNOS4_GPIO_PART1_BASE)->bank)) \
- - EXYNOS4_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin)
-
-#define EXYNOS4_GPIO_PART1_MAX ((sizeof(struct exynos4_gpio_part1) \
- / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos4_gpio_part2_get_nr(bank, pin) \
- (((((((unsigned int) &(((struct exynos4_gpio_part2 *) \
- EXYNOS4_GPIO_PART2_BASE)->bank)) \
- - EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX)
-
-#define exynos4x12_gpio_part1_get_nr(bank, pin) \
- ((((((unsigned int) &(((struct exynos4x12_gpio_part1 *) \
- EXYNOS4X12_GPIO_PART1_BASE)->bank)) \
- - EXYNOS4X12_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin)
-
-#define EXYNOS4X12_GPIO_PART1_MAX ((sizeof(struct exynos4x12_gpio_part1) \
- / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos4x12_gpio_part2_get_nr(bank, pin) \
- (((((((unsigned int) &(((struct exynos4x12_gpio_part2 *) \
- EXYNOS4X12_GPIO_PART2_BASE)->bank)) \
- - EXYNOS4X12_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART1_MAX)
-
-#define EXYNOS4X12_GPIO_PART2_MAX ((sizeof(struct exynos4x12_gpio_part2) \
- / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos4x12_gpio_part3_get_nr(bank, pin) \
- (((((((unsigned int) &(((struct exynos4x12_gpio_part3 *) \
- EXYNOS4X12_GPIO_PART3_BASE)->bank)) \
- - EXYNOS4X12_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART2_MAX)
-
-#define exynos5_gpio_part1_get_nr(bank, pin) \
- ((((((unsigned int) &(((struct exynos5_gpio_part1 *) \
- EXYNOS5_GPIO_PART1_BASE)->bank)) \
- - EXYNOS5_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin)
-
-#define EXYNOS5_GPIO_PART1_MAX ((sizeof(struct exynos5_gpio_part1) \
- / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos5_gpio_part2_get_nr(bank, pin) \
- (((((((unsigned int) &(((struct exynos5_gpio_part2 *) \
- EXYNOS5_GPIO_PART2_BASE)->bank)) \
- - EXYNOS5_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART1_MAX)
-
-#define EXYNOS5_GPIO_PART2_MAX ((sizeof(struct exynos5_gpio_part2) \
- / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos5_gpio_part3_get_nr(bank, pin) \
- (((((((unsigned int) &(((struct exynos5_gpio_part3 *) \
- EXYNOS5_GPIO_PART3_BASE)->bank)) \
- - EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX)
-
-
-/* EXYNOS5420 */
-#define exynos5420_gpio_part1_get_nr(bank, pin) \
- ((((((unsigned int) &(((struct exynos5420_gpio_part1 *)\
- EXYNOS5420_GPIO_PART1_BASE)->bank)) \
- - EXYNOS5420_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin)
-
-#define EXYNOS5420_GPIO_PART1_MAX ((sizeof(struct exynos5420_gpio_part1) \
- / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos5420_gpio_part2_get_nr(bank, pin) \
- (((((((unsigned int) &(((struct exynos5420_gpio_part2 *)\
- EXYNOS5420_GPIO_PART2_BASE)->bank)) \
- - EXYNOS5420_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART1_MAX)
-
-#define EXYNOS5420_GPIO_PART2_MAX ((sizeof(struct exynos5420_gpio_part2) \
- / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos5420_gpio_part3_get_nr(bank, pin) \
- (((((((unsigned int) &(((struct exynos5420_gpio_part3 *)\
- EXYNOS5420_GPIO_PART3_BASE)->bank)) \
- - EXYNOS5420_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART2_MAX)
-
-#define EXYNOS5420_GPIO_PART3_MAX ((sizeof(struct exynos5420_gpio_part3) \
- / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define exynos5420_gpio_part4_get_nr(bank, pin) \
- (((((((unsigned int) &(((struct exynos5420_gpio_part4 *)\
- EXYNOS5420_GPIO_PART4_BASE)->bank)) \
- - EXYNOS5420_GPIO_PART4_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART3_MAX)
-
-#define EXYNOS5420_GPIO_PART4_MAX ((sizeof(struct exynos5420_gpio_part4) \
- / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define EXYNOS5420_GPIO_PART5_MAX ((sizeof(struct exynos5420_gpio_part5) \
- / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-static inline unsigned int s5p_gpio_base(int nr)
+#define S5P_GPIO_PART_SHIFT (24)
+#define S5P_GPIO_PART_MASK (0xff)
+#define S5P_GPIO_BANK_SHIFT (8)
+#define S5P_GPIO_BANK_MASK (0xffff)
+#define S5P_GPIO_PIN_MASK (0xff)
+
+#define S5P_GPIO_SET_PART(x) \
+ (((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT)
+
+#define S5P_GPIO_GET_PART(x) \
+ (((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK)
+
+#define S5P_GPIO_SET_PIN(x) \
+ ((x) & S5P_GPIO_PIN_MASK)
+
+#define EXYNOS4_GPIO_SET_BANK(part, bank) \
+ ((((unsigned)&(((struct exynos4_gpio_part##part *) \
+ EXYNOS4_GPIO_PART##part##_BASE)->bank) \
+ - EXYNOS4_GPIO_PART##part##_BASE) \
+ & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define EXYNOS4X12_GPIO_SET_BANK(part, bank) \
+ ((((unsigned)&(((struct exynos4x12_gpio_part##part *) \
+ EXYNOS4X12_GPIO_PART##part##_BASE)->bank) \
+ - EXYNOS4X12_GPIO_PART##part##_BASE) \
+ & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define EXYNOS5_GPIO_SET_BANK(part, bank) \
+ ((((unsigned)&(((struct exynos5420_gpio_part##part *) \
+ EXYNOS5420_GPIO_PART##part##_BASE)->bank) \
+ - EXYNOS5_GPIO_PART##part##_BASE) \
+ & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define EXYNOS5420_GPIO_SET_BANK(part, bank) \
+ ((((unsigned)&(((struct exynos5420_gpio_part##part *) \
+ EXYNOS5420_GPIO_PART##part##_BASE)->bank) \
+ - EXYNOS5420_GPIO_PART##part##_BASE) \
+ & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define exynos4_gpio_get(part, bank, pin) \
+ (S5P_GPIO_SET_PART(part) | \
+ EXYNOS4_GPIO_SET_BANK(part, bank) | \
+ S5P_GPIO_SET_PIN(pin))
+
+#define exynos4x12_gpio_get(part, bank, pin) \
+ (S5P_GPIO_SET_PART(part) | \
+ EXYNOS4X12_GPIO_SET_BANK(part, bank) | \
+ S5P_GPIO_SET_PIN(pin))
+
+#define exynos5420_gpio_get(part, bank, pin) \
+ (S5P_GPIO_SET_PART(part) | \
+ EXYNOS5420_GPIO_SET_BANK(part, bank) | \
+ S5P_GPIO_SET_PIN(pin))
+
+#define exynos5_gpio_get(part, bank, pin) \
+ (S5P_GPIO_SET_PART(part) | \
+ EXYNOS5_GPIO_SET_BANK(part, bank) | \
+ S5P_GPIO_SET_PIN(pin))
+
+static inline unsigned int s5p_gpio_base(int gpio)
{
- if (cpu_is_exynos5()) {
- if (proid_is_exynos5420()) {
- if (nr < EXYNOS5420_GPIO_PART1_MAX)
- return EXYNOS5420_GPIO_PART1_BASE;
- else if (nr < EXYNOS5420_GPIO_PART2_MAX)
- return EXYNOS5420_GPIO_PART2_BASE;
- else if (nr < EXYNOS5420_GPIO_PART3_MAX)
- return EXYNOS5420_GPIO_PART3_BASE;
- else
- return EXYNOS5420_GPIO_PART4_BASE;
- } else {
- if (nr < EXYNOS5_GPIO_PART1_MAX)
- return EXYNOS5_GPIO_PART1_BASE;
- else if (nr < EXYNOS5_GPIO_PART2_MAX)
- return EXYNOS5_GPIO_PART2_BASE;
- else
- return EXYNOS5_GPIO_PART3_BASE;
- }
- } else if (cpu_is_exynos4()) {
- if (nr < EXYNOS4_GPIO_PART1_MAX)
- return EXYNOS4_GPIO_PART1_BASE;
- else
- return EXYNOS4_GPIO_PART2_BASE;
+ unsigned gpio_part = S5P_GPIO_GET_PART(gpio);
+
+ switch (gpio_part) {
+ case 1:
+ return samsung_get_base_gpio_part1();
+ case 2:
+ return samsung_get_base_gpio_part2();
+ case 3:
+ return samsung_get_base_gpio_part3();
+ case 4:
+ return samsung_get_base_gpio_part4();
+ default:
+ return 0;
}
-
- return 0;
-}
-
-static inline unsigned int s5p_gpio_part_max(int nr)
-{
- if (cpu_is_exynos5()) {
- if (proid_is_exynos5420()) {
- if (nr < EXYNOS5420_GPIO_PART1_MAX)
- return 0;
- else if (nr < EXYNOS5420_GPIO_PART2_MAX)
- return EXYNOS5420_GPIO_PART1_MAX;
- else if (nr < EXYNOS5420_GPIO_PART3_MAX)
- return EXYNOS5420_GPIO_PART2_MAX;
- else if (nr < EXYNOS5420_GPIO_PART4_MAX)
- return EXYNOS5420_GPIO_PART3_MAX;
- else
- return EXYNOS5420_GPIO_PART4_MAX;
- } else {
- if (nr < EXYNOS5_GPIO_PART1_MAX)
- return 0;
- else if (nr < EXYNOS5_GPIO_PART2_MAX)
- return EXYNOS5_GPIO_PART1_MAX;
- else
- return EXYNOS5_GPIO_PART2_MAX;
- }
- } else if (cpu_is_exynos4()) {
- if (proid_is_exynos4412()) {
- if (nr < EXYNOS4X12_GPIO_PART1_MAX)
- return 0;
- else if (nr < EXYNOS4X12_GPIO_PART2_MAX)
- return EXYNOS4X12_GPIO_PART1_MAX;
- else
- return EXYNOS4X12_GPIO_PART2_MAX;
- } else {
- if (nr < EXYNOS4_GPIO_PART1_MAX)
- return 0;
- else
- return EXYNOS4_GPIO_PART1_MAX;
- }
- }
-
- return 0;
}
#endif
diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h
index ac60fe6..da8df74 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h
@@ -125,20 +125,45 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
/* GPIO pins per bank */
#define GPIO_PER_BANK 8
-static inline unsigned int s5p_gpio_base(int nr)
-{
- return S5PC110_GPIO_BASE;
-}
+#define S5P_GPIO_PART_SHIFT (24)
+#define S5P_GPIO_PART_MASK (0xff)
+#define S5P_GPIO_BANK_SHIFT (8)
+#define S5P_GPIO_BANK_MASK (0xffff)
+#define S5P_GPIO_PIN_MASK (0xff)
+
+#define S5P_GPIO_SET_PART(x) \
+ (((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT)
+
+#define S5P_GPIO_GET_PART(x) \
+ (((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK)
+
+#define S5P_GPIO_SET_PIN(x) \
+ ((x) & S5P_GPIO_PIN_MASK)
-static inline unsigned int s5p_gpio_part_max(int nr)
+#define S5PC100_SET_BANK(bank) \
+ (((unsigned)&(((struct s5pc100_gpio *) \
+ S5PC100_GPIO_BASE)->bank) - S5PC100_GPIO_BASE) \
+ & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define S5PC110_SET_BANK(bank) \
+ ((((unsigned)&(((struct s5pc110_gpio *) \
+ S5PC110_GPIO_BASE)->bank) - S5PC110_GPIO_BASE) \
+ & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+
+#define s5pc100_gpio_get(bank, pin) \
+ (S5P_GPIO_SET_PART(0) | \
+ S5PC100_SET_BANK(bank) | \
+ S5P_GPIO_SET_PIN(pin))
+
+#define s5pc110_gpio_get(bank, pin) \
+ (S5P_GPIO_SET_PART(0) | \
+ S5PC110_SET_BANK(bank) | \
+ S5P_GPIO_SET_PIN(pin))
+
+static inline unsigned int s5p_gpio_base(int nr)
{
- return 0;
+ return samsung_get_base_gpio();
}
-
-#define s5pc110_gpio_get_nr(bank, pin) \
- ((((((unsigned int)&(((struct s5pc110_gpio *)S5PC110_GPIO_BASE)->bank))\
- - S5PC110_GPIO_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin)
#endif
/* Pin configurations */
--
cgit v1.1
From 86b657878b1ad311167c88b555afded10f98f4d4 Mon Sep 17 00:00:00 2001
From: Stephen Warren
Date: Tue, 21 Jan 2014 17:19:19 -0700
Subject: ARM: tegra: accept any SKU ID for most chips
For Tegra20, the SKU ID actually impacts how U-Boot programs the chip,
and hence we need to explicitly know about each and every SKU ID in order
to operate correctly.
However, for Tegra30/114, this isn't the case. Rather than forcing each
new user with a different SKU to manually add their SKU ID into the code,
simply accept any SKU ID.
If U-Boot ever starts e.g. programming maximal CPU clocks etc., we'll
need to undo this, or make the default case map to conservative defaults,
but for now it's likely the path to least support cost.
Reported-by: Olof Johansson
Signed-off-by: Stephen Warren
Signed-off-by: Tom Warren
---
arch/arm/cpu/tegra-common/ap.c | 2 ++
1 file changed, 2 insertions(+)
(limited to 'arch/arm')
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index 60d71a6..f205be4 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -72,6 +72,7 @@ int tegra_get_chip_sku(void)
case SKU_ID_T33:
case SKU_ID_T30:
case SKU_ID_TM30MQS_P_A3:
+ default:
return TEGRA_SOC_T30;
}
break;
@@ -79,6 +80,7 @@ int tegra_get_chip_sku(void)
switch (sku_id) {
case SKU_ID_T114_ENG:
case SKU_ID_T114_1:
+ default:
return TEGRA_SOC_T114;
}
break;
--
cgit v1.1
From 0b01b53aa54d44a7f9a09bdfdc3d84fe1e1069fe Mon Sep 17 00:00:00 2001
From: Tom Warren
Date: Fri, 24 Jan 2014 10:16:17 -0700
Subject: ARM: tegra: deduplicate MASK_BITS_xxx clock mux enum
The enum used to define the set of register bits used to represent a
clock's input mux, MUX_BITS_*, is defined separately for each SoC at
present. Move this definition to a common location to ease fixing up
some issues with the definition, and the code that uses it.
Signed-off-by: Tom Warren
[swarren, extracted from a larger patch by Tom]
Signed-off-by: Stephen Warren
Reviewed-by: Thierry Reding
Tested-by: Thierry Reding
Acked-by: Thierry Reding
Signed-off-by: Tom Warren
---
arch/arm/cpu/tegra114-common/clock.c | 6 ------
arch/arm/cpu/tegra30-common/clock.c | 6 ------
arch/arm/include/asm/arch-tegra/clock.h | 6 ++++++
3 files changed, 6 insertions(+), 12 deletions(-)
(limited to 'arch/arm')
diff --git a/arch/arm/cpu/tegra114-common/clock.c b/arch/arm/cpu/tegra114-common/clock.c
index 5c4305a..47612e1 100644
--- a/arch/arm/cpu/tegra114-common/clock.c
+++ b/arch/arm/cpu/tegra114-common/clock.c
@@ -61,12 +61,6 @@ enum {
CLOCK_MAX_MUX = 8 /* number of source options for each clock */
};
-enum {
- MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */
- MASK_BITS_31_29,
- MASK_BITS_29_28,
-};
-
/*
* Clock source mux for each clock type. This just converts our enum into
* a list of mux sources for use by the code.
diff --git a/arch/arm/cpu/tegra30-common/clock.c b/arch/arm/cpu/tegra30-common/clock.c
index 74bd22b..89c3529 100644
--- a/arch/arm/cpu/tegra30-common/clock.c
+++ b/arch/arm/cpu/tegra30-common/clock.c
@@ -60,12 +60,6 @@ enum {
CLOCK_MAX_MUX = 8 /* number of source options for each clock */
};
-enum {
- MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */
- MASK_BITS_31_29,
- MASK_BITS_29_28,
-};
-
/*
* Clock source mux for each clock type. This just converts our enum into
* a list of mux sources for use by the code.
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
index e7d0fd4..052c020 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -20,6 +20,12 @@ enum clock_osc_freq {
CLOCK_OSC_FREQ_COUNT,
};
+enum {
+ MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */
+ MASK_BITS_31_29,
+ MASK_BITS_29_28,
+};
+
#include
/* PLL stabilization delay in usec */
#define CLOCK_PLL_STABLE_DELAY_US 300
--
cgit v1.1
From 5916a36ee99196efa97902471f7e2e725f4aa235 Mon Sep 17 00:00:00 2001
From: Stephen Warren
Date: Fri, 24 Jan 2014 10:16:18 -0700
Subject: ARM: tegra: rename MASK_BITS_29_28 to MASK_BITS_31_28
The only place where the MASK_BITS_* values are used is in
adjust_periph_pll(), which interprets the value 4 (old MASK_BITS_29_28,
new MASK_BITS_31_28) as being associated with mask OUT_CLK_SOURCE4_MASK,
i.e. bits 31:28. Rename the MASK_BITS_ macro to reflect how it's actually
implemented.
Note that no Tegra clock register actually uses all of bits 31:28 as
the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in
those cases, nothing is stored in the bits above the mux field, so it's
safe to pretend that the mux field extends all the way to the end of the
register. As such, the U-Boot clock driver is currently a bit lazy, and
doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps
them all together and pretends they're all 31:28. This patch doesn't
cause this issue; it was pre-existing. Hopefully, future patches will
clean this up.
Signed-off-by: Stephen Warren
Reviewed-by: Thierry Reding
Tested-by: Thierry Reding
Acked-by: Thierry Reding
Signed-off-by: Tom Warren
---
arch/arm/cpu/tegra114-common/clock.c | 2 +-
arch/arm/cpu/tegra30-common/clock.c | 2 +-
arch/arm/include/asm/arch-tegra/clock.h | 11 ++++++++++-
3 files changed, 12 insertions(+), 3 deletions(-)
(limited to 'arch/arm')
diff --git a/arch/arm/cpu/tegra114-common/clock.c b/arch/arm/cpu/tegra114-common/clock.c
index 47612e1..3bede71 100644
--- a/arch/arm/cpu/tegra114-common/clock.c
+++ b/arch/arm/cpu/tegra114-common/clock.c
@@ -103,7 +103,7 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
MASK_BITS_31_29},
{ CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_29_28}
+ MASK_BITS_31_28}
};
/*
diff --git a/arch/arm/cpu/tegra30-common/clock.c b/arch/arm/cpu/tegra30-common/clock.c
index 89c3529..3352870 100644
--- a/arch/arm/cpu/tegra30-common/clock.c
+++ b/arch/arm/cpu/tegra30-common/clock.c
@@ -102,7 +102,7 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
MASK_BITS_31_29},
{ CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_29_28}
+ MASK_BITS_31_28}
};
/*
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
index 052c020..80825e3 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -20,10 +20,19 @@ enum clock_osc_freq {
CLOCK_OSC_FREQ_COUNT,
};
+/*
+ * Note that no Tegra clock register actually uses all of bits 31:28 as
+ * the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in
+ * those cases, nothing is stored in the bits about the mux field, so it's
+ * safe to pretend that the mux field extends all the way to the end of the
+ * register. As such, the U-Boot clock driver is currently a bit lazy, and
+ * doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps
+ * them all together and pretends they're all 31:28.
+ */
enum {
MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */
MASK_BITS_31_29,
- MASK_BITS_29_28,
+ MASK_BITS_31_28,
};
#include
--
cgit v1.1
From 9cb0c6dc6928864c981f4cb9f20cc72ef7b8ff38 Mon Sep 17 00:00:00 2001
From: Stephen Warren
Date: Fri, 24 Jan 2014 10:16:19 -0700
Subject: ARM: tegra: rename OUT_CLK_SOURCE_*
OUT_CLK_SOURCE_ are currently named after the number of bits the mask
they represent includes. However, bit count is not the only possible
variable; bit position may also vary. Rename OUT_CLK_SOURCE_ to
OUT_CLK_SOURCE_31_30_ and OUT_CLK_SOURCE4_ to OUT_CLK_SOURCE_31_28 to
more completely describe exactly what they represent, without having to
go look up the definitions.
Signed-off-by: Stephen Warren
Reviewed-by: Thierry Reding
Tested-by: Thierry Reding
Acked-by: Thierry Reding
Signed-off-by: Tom Warren
---
arch/arm/cpu/tegra-common/clock.c | 16 ++++++++--------
arch/arm/include/asm/arch-tegra/clk_rst.h | 9 +++++----
2 files changed, 13 insertions(+), 12 deletions(-)
(limited to 'arch/arm')
diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c
index 268fb91..d9f2c76 100644
--- a/arch/arm/cpu/tegra-common/clock.c
+++ b/arch/arm/cpu/tegra-common/clock.c
@@ -142,8 +142,8 @@ void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
value = readl(reg);
- value &= ~OUT_CLK_SOURCE_MASK;
- value |= source << OUT_CLK_SOURCE_SHIFT;
+ value &= ~OUT_CLK_SOURCE_31_30_MASK;
+ value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
value &= ~OUT_CLK_DIVISOR_MASK;
value |= divisor << OUT_CLK_DIVISOR_SHIFT;
@@ -155,8 +155,8 @@ void clock_ll_set_source(enum periph_id periph_id, unsigned source)
{
u32 *reg = get_periph_source_reg(periph_id);
- clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
- source << OUT_CLK_SOURCE_SHIFT);
+ clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
+ source << OUT_CLK_SOURCE_31_30_SHIFT);
}
/**
@@ -305,11 +305,11 @@ static int adjust_periph_pll(enum periph_id periph_id, int source,
if (source < 0)
return -1;
if (mux_bits == 4) {
- clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK,
- source << OUT_CLK_SOURCE4_SHIFT);
+ clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
+ source << OUT_CLK_SOURCE_31_28_SHIFT);
} else {
- clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
- source << OUT_CLK_SOURCE_SHIFT);
+ clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
+ source << OUT_CLK_SOURCE_31_30_SHIFT);
}
udelay(2);
return 0;
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h
index 074b3bc..9f81237 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -233,11 +233,12 @@ enum {
#define OUT_CLK_DIVISOR_SHIFT 0
#define OUT_CLK_DIVISOR_MASK (0xffff << OUT_CLK_DIVISOR_SHIFT)
-#define OUT_CLK_SOURCE_SHIFT 30
-#define OUT_CLK_SOURCE_MASK (3U << OUT_CLK_SOURCE_SHIFT)
+#define OUT_CLK_SOURCE_31_30_SHIFT 30
+#define OUT_CLK_SOURCE_31_30_MASK (3U << OUT_CLK_SOURCE_31_30_SHIFT)
-#define OUT_CLK_SOURCE4_SHIFT 28
-#define OUT_CLK_SOURCE4_MASK (15U << OUT_CLK_SOURCE4_SHIFT)
+/* Note: See comment for MASK_BITS_31_28 in arch-tegra/clock.h */
+#define OUT_CLK_SOURCE_31_28_SHIFT 28
+#define OUT_CLK_SOURCE_31_28_MASK (15U << OUT_CLK_SOURCE_31_28_SHIFT)
/* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */
#define SCLK_SYS_STATE_SHIFT 28U
--
cgit v1.1
From 54d2e182925de2be7018535ca5123e2566617540 Mon Sep 17 00:00:00 2001
From: Stephen Warren
Date: Fri, 24 Jan 2014 10:16:20 -0700
Subject: ARM: tegra: use MASK_BITS_* macros everywhere
Not all code that set or interpreted "mux_bits" was using the named
macros, but rather some was simply using hard-coded integer constants.
This makes it hard to determine which pieces of code are affected by
changes to those constants.
Replace the integer constants with the equivalent macro definitions so
that everything is nicely tied together.
Note that I'm not convinced all the code was using the correct integer
constants, and hence I'm not convinced that all the code is now using
the desired macros. However, this change is a purely mechanical
replacement and should have no functional change. Fixing any bugs will
come later, separately.
Signed-off-by: Stephen Warren
Reviewed-by: Thierry Reding
Tested-by: Thierry Reding
Acked-by: Thierry Reding
Signed-off-by: Tom Warren
---
arch/arm/cpu/tegra-common/clock.c | 2 +-
arch/arm/cpu/tegra20-common/clock.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
(limited to 'arch/arm')
diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c
index d9f2c76..96b705f 100644
--- a/arch/arm/cpu/tegra-common/clock.c
+++ b/arch/arm/cpu/tegra-common/clock.c
@@ -304,7 +304,7 @@ static int adjust_periph_pll(enum periph_id periph_id, int source,
/* work out the source clock and set it */
if (source < 0)
return -1;
- if (mux_bits == 4) {
+ if (mux_bits == MASK_BITS_31_28) {
clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
source << OUT_CLK_SOURCE_31_28_SHIFT);
} else {
diff --git a/arch/arm/cpu/tegra20-common/clock.c b/arch/arm/cpu/tegra20-common/clock.c
index 34124f9..0c4f5fb 100644
--- a/arch/arm/cpu/tegra20-common/clock.c
+++ b/arch/arm/cpu/tegra20-common/clock.c
@@ -412,9 +412,9 @@ int get_periph_clock_source(enum periph_id periph_id,
* with its 16-bit divisor
*/
if (type == CLOCK_TYPE_PCXTS)
- *mux_bits = 4;
+ *mux_bits = MASK_BITS_31_28;
else
- *mux_bits = 2;
+ *mux_bits = MASK_BITS_31_30;
if (type == CLOCK_TYPE_PCMT16)
*divider_bits = 16;
else
--
cgit v1.1
From 04b8e8e7452a4cd00003e33a5a736bd077ff3471 Mon Sep 17 00:00:00 2001
From: Stephen Warren
Date: Fri, 24 Jan 2014 10:16:21 -0700
Subject: ARM: tegra: MASK_BITS_ no longer needs specific values
Since all code that sets or interprets MASK_BITS_* now uses the enums
to define/compare the values, there is no need for MASK_BITS_* to have
a specific integer value. In fact, having a specific integer value may
encourage people to hard-code those values, or interpret the values in
incorrect ways.
As such, remove the logic that assigns a specific value to the enum
values in order to make it completely clear that it's just an enum, not
something that directly represents some integer value.
Signed-off-by: Stephen Warren
Reviewed-by: Thierry Reding
Tested-by: Thierry Reding
Acked-by: Thierry Reding
Signed-off-by: Tom Warren
---
arch/arm/include/asm/arch-tegra/clock.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm')
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
index 80825e3..2f85696 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -30,7 +30,7 @@ enum clock_osc_freq {
* them all together and pretends they're all 31:28.
*/
enum {
- MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */
+ MASK_BITS_31_30,
MASK_BITS_31_29,
MASK_BITS_31_28,
};
--
cgit v1.1
From c82014daf5ed8030d2ec5903bd51b5ab817fb000 Mon Sep 17 00:00:00 2001
From: Tom Warren
Date: Fri, 24 Jan 2014 10:16:22 -0700
Subject: ARM: tegra: implement MASK_BITS_31_29
Some clock sources have 3-bit muxes in bits 31:29. Implement core
support for this mux field.
Signed-off-by: Tom Warren
[swarren, extracted from a larger patch by Tom]
Signed-off-by: Stephen Warren
Reviewed-by: Thierry Reding
Tested-by: Thierry Reding
Acked-by: Thierry Reding
Signed-off-by: Tom Warren
---
arch/arm/cpu/tegra-common/clock.c | 22 ++++++++++++++++++----
arch/arm/include/asm/arch-tegra/clk_rst.h | 3 +++
2 files changed, 21 insertions(+), 4 deletions(-)
(limited to 'arch/arm')
diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c
index 96b705f..33bb190 100644
--- a/arch/arm/cpu/tegra-common/clock.c
+++ b/arch/arm/cpu/tegra-common/clock.c
@@ -304,13 +304,27 @@ static int adjust_periph_pll(enum periph_id periph_id, int source,
/* work out the source clock and set it */
if (source < 0)
return -1;
- if (mux_bits == MASK_BITS_31_28) {
- clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
- source << OUT_CLK_SOURCE_31_28_SHIFT);
- } else {
+
+ switch (mux_bits) {
+ case MASK_BITS_31_30:
clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
source << OUT_CLK_SOURCE_31_30_SHIFT);
+ break;
+
+ case MASK_BITS_31_29:
+ clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
+ source << OUT_CLK_SOURCE_31_29_SHIFT);
+ break;
+
+ case MASK_BITS_31_28:
+ clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
+ source << OUT_CLK_SOURCE_31_28_SHIFT);
+ break;
+
+ default:
+ return -1;
}
+
udelay(2);
return 0;
}
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h
index 9f81237..f07b83d 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -236,6 +236,9 @@ enum {
#define OUT_CLK_SOURCE_31_30_SHIFT 30
#define OUT_CLK_SOURCE_31_30_MASK (3U << OUT_CLK_SOURCE_31_30_SHIFT)
+#define OUT_CLK_SOURCE_31_29_SHIFT 29
+#define OUT_CLK_SOURCE_31_29_MASK (7U << OUT_CLK_SOURCE_31_29_SHIFT)
+
/* Note: See comment for MASK_BITS_31_28 in arch-tegra/clock.h */
#define OUT_CLK_SOURCE_31_28_SHIFT 28
#define OUT_CLK_SOURCE_31_28_MASK (15U << OUT_CLK_SOURCE_31_28_SHIFT)
--
cgit v1.1
From 9399e540ca5b984582cddb1936ec44bf2756f8a1 Mon Sep 17 00:00:00 2001
From: Stephen Warren
Date: Fri, 24 Jan 2014 10:23:02 -0700
Subject: ARM: tegra: amend pmc.h for Tegra114+
Tegra114 and later's PMC module removes the pwrgate_timer_on register
and replaces it with a clamp_status register. Adjust pmc.h to reflect
this, and update any code affected by the change.
The cpu.c change in this patch was extracted from a much larger patch
by Jimmy Zhang. The pmc.h change was written from scratch, but inspired
by related changes made by Tom Warren.
There could well be other differences in the PMC register set for chips
after Tegra20/30. However, they don't affect the code in U-Boot at
present, so I haven't attempted an exhaustive update of pmc.h.
Signed-off-by: Stephen Warren
Reviewed-by: Thierry Reding
Acked-by: Thierry Reding
Tested-by: Thierry Reding
Signed-off-by: Tom Warren
---
arch/arm/cpu/arm720t/tegra114/cpu.c | 4 ++--
arch/arm/include/asm/arch-tegra/pmc.h | 6 +++++-
2 files changed, 7 insertions(+), 3 deletions(-)
(limited to 'arch/arm')
diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c
index 51ecff7..7a1747a 100644
--- a/arch/arm/cpu/arm720t/tegra114/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra114/cpu.c
@@ -219,8 +219,8 @@ static int is_clamp_enabled(u32 mask)
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
- /* Get clamp status. TODO: Add pmc_clamp_status alias to pmc.h */
- reg = readl(&pmc->pmc_pwrgate_timer_on);
+ /* Get clamp status. */
+ reg = readl(&pmc->pmc_clamp_status);
return (reg & mask) == mask;
}
diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h
index ba22236..6e5f61e 100644
--- a/arch/arm/include/asm/arch-tegra/pmc.h
+++ b/arch/arm/include/asm/arch-tegra/pmc.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2010,2011
+ * (C) Copyright 2010,2011,2014
* NVIDIA Corporation
*
* SPDX-License-Identifier: GPL-2.0+
@@ -21,7 +21,11 @@ struct pmc_ctlr {
uint pmc_dpd_sample; /* _DPD_PADS_SAMPLE_0, offset 20 */
uint pmc_dpd_enable; /* _DPD_PADS_ENABLE_0, offset 24 */
uint pmc_pwrgate_timer_off; /* _PWRGATE_TIMER_OFF_0, offset 28 */
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30)
uint pmc_pwrgate_timer_on; /* _PWRGATE_TIMER_ON_0, offset 2C */
+#else
+ uint pmc_clamp_status; /* _CLAMP_STATUS_0, offset 2C */
+#endif
uint pmc_pwrgate_toggle; /* _PWRGATE_TOGGLE_0, offset 30 */
uint pmc_remove_clamping; /* _REMOVE_CLAMPING_CMD_0, offset 34 */
uint pmc_pwrgate_status; /* _PWRGATE_STATUS_0, offset 38 */
--
cgit v1.1
From b9dd6215ce280a460ff182f51e80b7f4bf8b019a Mon Sep 17 00:00:00 2001
From: Jimmy Zhang
Date: Fri, 24 Jan 2014 10:37:36 -0700
Subject: ARM: tegra: don't exceed AVP limits when configuring PLLP
Based on the Tegra TRM, the system clock (which is the AVP clock) can
run up to 275MHz. On power on, the default sytem clock source is set to
PLLP_OUT0. In function clock_early_init(), PLLP_OUT0 will be set to
408MHz which is beyond system clock's upper limit.
The fix is to set the system clock to CLK_M before initializing PLLP,
and then switch back to PLLP_OUT4, which has an appropriate divider
configured, after PLLP has been configured
Implement this logic in new function tegra30_set_up_pllp(),
which sets up PLLP and all PLLP_OUT* dividers, and handles the AVP
clock switching. Remove the duplicate PLLP setup from pllx_set_rate()
and adjust_pllp_out_freqs().
Signed-off-by: Jimmy Zhang
[swarren, significantly refactored the change]
Signed-off-by: Stephen Warren
Reviewed-by: Thierry Reding
Tested-by: Thierry Reding
Acked-by: Thierry Reding
Signed-off-by: Tom Warren
---
arch/arm/cpu/arm720t/tegra-common/cpu.c | 26 +--------
arch/arm/cpu/arm720t/tegra114/cpu.c | 14 +----
arch/arm/cpu/arm720t/tegra30/cpu.c | 14 +----
arch/arm/cpu/tegra-common/clock.c | 94 ++++++++++++++++++++++++++++++-
arch/arm/cpu/tegra114-common/clock.c | 8 +--
arch/arm/cpu/tegra30-common/clock.c | 31 +---------
arch/arm/include/asm/arch-tegra/clk_rst.h | 16 +++++-
arch/arm/include/asm/arch-tegra/clock.h | 2 +
8 files changed, 118 insertions(+), 87 deletions(-)
(limited to 'arch/arm')
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c
index 72c69b9..03f67b1 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -114,24 +114,6 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
},
};
-void adjust_pllp_out_freqs(void)
-{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH];
- u32 reg;
-
- /* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
- reg = readl(&pll->pll_out[0]); /* OUTA, contains OUT2 / OUT1 */
- reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR
- | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR;
- writel(reg, &pll->pll_out[0]);
-
- reg = readl(&pll->pll_out[1]); /* OUTB, contains OUT4 / OUT3 */
- reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR
- | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR;
- writel(reg, &pll->pll_out[1]);
-}
-
int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
u32 divp, u32 cpcon)
{
@@ -207,12 +189,6 @@ void init_pllx(void)
/* set pllx */
sel = &tegra_pll_x_table[chip_sku][osc];
pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
-
- /* adjust PLLP_out1-4 on T3x/T114 */
- if (soc_type >= CHIPID_TEGRA30) {
- debug(" init_pllx: adjusting PLLP out freqs\n");
- adjust_pllp_out_freqs();
- }
}
void enable_cpu_clock(int enable)
diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c
index 7a1747a..385e1a1 100644
--- a/arch/arm/cpu/arm720t/tegra114/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra114/cpu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -126,18 +126,6 @@ void t114_init_clocks(void)
/* Set active CPU cluster to G */
clrbits_le32(&flow->cluster_control, 1);
- /*
- * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
- * at 108 MHz. This is glitch free as only the source is changed, no
- * special precaution needed.
- */
- val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
- (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
- (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
- (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
- (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
- writel(val, &clkrst->crc_sclk_brst_pol);
-
writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
debug("Setting up PLLX\n");
diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c
index e162357..a806483 100644
--- a/arch/arm/cpu/arm720t/tegra30/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra30/cpu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -84,18 +84,6 @@ void t30_init_clocks(void)
/* Set active CPU cluster to G */
clrbits_le32(flow->cluster_control, 1 << 0);
- /*
- * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
- * at 108 MHz. This is glitch free as only the source is changed, no
- * special precaution needed.
- */
- val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
- (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
- (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
- (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
- (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
- writel(val, &clkrst->crc_sclk_brst_pol);
-
writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |
diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c
index 33bb190..11c7435 100644
--- a/arch/arm/cpu/tegra-common/clock.c
+++ b/arch/arm/cpu/tegra-common/clock.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -575,3 +575,95 @@ void clock_init(void)
/* Do any special system timer/TSC setup */
arch_timer_init();
}
+
+static void set_avp_clock_source(u32 src)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 val;
+
+ val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
+ (src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
+ (src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
+ (src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
+ (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
+ writel(val, &clkrst->crc_sclk_brst_pol);
+ udelay(3);
+}
+
+/*
+ * This function is useful on Tegra30, and any later SoCs that have compatible
+ * PLLP configuration registers.
+ */
+void tegra30_set_up_pllp(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ /*
+ * Based on the Tegra TRM, the system clock (which is the AVP clock) can
+ * run up to 275MHz. On power on, the default sytem clock source is set
+ * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to
+ * 408MHz which is beyond system clock's upper limit.
+ *
+ * The fix is to set the system clock to CLK_M before initializing PLLP,
+ * and then switch back to PLLP_OUT4, which has an appropriate divider
+ * configured, after PLLP has been configured
+ */
+ set_avp_clock_source(SCLK_SOURCE_CLKM);
+
+ /*
+ * PLLP output frequency set to 408Mhz
+ * PLLC output frequency set to 228Mhz
+ */
+ switch (clock_get_osc_freq()) {
+ case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+ clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
+ clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
+ break;
+
+ case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
+ clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
+ clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
+ break;
+
+ case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+ clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
+ clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
+ break;
+ case CLOCK_OSC_FREQ_19_2:
+ default:
+ /*
+ * These are not supported. It is too early to print a
+ * message and the UART likely won't work anyway due to the
+ * oscillator being wrong.
+ */
+ break;
+ }
+
+ /* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
+
+ /* OUT1, 2 */
+ /* Assert RSTN before enable */
+ reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN;
+ writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
+ /* Set divisor and reenable */
+ reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO)
+ | PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS
+ | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
+ | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
+ writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
+
+ /* OUT3, 4 */
+ /* Assert RSTN before enable */
+ reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
+ writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
+ /* Set divisor and reenable */
+ reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
+ | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
+ | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
+ | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
+ writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
+
+ set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
+}
diff --git a/arch/arm/cpu/tegra114-common/clock.c b/arch/arm/cpu/tegra114-common/clock.c
index 3bede71..d5194e1 100644
--- a/arch/arm/cpu/tegra114-common/clock.c
+++ b/arch/arm/cpu/tegra114-common/clock.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -604,26 +604,24 @@ void clock_early_init(void)
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ tegra30_set_up_pllp();
+
/*
- * PLLP output frequency set to 408Mhz
* PLLC output frequency set to 600Mhz
* PLLD output frequency set to 925Mhz
*/
switch (clock_get_osc_freq()) {
case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
- clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
break;
case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
- clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
break;
case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
- clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
break;
diff --git a/arch/arm/cpu/tegra30-common/clock.c b/arch/arm/cpu/tegra30-common/clock.c
index 3352870..80ba2d8 100644
--- a/arch/arm/cpu/tegra30-common/clock.c
+++ b/arch/arm/cpu/tegra30-common/clock.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -581,34 +581,7 @@ enum periph_id clk_id_to_periph_id(int clk_id)
void clock_early_init(void)
{
- /*
- * PLLP output frequency set to 408Mhz
- * PLLC output frequency set to 228Mhz
- */
- switch (clock_get_osc_freq()) {
- case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
- clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
- clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
- break;
-
- case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
- clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
- clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
- break;
-
- case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
- clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
- clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
- break;
- case CLOCK_OSC_FREQ_19_2:
- default:
- /*
- * These are not supported. It is too early to print a
- * message and the UART likely won't work anyway due to the
- * oscillator being wrong.
- */
- break;
- }
+ tegra30_set_up_pllp();
}
void arch_timer_init(void)
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h
index f07b83d..021cfcc 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2010,2011
+ * (C) Copyright 2010-2014
* NVIDIA Corporation
*
* SPDX-License-Identifier: GPL-2.0+
@@ -209,6 +209,20 @@ enum {
IN_408_OUT_9_6_DIVISOR = 83,
};
+#define PLLP_OUT1_RSTN_DIS (1 << 0)
+#define PLLP_OUT1_RSTN_EN (0 << 0)
+#define PLLP_OUT1_CLKEN (1 << 1)
+#define PLLP_OUT2_RSTN_DIS (1 << 16)
+#define PLLP_OUT2_RSTN_EN (0 << 16)
+#define PLLP_OUT2_CLKEN (1 << 17)
+
+#define PLLP_OUT3_RSTN_DIS (1 << 0)
+#define PLLP_OUT3_RSTN_EN (0 << 0)
+#define PLLP_OUT3_CLKEN (1 << 1)
+#define PLLP_OUT4_RSTN_DIS (1 << 16)
+#define PLLP_OUT4_RSTN_EN (0 << 16)
+#define PLLP_OUT4_CLKEN (1 << 17)
+
/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */
#define PLLU_POWERDOWN (1 << 16)
#define PLL_ENABLE_POWERDOWN (1 << 14)
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
index 2f85696..9d8114c 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -320,4 +320,6 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon);
/* SoC-specific TSC init */
void arch_timer_init(void);
+void tegra30_set_up_pllp(void);
+
#endif /* _TEGRA_CLOCK_H_ */
--
cgit v1.1
From 41cd530d6d9b4fb3c2ab475cb92f1242400b5fb1 Mon Sep 17 00:00:00 2001
From: Stephen Warren
Date: Fri, 24 Jan 2014 12:46:07 -0700
Subject: ARM: tegra: misc cleanups triggered by Tegra124 review
Use a named constant for the PLL lock bit in enable_cpu_clocks().
Construct the complete value of pmc_pwrgate_toggle, rather than doing a
read-modify-write; the register is simple enough and doesn't need to
maintain state between operations.
Signed-off-by: Stephen Warren
Tested-by: Thierry Reding
Signed-off-by: Tom Warren
---
arch/arm/cpu/arm720t/tegra114/cpu.c | 6 ++----
arch/arm/include/asm/arch-tegra/clk_rst.h | 3 +++
2 files changed, 5 insertions(+), 4 deletions(-)
(limited to 'arch/arm')
diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c
index 385e1a1..a5de100 100644
--- a/arch/arm/cpu/arm720t/tegra114/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra114/cpu.c
@@ -68,7 +68,7 @@ static void enable_cpu_clocks(void)
/* Wait for PLL-X to lock */
do {
reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
- } while ((reg & (1 << 27)) == 0);
+ } while ((reg & PLL_LOCK_MASK) == 0);
/* Wait until all clocks are stable */
udelay(PLL_STABILIZATION_DELAY);
@@ -221,9 +221,7 @@ static void power_partition(u32 status, u32 partid)
if (!is_partition_powered(status)) {
/* No, toggle the partition power state (OFF -> ON) */
debug("power_partition, toggling state\n");
- clrbits_le32(&pmc->pmc_pwrgate_toggle, 0x1F);
- setbits_le32(&pmc->pmc_pwrgate_toggle, partid);
- setbits_le32(&pmc->pmc_pwrgate_toggle, START_CP);
+ writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
/* Wait for the power to come up */
while (!is_partition_powered(status))
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h
index 021cfcc..cc60825 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -160,6 +160,9 @@ struct clk_rst_ctlr {
#define PLL_BASE_OVRRIDE_MASK (1U << 28)
+#define PLL_LOCK_SHIFT 27
+#define PLL_LOCK_MASK (1U << PLL_LOCK_SHIFT)
+
#define PLL_DIVP_SHIFT 20
#define PLL_DIVP_MASK (7U << PLL_DIVP_SHIFT)
--
cgit v1.1
From cad38a57d3c4505d560f46bdc2640846656d0efb Mon Sep 17 00:00:00 2001
From: Stephen Warren
Date: Fri, 24 Jan 2014 12:46:08 -0700
Subject: ARM: tegra: pass just partition ID to power_partition()
Pass just the partition ID to power_partition(), rather than also passing
the partition's status register mask too. This makes it simpler to get
call-sites correct, since they don't need to pass two different values
that define the same thing and must match.
Consequently, we can remove the mask definitions from pmc.h.
Suggested-by: Thierry Reding
Signed-off-by: Stephen Warren
Signed-off-by: Tom Warren
---
arch/arm/cpu/arm720t/tegra114/cpu.c | 24 ++++++++++++------------
arch/arm/include/asm/arch-tegra/pmc.h | 9 +++------
2 files changed, 15 insertions(+), 18 deletions(-)
(limited to 'arch/arm')
diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c
index a5de100..d10b96a 100644
--- a/arch/arm/cpu/arm720t/tegra114/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra114/cpu.c
@@ -192,43 +192,43 @@ void t114_init_clocks(void)
debug("t114_init_clocks exit\n");
}
-static int is_partition_powered(u32 mask)
+static bool is_partition_powered(u32 partid)
{
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
/* Get power gate status */
reg = readl(&pmc->pmc_pwrgate_status);
- return (reg & mask) == mask;
+ return !!(reg & (1 << partid));
}
-static int is_clamp_enabled(u32 mask)
+static bool is_clamp_enabled(u32 partid)
{
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
u32 reg;
/* Get clamp status. */
reg = readl(&pmc->pmc_clamp_status);
- return (reg & mask) == mask;
+ return !!(reg & (1 << partid));
}
-static void power_partition(u32 status, u32 partid)
+static void power_partition(u32 partid)
{
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- debug("%s: status = %08X, part ID = %08X\n", __func__, status, partid);
+ debug("%s: part ID = %08X\n", __func__, partid);
/* Is the partition already on? */
- if (!is_partition_powered(status)) {
+ if (!is_partition_powered(partid)) {
/* No, toggle the partition power state (OFF -> ON) */
debug("power_partition, toggling state\n");
writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
/* Wait for the power to come up */
- while (!is_partition_powered(status))
+ while (!is_partition_powered(partid))
;
/* Wait for the clamp status to be cleared */
- while (is_clamp_enabled(status))
+ while (is_clamp_enabled(partid))
;
/* Give I/O signals time to stabilize */
@@ -243,13 +243,13 @@ void powerup_cpus(void)
/* We boot to the fast cluster */
debug("powerup_cpus entry: G cluster\n");
/* Power up the fast cluster rail partition */
- power_partition(CRAIL, CRAILID);
+ power_partition(CRAIL);
/* Power up the fast cluster non-CPU partition */
- power_partition(C0NC, C0NCID);
+ power_partition(C0NC);
/* Power up the fast cluster CPU0 partition */
- power_partition(CE0, CE0ID);
+ power_partition(CE0);
}
void start_cpu(u32 reset_vector)
diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h
index 6e5f61e..9f05a14 100644
--- a/arch/arm/include/asm/arch-tegra/pmc.h
+++ b/arch/arm/include/asm/arch-tegra/pmc.h
@@ -118,11 +118,8 @@ struct pmc_ctlr {
#define CPUPWRREQ_OE (1 << 16)
#define CPUPWRREQ_POL (1 << 15)
-#define CRAILID (0)
-#define CE0ID (14)
-#define C0NCID (15)
-#define CRAIL (1 << CRAILID)
-#define CE0 (1 << CE0ID)
-#define C0NC (1 << C0NCID)
+#define CRAIL 0
+#define CE0 14
+#define C0NC 15
#endif /* PMC_H */
--
cgit v1.1
From 41447fb2cf2fbeb448b1d606cb13ca1ae84f9737 Mon Sep 17 00:00:00 2001
From: Stephen Warren
Date: Fri, 24 Jan 2014 12:46:09 -0700
Subject: ARM: tegra: enable PLLX only once it's been fully configured
This programming sequence is correct per Jimmy Zhang, and makes sense
too!
Signed-off-by: Stephen Warren
Tested-by: Thierry Reding
Signed-off-by: Tom Warren
---
arch/arm/cpu/arm720t/tegra-common/cpu.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
(limited to 'arch/arm')
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c
index 03f67b1..322ce10 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
@@ -144,18 +144,23 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
reg |= (1 << PLL_DCCON_SHIFT);
writel(reg, &pll->pll_misc);
- /* Enable PLLX */
- reg = readl(&pll->pll_base);
- reg |= PLL_ENABLE_MASK;
-
/* Disable BYPASS */
+ reg = readl(&pll->pll_base);
reg &= ~PLL_BYPASS_MASK;
writel(reg, &pll->pll_base);
+ debug("pllx_set_rate: base = 0x%08X\n", reg);
/* Set lock_enable to PLLX_MISC */
reg = readl(&pll->pll_misc);
reg |= PLL_LOCK_ENABLE_MASK;
writel(reg, &pll->pll_misc);
+ debug("pllx_set_rate: misc = 0x%08X\n", reg);
+
+ /* Enable PLLX last, once it's all configured */
+ reg = readl(&pll->pll_base);
+ reg |= PLL_ENABLE_MASK;
+ writel(reg, &pll->pll_base);
+ debug("pllx_set_rate: base final = 0x%08X\n", reg);
return 0;
}
--
cgit v1.1
From a4bcd67c72aabfcc2153f4393cd9108b860d9040 Mon Sep 17 00:00:00 2001
From: Stephen Warren
Date: Fri, 24 Jan 2014 12:46:10 -0700
Subject: ARM: tegra: remove a conditional for CSITE rate
There's already an SoC-specific conditional in cpu.h to determine the
PLLP rate. Define the CSITE clock rate inside the same conditional, so
that we can remove a conditional from clock_enable_coresight(). This
means one less place to update the code for new SoCs.
Signed-off-by: Stephen Warren
Tested-by: Thierry Reding
Signed-off-by: Tom Warren
---
arch/arm/cpu/arm720t/tegra-common/cpu.c | 12 +-----------
arch/arm/cpu/arm720t/tegra-common/cpu.h | 8 +++++---
2 files changed, 6 insertions(+), 14 deletions(-)
(limited to 'arch/arm')
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c
index 322ce10..d62bb9e 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
@@ -315,7 +315,6 @@ void reset_A9_cpu(int reset)
void clock_enable_coresight(int enable)
{
u32 rst, src = 2;
- int soc_type;
debug("clock_enable_coresight entry\n");
clock_set_enable(PERIPH_ID_CORESIGHT, enable);
@@ -328,16 +327,7 @@ void clock_enable_coresight(int enable)
* Clock divider request would setup CSITE clock as 144MHz
* for PLLP base 216MHz and 204MHz for PLLP base 408MHz
*/
-
- soc_type = tegra_get_chip();
- if (soc_type == CHIPID_TEGRA30 || soc_type == CHIPID_TEGRA114)
- src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000);
- else if (soc_type == CHIPID_TEGRA20)
- src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
- else
- printf("%s: Unknown SoC type %X!\n",
- __func__, soc_type);
-
+ src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ);
clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
/* Unlock the CPU CoreSight interfaces */
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.h b/arch/arm/cpu/arm720t/tegra-common/cpu.h
index 60412c7..d1520ce 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.h
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2010-2011
+ * (C) Copyright 2010-2014
* NVIDIA Corporation
*
* SPDX-License-Identifier: GPL-2.0+
@@ -11,9 +11,11 @@
#define IO_STABILIZATION_DELAY (1000)
#if defined(CONFIG_TEGRA20)
-#define NVBL_PLLP_KHZ (216000)
+#define NVBL_PLLP_KHZ 216000
+#define CSITE_KHZ 144000
#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
-#define NVBL_PLLP_KHZ (408000)
+#define NVBL_PLLP_KHZ 408000
+#define CSITE_KHZ 204000
#else
#error "Unknown Tegra chip!"
#endif
--
cgit v1.1
From 49941b22ec99f9ef8ee6673f61e06e8fde239e97 Mon Sep 17 00:00:00 2001
From: Stephen Warren
Date: Fri, 24 Jan 2014 12:46:12 -0700
Subject: ARM: tegra: fix a typo in the tegra114.dtsi
The reg property for node spi@7000d800 was wrong. Fix it to match the
HW. This change was verified against the Linux kernel.
Signed-off-by: Stephen Warren
Tested-by: Thierry Reding
Signed-off-by: Tom Warren
---
arch/arm/dts/tegra114.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm')
diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
index 626cc3c..f52fcf1 100644
--- a/arch/arm/dts/tegra114.dtsi
+++ b/arch/arm/dts/tegra114.dtsi
@@ -139,7 +139,7 @@
spi@7000d800 {
compatible = "nvidia,tegra114-spi";
- reg = <0x7000d480 0x200>;
+ reg = <0x7000d800 0x200>;
interrupts = <0 83 0x04>;
nvidia,dma-request-selector = <&apbdma 17>;
#address-cells = <1>;
--
cgit v1.1
From 999c6baf79d74f6ec5c6c96334ad8d653b4081a7 Mon Sep 17 00:00:00 2001
From: Tom Warren
Date: Fri, 24 Jan 2014 12:46:13 -0700
Subject: ARM: tegra: add/edit headers for Tegra124
These headers define the Tegra124 hardware. Add them to the usual
place.
Add Tegra124 chip ID/SKU ID definitions to common headers.
There's no real HW change on Tegra124 for 90% of the toys, so it might
make sense for a future patch to unify some of the content of these
files in a common location.
Signed-off-by: Tom Warren
Signed-off-by: Stephen Warren
Tested-by: Thierry Reding
Signed-off-by: Tom Warren
---
arch/arm/include/asm/arch-tegra/clk_rst.h | 156 +++++-
arch/arm/include/asm/arch-tegra/gp_padctrl.h | 1 +
arch/arm/include/asm/arch-tegra/pmc.h | 255 +++++++++
arch/arm/include/asm/arch-tegra/tegra.h | 2 +
arch/arm/include/asm/arch-tegra124/ahb.h | 91 ++++
arch/arm/include/asm/arch-tegra124/clock-tables.h | 496 +++++++++++++++++
arch/arm/include/asm/arch-tegra124/clock.h | 19 +
arch/arm/include/asm/arch-tegra124/flow.h | 40 ++
arch/arm/include/asm/arch-tegra124/funcmux.h | 23 +
arch/arm/include/asm/arch-tegra124/gp_padctrl.h | 74 +++
arch/arm/include/asm/arch-tegra124/gpio.h | 303 +++++++++++
arch/arm/include/asm/arch-tegra124/hardware.h | 16 +
arch/arm/include/asm/arch-tegra124/pinmux.h | 620 ++++++++++++++++++++++
arch/arm/include/asm/arch-tegra124/pmu.h | 14 +
arch/arm/include/asm/arch-tegra124/spl.h | 13 +
arch/arm/include/asm/arch-tegra124/sysctr.h | 26 +
arch/arm/include/asm/arch-tegra124/tegra.h | 30 ++
arch/arm/include/asm/arch-tegra124/usb.h | 268 ++++++++++
18 files changed, 2419 insertions(+), 28 deletions(-)
create mode 100644 arch/arm/include/asm/arch-tegra124/ahb.h
create mode 100644 arch/arm/include/asm/arch-tegra124/clock-tables.h
create mode 100644 arch/arm/include/asm/arch-tegra124/clock.h
create mode 100644 arch/arm/include/asm/arch-tegra124/flow.h
create mode 100644 arch/arm/include/asm/arch-tegra124/funcmux.h
create mode 100644 arch/arm/include/asm/arch-tegra124/gp_padctrl.h
create mode 100644 arch/arm/include/asm/arch-tegra124/gpio.h
create mode 100644 arch/arm/include/asm/arch-tegra124/hardware.h
create mode 100644 arch/arm/include/asm/arch-tegra124/pinmux.h
create mode 100644 arch/arm/include/asm/arch-tegra124/pmu.h
create mode 100644 arch/arm/include/asm/arch-tegra124/spl.h
create mode 100644 arch/arm/include/asm/arch-tegra124/sysctr.h
create mode 100644 arch/arm/include/asm/arch-tegra124/tegra.h
create mode 100644 arch/arm/include/asm/arch-tegra124/usb.h
(limited to 'arch/arm')
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h
index cc60825..7d28e16 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -11,7 +11,8 @@
/* PLL registers - there are several PLLs in the clock controller */
struct clk_pll {
uint pll_base; /* the control register */
- uint pll_out[2]; /* output control */
+ /* pll_out[0] is output A control, pll_out[1] is output B control */
+ uint pll_out[2];
uint pll_misc; /* other misc things */
};
@@ -21,6 +22,13 @@ struct clk_pll_simple {
uint pll_misc; /* other misc things */
};
+struct clk_pllm {
+ uint pllm_base; /* the control register */
+ uint pllm_out; /* output control */
+ uint pllm_misc1; /* misc1 */
+ uint pllm_misc2; /* misc2 */
+};
+
/* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */
struct clk_set_clr {
uint set;
@@ -38,7 +46,8 @@ enum {
TEGRA_CLK_REGS = 3, /* Number of clock enable regs L/H/U */
TEGRA_CLK_SOURCES = 64, /* Number of ppl clock sources L/H/U */
TEGRA_CLK_REGS_VW = 2, /* Number of clock enable regs V/W */
- TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W*/
+ TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W */
+ TEGRA_CLK_SOURCES_X = 32, /* Number of ppl clock sources X */
};
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
@@ -47,7 +56,7 @@ struct clk_rst_ctlr {
uint crc_rst_dev[TEGRA_CLK_REGS]; /* _RST_DEVICES_L/H/U_0 */
uint crc_clk_out_enb[TEGRA_CLK_REGS]; /* _CLK_OUT_ENB_L/H/U_0 */
uint crc_reserved0; /* reserved_0, 0x1C */
- uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0,0x20 */
+ uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */
uint crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */
uint crc_sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */
uint crc_super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */
@@ -75,7 +84,21 @@ struct clk_rst_ctlr {
uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */
- uint crc_reserved20[64]; /* _reserved_20, 0x200-2fc */
+ uint crc_reserved20[32]; /* _reserved_20, 0x200-27c */
+
+ uint crc_clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */
+ uint crc_clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */
+ uint crc_clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */
+
+ uint crc_rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */
+ uint crc_rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */
+ uint crc_rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */
+
+ uint crc_reserved21[23]; /* _reserved_21, 0x298-2f0 */
+
+ uint crc_dfll_base; /* _DFLL_BASE_0, 0x2f4 */
+
+ uint crc_reserved22[2]; /* _reserved_22, 0x2f8-2fc */
/* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */
struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS];
@@ -105,10 +128,10 @@ struct clk_rst_ctlr {
uint crc_clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */
uint crc_clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37C */
uint crc_cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */
- uint crc_cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTR1L_0, 0x384 */
+ uint crc_cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1_0, 0x384 */
uint crc_cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */
uint crc_reserved33[9]; /* _reserved_33, 0x38c-3ac */
- uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* _G3D2_0..., 0x3b0-0x42c */
+ uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* 0x3B0-0x42C */
/* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */
struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
/* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
@@ -142,6 +165,47 @@ struct clk_rst_ctlr {
uint crc_audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */
uint crc_audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */
uint crc_audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */
+
+ uint crc_plld2_base; /* _PLLD2_BASE_0, 0x4B8 */
+ uint crc_plld2_misc; /* _PLLD2_MISC_0, 0x4BC */
+ uint crc_utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4C0 */
+ uint crc_pllrefe_base; /* _PLLREFE_BASE_0, 0x4C4 */
+ uint crc_pllrefe_misc; /* _PLLREFE_MISC_0, 0x4C8 */
+ uint crs_reserved_50[7]; /* _reserved_50, 0x4CC-0x4E4 */
+ uint crc_pllc2_base; /* _PLLC2_BASE_0, 0x4E8 */
+ uint crc_pllc2_misc0; /* _PLLC2_MISC_0_0, 0x4EC */
+ uint crc_pllc2_misc1; /* _PLLC2_MISC_1_0, 0x4F0 */
+ uint crc_pllc2_misc2; /* _PLLC2_MISC_2_0, 0x4F4 */
+ uint crc_pllc2_misc3; /* _PLLC2_MISC_3_0, 0x4F8 */
+ uint crc_pllc3_base; /* _PLLC3_BASE_0, 0x4FC */
+ uint crc_pllc3_misc0; /* _PLLC3_MISC_0_0, 0x500 */
+ uint crc_pllc3_misc1; /* _PLLC3_MISC_1_0, 0x504 */
+ uint crc_pllc3_misc2; /* _PLLC3_MISC_2_0, 0x508 */
+ uint crc_pllc3_misc3; /* _PLLC3_MISC_3_0, 0x50C */
+ uint crc_pllx_misc1; /* _PLLX_MISC_1_0, 0x510 */
+ uint crc_pllx_misc2; /* _PLLX_MISC_2_0, 0x514 */
+ uint crc_pllx_misc3; /* _PLLX_MISC_3_0, 0x518 */
+ uint crc_xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0_0, 0x51C */
+ uint crc_xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG0_1, 0x520 */
+ uint crc_plle_aux1; /* _PLLE_AUX1_0, 0x524 */
+ uint crc_pllp_reshift; /* _PLLP_RESHIFT_0, 0x528 */
+ uint crc_utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52C */
+ uint crc_pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */
+ uint crc_xusb_pll_cfg0; /* _XUSB_PLL_CFG0_0, 0x534 */
+ uint crc_reserved51[1]; /* _reserved_51, 0x538 */
+ uint crc_clk_cpu_misc; /* _CLK_CPU_MISC_0, 0x53C */
+ uint crc_clk_cpug_misc; /* _CLK_CPUG_MISC_0, 0x540 */
+ uint crc_clk_cpulp_misc; /* _CLK_CPULP_MISC_0, 0x544 */
+ uint crc_pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG_0, 0x548 */
+ uint crc_pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG_0, 0x54C */
+ uint crc_pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS_0, 0x550 */
+ uint crc_reserved52[1]; /* _reserved_52, 0x554 */
+ uint crc_super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */
+ uint crc_spare_reg0; /* _SPARE_REG0_0, 0x55C */
+
+ /* Tegra124 - skip to 0x600 here for new CLK_SOURCE_ regs */
+ uint crc_reserved60[40]; /* _reserved_60, 0x560 - 0x5FC */
+ uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */
};
/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
@@ -236,9 +300,15 @@ enum {
#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
-/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
-#define OSC_XOBP_SHIFT 1
-#define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT)
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 0x50 */
+#define OSC_XOE_SHIFT 0
+#define OSC_XOE_MASK (1 << OSC_XOE_SHIFT)
+#define OSC_XOE_ENABLE (1 << OSC_XOE_SHIFT)
+#define OSC_XOBP_SHIFT 1
+#define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT)
+#define OSC_XOFS_SHIFT 4
+#define OSC_XOFS_MASK (0x3F << OSC_XOFS_SHIFT)
+#define OSC_DRIVE_STRENGTH 7
/*
* CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits
@@ -311,7 +381,7 @@ enum {
#define SUPER_SCLK_DIVISOR_SHIFT 0
#define SUPER_SCLK_DIVISOR_MASK (0xff << SUPER_SCLK_DIVISOR_SHIFT)
-/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE */
+/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */
#define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7
#define CLK_SYS_RATE_HCLK_DISABLE_MASK (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT)
#define CLK_SYS_RATE_AHB_RATE_SHIFT 4
@@ -321,23 +391,53 @@ enum {
#define CLK_SYS_RATE_APB_RATE_SHIFT 0
#define CLK_SYS_RATE_APB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
-/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR */
-#define CLR_CPURESET0 (1 << 0)
-#define CLR_CPURESET1 (1 << 1)
-#define CLR_CPURESET2 (1 << 2)
-#define CLR_CPURESET3 (1 << 3)
-#define CLR_DBGRESET0 (1 << 12)
-#define CLR_DBGRESET1 (1 << 13)
-#define CLR_DBGRESET2 (1 << 14)
-#define CLR_DBGRESET3 (1 << 15)
-#define CLR_CORERESET0 (1 << 16)
-#define CLR_CORERESET1 (1 << 17)
-#define CLR_CORERESET2 (1 << 18)
-#define CLR_CORERESET3 (1 << 19)
-#define CLR_CXRESET0 (1 << 20)
-#define CLR_CXRESET1 (1 << 21)
-#define CLR_CXRESET2 (1 << 22)
-#define CLR_CXRESET3 (1 << 23)
-#define CLR_NONCPURESET (1 << 29)
+/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR 0x344 */
+#define CLR_CPURESET0 (1 << 0)
+#define CLR_CPURESET1 (1 << 1)
+#define CLR_CPURESET2 (1 << 2)
+#define CLR_CPURESET3 (1 << 3)
+#define CLR_DBGRESET0 (1 << 12)
+#define CLR_DBGRESET1 (1 << 13)
+#define CLR_DBGRESET2 (1 << 14)
+#define CLR_DBGRESET3 (1 << 15)
+#define CLR_CORERESET0 (1 << 16)
+#define CLR_CORERESET1 (1 << 17)
+#define CLR_CORERESET2 (1 << 18)
+#define CLR_CORERESET3 (1 << 19)
+#define CLR_CXRESET0 (1 << 20)
+#define CLR_CXRESET1 (1 << 21)
+#define CLR_CXRESET2 (1 << 22)
+#define CLR_CXRESET3 (1 << 23)
+#define CLR_L2RESET (1 << 24)
+#define CLR_NONCPURESET (1 << 29)
+#define CLR_PRESETDBG (1 << 30)
+
+/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c */
+#define CLR_CPU0_CLK_STP (1 << 8)
+#define CLR_CPU1_CLK_STP (1 << 9)
+#define CLR_CPU2_CLK_STP (1 << 10)
+#define CLR_CPU3_CLK_STP (1 << 11)
+
+/* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */
+#define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29)
+
+/* CRC_CLK_ENB_V_SET_0 0x440 */
+#define SET_CLK_ENB_CPUG_ENABLE (1 << 0)
+#define SET_CLK_ENB_CPULP_ENABLE (1 << 1)
+#define SET_CLK_ENB_MSELECT_ENABLE (1 << 3)
+
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 0x484 */
+#define PLL_ACTIVE_POWERDOWN (1 << 12)
+#define PLL_ENABLE_POWERDOWN (1 << 14)
+#define PLLU_POWERDOWN (1 << 16)
+
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 0x488 */
+#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
+#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
+#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
+
+/* CLK_RST_CONTROLLER_PLLX_MISC_3 */
+#define PLLX_IDDQ_SHIFT 3
+#define PLLX_IDDQ_MASK (1U << PLLX_IDDQ_SHIFT)
#endif /* _TEGRA_CLK_RST_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/gp_padctrl.h b/arch/arm/include/asm/arch-tegra/gp_padctrl.h
index c840c08..7a86acb 100644
--- a/arch/arm/include/asm/arch-tegra/gp_padctrl.h
+++ b/arch/arm/include/asm/arch-tegra/gp_padctrl.h
@@ -20,5 +20,6 @@
#define CHIPID_TEGRA20 0x20
#define CHIPID_TEGRA30 0x30
#define CHIPID_TEGRA114 0x35
+#define CHIPID_TEGRA124 0x40
#endif /* _TEGRA_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h
index 9f05a14..4c3264b 100644
--- a/arch/arm/include/asm/arch-tegra/pmc.h
+++ b/arch/arm/include/asm/arch-tegra/pmc.h
@@ -107,6 +107,179 @@ struct pmc_ctlr {
uint pmc_sys_33v_en; /* _SYS_33V_EN_0, offset 154 */
uint pmc_bo_mirror_access; /* _BOUNDOUT_MIRROR_ACCESS_0, off158 */
uint pmc_gate; /* _GATE_0, offset 15C */
+ /* The following fields are in Tegra124 and later only */
+ uint pmc_wake2_mask; /* _WAKE2_MASK_0, offset 160 */
+ uint pmc_wake2_lvl; /* _WAKE2_LVL_0, offset 164 */
+ uint pmc_wake2_stat; /* _WAKE2_STATUS_0, offset 168 */
+ uint pmc_sw_wake2_stat; /* _SW_WAKE2_STATUS_0, offset 16C */
+ uint pmc_auto_wake2_lvl_mask; /* _AUTO_WAKE2_LVL_MASK_0, offset 170 */
+ uint pmc_pg_mask2; /* _PG_MASK_2_0, offset 174 */
+ uint pmc_pg_mask_ce1; /* _PG_MASK_CE1_0, offset 178 */
+ uint pmc_pg_mask_ce2; /* _PG_MASK_CE2_0, offset 17C */
+ uint pmc_pg_mask_ce3; /* _PG_MASK_CE3_0, offset 180 */
+ uint pmc_pwrgate_timer_ce0; /* _PWRGATE_TIMER_CE_0_0, offset 184 */
+ uint pmc_pwrgate_timer_ce1; /* _PWRGATE_TIMER_CE_1_0, offset 188 */
+ uint pmc_pwrgate_timer_ce2; /* _PWRGATE_TIMER_CE_2_0, offset 18C */
+ uint pmc_pwrgate_timer_ce3; /* _PWRGATE_TIMER_CE_3_0, offset 190 */
+ uint pmc_pwrgate_timer_ce4; /* _PWRGATE_TIMER_CE_4_0, offset 194 */
+ uint pmc_pwrgate_timer_ce5; /* _PWRGATE_TIMER_CE_5_0, offset 198 */
+ uint pmc_pwrgate_timer_ce6; /* _PWRGATE_TIMER_CE_6_0, offset 19C */
+ uint pmc_pcx_edpd_cntrl; /* _PCX_EDPD_CNTRL_0, offset 1A0 */
+ uint pmc_osc_edpd_over; /* _OSC_EDPD_OVER_0, offset 1A4 */
+ uint pmc_clk_out_cntrl; /* _CLK_OUT_CNTRL_0, offset 1A8 */
+ uint pmc_sata_pwrgate; /* _SATA_PWRGT_0, offset 1AC */
+ uint pmc_sensor_ctrl; /* _SENSOR_CTRL_0, offset 1B0 */
+ uint pmc_reset_status; /* _RTS_STATUS_0, offset 1B4 */
+ uint pmc_io_dpd_req; /* _IO_DPD_REQ_0, offset 1B8 */
+ uint pmc_io_dpd_stat; /* _IO_DPD_STATUS_0, offset 1BC */
+ uint pmc_io_dpd2_req; /* _IO_DPD2_REQ_0, offset 1C0 */
+ uint pmc_io_dpd2_stat; /* _IO_DPD2_STATUS_0, offset 1C4 */
+ uint pmc_sel_dpd_tim; /* _SEL_DPD_TIM_0, offset 1C8 */
+ uint pmc_vddp_sel; /* _VDDP_SEL_0, offset 1CC */
+
+ uint pmc_ddr_cfg; /* _DDR_CFG_0, offset 1D0 */
+ uint pmc_e_no_vttgen; /* _E_NO_VTTGEN_0, offset 1D4 */
+ uint pmc_reserved0; /* _RESERVED, offset 1D8 */
+ uint pmc_pllm_wb0_ovrride_frq; /* _PLLM_WB0_OVERRIDE_FREQ_0, off 1DC */
+ uint pmc_test_pwrgate; /* _TEST_PWRGATE_0, offset 1E0 */
+ uint pmc_pwrgate_timer_mult; /* _PWRGATE_TIMER_MULT_0, offset 1E4 */
+ uint pmc_dsi_sel_dpd; /* _DSI_SEL_DPD_0, offset 1E8 */
+ uint pmc_utmip_uhsic_triggers; /* _UTMIP_UHSIC_TRIGGERS_0, off 1EC */
+ uint pmc_utmip_uhsic_saved_st; /* _UTMIP_UHSIC_SAVED_STATE_0, off1F0 */
+ uint pmc_utmip_pad_cfg; /* _UTMIP_PAD_CFG_0, offset 1F4 */
+ uint pmc_utmip_term_pad_cfg; /* _UTMIP_TERM_PAD_CFG_0, offset 1F8 */
+ uint pmc_utmip_uhsic_sleep_cfg; /* _UTMIP_UHSIC_SLEEP_CFG_0, off 1FC */
+
+ uint pmc_todo_0[9]; /* offset 200-220 */
+ uint pmc_secure_scratch6; /* _SECURE_SCRATCH6_0, offset 224 */
+ uint pmc_secure_scratch7; /* _SECURE_SCRATCH7_0, offset 228 */
+ uint pmc_scratch43; /* _SCRATCH43_0, offset 22C */
+ uint pmc_scratch44; /* _SCRATCH44_0, offset 230 */
+ uint pmc_scratch45;
+ uint pmc_scratch46;
+ uint pmc_scratch47;
+ uint pmc_scratch48;
+ uint pmc_scratch49;
+ uint pmc_scratch50;
+ uint pmc_scratch51;
+ uint pmc_scratch52;
+ uint pmc_scratch53;
+ uint pmc_scratch54;
+ uint pmc_scratch55; /* _SCRATCH55_0, offset 25C */
+ uint pmc_scratch0_eco; /* _SCRATCH0_ECO_0, offset 260 */
+ uint pmc_por_dpd_ctrl; /* _POR_DPD_CTRL_0, offset 264 */
+ uint pmc_scratch2_eco; /* _SCRATCH2_ECO_0, offset 268 */
+ uint pmc_todo_1[17]; /* TODO: 26C ~ 2AC */
+ uint pmc_pllm_wb0_override2; /* _PLLM_WB0_OVERRIDE2, offset 2B0 */
+ uint pmc_tsc_mult; /* _TSC_MULT_0, offset 2B4 */
+ uint pmc_cpu_vsense_override; /* _CPU_VSENSE_OVERRIDE_0, offset 2B8 */
+ uint pmc_glb_amap_cfg; /* _GLB_AMAP_CFG_0, offset 2BC */
+ uint pmc_sticky_bits; /* _STICKY_BITS_0, offset 2C0 */
+ uint pmc_sec_disable2; /* _SEC_DISALBE2, offset 2C4 */
+ uint pmc_weak_bias; /* _WEAK_BIAS_0, offset 2C8 */
+ uint pmc_todo_3[13]; /* TODO: 2CC ~ 2FC */
+ uint pmc_secure_scratch8; /* _SECURE_SCRATCH8_0, offset 300 */
+ uint pmc_secure_scratch9;
+ uint pmc_secure_scratch10;
+ uint pmc_secure_scratch11;
+ uint pmc_secure_scratch12;
+ uint pmc_secure_scratch13;
+ uint pmc_secure_scratch14;
+ uint pmc_secure_scratch15;
+ uint pmc_secure_scratch16;
+ uint pmc_secure_scratch17;
+ uint pmc_secure_scratch18;
+ uint pmc_secure_scratch19;
+ uint pmc_secure_scratch20;
+ uint pmc_secure_scratch21;
+ uint pmc_secure_scratch22;
+ uint pmc_secure_scratch23;
+ uint pmc_secure_scratch24; /* _SECURE_SCRATCH24_0, offset 340 */
+ uint pmc_secure_scratch25;
+ uint pmc_secure_scratch26;
+ uint pmc_secure_scratch27;
+ uint pmc_secure_scratch28;
+ uint pmc_secure_scratch29;
+ uint pmc_secure_scratch30;
+ uint pmc_secure_scratch31;
+ uint pmc_secure_scratch32;
+ uint pmc_secure_scratch33;
+ uint pmc_secure_scratch34;
+ uint pmc_secure_scratch35; /* _SECURE_SCRATCH35_0, offset 36C */
+
+ uint pmc_reserved1[52]; /* RESERVED: 370 ~ 43C */
+ uint pmc_cntrl2; /* _CNTRL2_0, offset 440 */
+ uint pmc_reserved2[6]; /* RESERVED: 444 ~ 458 */
+ uint pmc_io_dpd3_req; /* _IO_DPD3_REQ_0, offset 45c */
+ uint pmc_io_dpd3_stat; /* _IO_DPD3_STATUS_0, offset 460 */
+ uint pmc_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 464 */
+ uint pmc_reserved3[102]; /* RESERVED: 468 ~ 5FC */
+
+ uint pmc_scratch56; /* _SCRATCH56_0, offset 600 */
+ uint pmc_scratch57;
+ uint pmc_scratch58;
+ uint pmc_scratch59;
+ uint pmc_scratch60;
+ uint pmc_scratch61;
+ uint pmc_scratch62;
+ uint pmc_scratch63;
+ uint pmc_scratch64;
+ uint pmc_scratch65;
+ uint pmc_scratch66;
+ uint pmc_scratch67;
+ uint pmc_scratch68;
+ uint pmc_scratch69;
+ uint pmc_scratch70;
+ uint pmc_scratch71;
+ uint pmc_scratch72;
+ uint pmc_scratch73;
+ uint pmc_scratch74;
+ uint pmc_scratch75;
+ uint pmc_scratch76;
+ uint pmc_scratch77;
+ uint pmc_scratch78;
+ uint pmc_scratch79;
+ uint pmc_scratch80;
+ uint pmc_scratch81;
+ uint pmc_scratch82;
+ uint pmc_scratch83;
+ uint pmc_scratch84;
+ uint pmc_scratch85;
+ uint pmc_scratch86;
+ uint pmc_scratch87;
+ uint pmc_scratch88;
+ uint pmc_scratch89;
+ uint pmc_scratch90;
+ uint pmc_scratch91;
+ uint pmc_scratch92;
+ uint pmc_scratch93;
+ uint pmc_scratch94;
+ uint pmc_scratch95;
+ uint pmc_scratch96;
+ uint pmc_scratch97;
+ uint pmc_scratch98;
+ uint pmc_scratch99;
+ uint pmc_scratch100;
+ uint pmc_scratch101;
+ uint pmc_scratch102;
+ uint pmc_scratch103;
+ uint pmc_scratch104;
+ uint pmc_scratch105;
+ uint pmc_scratch106;
+ uint pmc_scratch107;
+ uint pmc_scratch108;
+ uint pmc_scratch109;
+ uint pmc_scratch110;
+ uint pmc_scratch111;
+ uint pmc_scratch112;
+ uint pmc_scratch113;
+ uint pmc_scratch114;
+ uint pmc_scratch115;
+ uint pmc_scratch116;
+ uint pmc_scratch117;
+ uint pmc_scratch118;
+ uint pmc_scratch119;
+ uint pmc_scratch1_eco; /* offset 700 */
};
#define CPU_PWRED 1
@@ -122,4 +295,86 @@ struct pmc_ctlr {
#define CE0 14
#define C0NC 15
+#define PMC_XOFS_SHIFT 1
+#define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT)
+
+#define TIMER_MULT_SHIFT 0
+#define TIMER_MULT_MASK (3 << TIMER_MULT_SHIFT)
+#define TIMER_MULT_CPU_SHIFT 2
+#define TIMER_MULT_CPU_MASK (3 << TIMER_MULT_CPU_SHIFT)
+#define MULT_1 0
+#define MULT_2 1
+#define MULT_4 2
+#define MULT_8 3
+
+#define AMAP_WRITE_SHIFT 20
+#define AMAP_WRITE_ON (1 << AMAP_WRITE_SHIFT)
+
+/* SEC_DISABLE_0, 0x04 */
+#define SEC_DISABLE_WRITE0_ON (1 << 4)
+#define SEC_DISABLE_READ0_ON (1 << 5)
+#define SEC_DISABLE_WRITE1_ON (1 << 6)
+#define SEC_DISABLE_READ1_ON (1 << 7)
+#define SEC_DISABLE_WRITE2_ON (1 << 8)
+#define SEC_DISABLE_READ2_ON (1 << 9)
+#define SEC_DISABLE_WRITE3_ON (1 << 10)
+#define SEC_DISABLE_READ3_ON (1 << 11)
+#define SEC_DISABLE_AMAP_WRITE_ON (1 << 20)
+
+/* APBDEV_PMC_PWRGATE_TOGGLE_0 0x30 */
+#define PWRGATE_TOGGLE_PARTID_CRAIL 0
+#define PWRGATE_TOGGLE_PARTID_TD 1
+#define PWRGATE_TOGGLE_PARTID_VE 2
+#define PWRGATE_TOGGLE_PARTID_PCX 3
+#define PWRGATE_TOGGLE_PARTID_VDE 4
+#define PWRGATE_TOGGLE_PARTID_L2C 5
+#define PWRGATE_TOGGLE_PARTID_MPE 6
+#define PWRGATE_TOGGLE_PARTID_HEG 7
+#define PWRGATE_TOGGLE_PARTID_SAX 8
+#define PWRGATE_TOGGLE_PARTID_CE1 9
+#define PWRGATE_TOGGLE_PARTID_CE2 10
+#define PWRGATE_TOGGLE_PARTID_CE3 11
+#define PWRGATE_TOGGLE_PARTID_CELP 12
+#define PWRGATE_TOGGLE_PARTID_CE0 14
+#define PWRGATE_TOGGLE_PARTID_C0NC 15
+#define PWRGATE_TOGGLE_PARTID_C1NC 16
+#define PWRGATE_TOGGLE_PARTID_SOR 17
+#define PWRGATE_TOGGLE_PARTID_DIS 18
+#define PWRGATE_TOGGLE_PARTID_DISB 19
+#define PWRGATE_TOGGLE_PARTID_XUSBA 20
+#define PWRGATE_TOGGLE_PARTID_XUSBB 21
+#define PWRGATE_TOGGLE_PARTID_XUSBC 22
+#define PWRGATE_TOGGLE_PARTID_VIC 23
+#define PWRGATE_TOGGLE_PARTID_IRAM 24
+#define PWRGATE_TOGGLE_START (1 << 8)
+
+/* APBDEV_PMC_PWRGATE_STATUS_0 0x38 */
+#define PWRGATE_STATUS_CRAIL_ENABLE (1 << 0)
+#define PWRGATE_STATUS_TD_ENABLE (1 << 1)
+#define PWRGATE_STATUS_VE_ENABLE (1 << 2)
+#define PWRGATE_STATUS_PCX_ENABLE (1 << 3)
+#define PWRGATE_STATUS_VDE_ENABLE (1 << 4)
+#define PWRGATE_STATUS_L2C_ENABLE (1 << 5)
+#define PWRGATE_STATUS_MPE_ENABLE (1 << 6)
+#define PWRGATE_STATUS_HEG_ENABLE (1 << 7)
+#define PWRGATE_STATUS_SAX_ENABLE (1 << 8)
+#define PWRGATE_STATUS_CE1_ENABLE (1 << 9)
+#define PWRGATE_STATUS_CE2_ENABLE (1 << 10)
+#define PWRGATE_STATUS_CE3_ENABLE (1 << 11)
+#define PWRGATE_STATUS_CELP_ENABLE (1 << 12)
+#define PWRGATE_STATUS_CE0_ENABLE (1 << 14)
+#define PWRGATE_STATUS_C0NC_ENABLE (1 << 15)
+#define PWRGATE_STATUS_C1NC_ENABLE (1 << 16)
+#define PWRGATE_STATUS_SOR_ENABLE (1 << 17)
+#define PWRGATE_STATUS_DIS_ENABLE (1 << 18)
+#define PWRGATE_STATUS_DISB_ENABLE (1 << 19)
+#define PWRGATE_STATUS_XUSBA_ENABLE (1 << 20)
+#define PWRGATE_STATUS_XUSBB_ENABLE (1 << 21)
+#define PWRGATE_STATUS_XUSBC_ENABLE (1 << 22)
+#define PWRGATE_STATUS_VIC_ENABLE (1 << 23)
+#define PWRGATE_STATUS_IRAM_ENABLE (1 << 24)
+
+/* APBDEV_PMC_CNTRL2_0 0x440 */
+#define HOLD_CKE_LOW_EN (1 << 12)
+
#endif /* PMC_H */
diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
index e99f681..5fe19ae 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -68,6 +68,7 @@ enum {
SKU_ID_TM30MQS_P_A3 = 0xb1,
SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */
SKU_ID_T114_1 = 0x01,
+ SKU_ID_T124_ENG = 0x00, /* Venice2 value, unfused */
};
/*
@@ -81,6 +82,7 @@ enum {
TEGRA_SOC_T25,
TEGRA_SOC_T30,
TEGRA_SOC_T114,
+ TEGRA_SOC_T124,
TEGRA_SOC_CNT,
TEGRA_SOC_UNKNOWN = -1,
diff --git a/arch/arm/include/asm/arch-tegra124/ahb.h b/arch/arm/include/asm/arch-tegra124/ahb.h
new file mode 100644
index 0000000..4e48c43
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/ahb.h
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA124_AHB_H_
+#define _TEGRA124_AHB_H_
+
+struct ahb_ctlr {
+ u32 reserved0; /* 00h */
+ u32 arbitration_disable; /* _ARBITRATION_DISABLE_0, 04h */
+ u32 arbitration_priority_ctrl; /* _ARBITRATION_PRIORITY_CTRL_0,08h */
+ u32 arbitration_usr_protect; /* _ARBITRATION_USR_PROTECT_0, 0ch */
+ u32 gizmo_ahb_mem; /* _GIZMO_AHB_MEM_0, 10h */
+ u32 gizmo_apb_dma; /* _GIZMO_APB_DMA_0, 14h */
+ u32 reserved6[2]; /* 18h, 1ch */
+ u32 gizmo_usb; /* _GIZMO_USB_0, 20h */
+ u32 gizmo_ahb_xbar_bridge; /* _GIZMO_AHB_XBAR_BRIDGE_0, 24h */
+ u32 gizmo_cpu_ahb_bridge; /* _GIZMO_CPU_AHB_BRIDGE_0, 28h */
+ u32 gizmo_cop_ahb_bridge; /* _GIZMO_COP_AHB_BRIDGE_0, 2ch */
+ u32 gizmo_xbar_apb_ctlr; /* _GIZMO_XBAR_APB_CTLR_0, 30h */
+ u32 gizmo_vcp_ahb_bridge; /* _GIZMO_VCP_AHB_BRIDGE_0, 34h */
+ u32 reserved13[2]; /* 38h, 3ch */
+ u32 gizmo_nand; /* _GIZMO_NAND_0, 40h */
+ u32 reserved15; /* 44h */
+ u32 gizmo_sdmmc4; /* _GIZMO_SDMMC4_0, 48h */
+ u32 reserved17; /* 4ch */
+ u32 gizmo_se; /* _GIZMO_SE_0, 50h */
+ u32 gizmo_tzram; /* _GIZMO_TZRAM_0, 54h */
+ u32 reserved20[3]; /* 58h, 5ch, 60h */
+ u32 gizmo_bsev; /* _GIZMO_BSEV_0, 64h */
+ u32 reserved22[3]; /* 68h, 6ch, 70h */
+ u32 gizmo_bsea; /* _GIZMO_BSEA_0, 74h */
+ u32 gizmo_nor; /* _GIZMO_NOR_0, 78h */
+ u32 gizmo_usb2; /* _GIZMO_USB2_0, 7ch */
+ u32 gizmo_usb3; /* _GIZMO_USB3_0, 80h */
+ u32 gizmo_sdmmc1; /* _GIZMO_SDMMC1_0, 84h */
+ u32 gizmo_sdmmc2; /* _GIZMO_SDMMC2_0, 88h */
+ u32 gizmo_sdmmc3; /* _GIZMO_SDMMC3_0, 8ch */
+ u32 reserved30[13]; /* 90h ~ c0h */
+ u32 ahb_wrq_empty; /* _AHB_WRQ_EMPTY_0, c4h */
+ u32 reserved32[5]; /* c8h ~ d8h */
+ u32 ahb_mem_prefetch_cfg_x; /* _AHB_MEM_PREFETCH_CFG_X_0, dch */
+ u32 arbitration_xbar_ctrl; /* _ARBITRATION_XBAR_CTRL_0, e0h */
+ u32 ahb_mem_prefetch_cfg3; /* _AHB_MEM_PREFETCH_CFG3_0, e4h */
+ u32 ahb_mem_prefetch_cfg4; /* _AHB_MEM_PREFETCH_CFG3_0, e8h */
+ u32 avp_ppcs_rd_coh_status; /* _AVP_PPCS_RD_COH_STATUS_0, ech */
+ u32 ahb_mem_prefetch_cfg1; /* _AHB_MEM_PREFETCH_CFG1_0, f0h */
+ u32 ahb_mem_prefetch_cfg2; /* _AHB_MEM_PREFETCH_CFG2_0, f4h */
+ u32 ahbslvmem_status; /* _AHBSLVMEM_STATUS_0, f8h */
+ /* _ARBITRATION_AHB_MEM_WRQUE_MST_ID_0, fch */
+ u32 arbitration_ahb_mem_wrque_mst_id;
+ u32 arbitration_cpu_abort_addr; /* _ARBITRATION_CPU_ABORT_ADDR_0,100h */
+ u32 arbitration_cpu_abort_info; /* _ARBITRATION_CPU_ABORT_INFO_0,104h */
+ u32 arbitration_cop_abort_addr; /* _ARBITRATION_COP_ABORT_ADDR_0,108h */
+ u32 arbitration_cop_abort_info; /* _ARBITRATION_COP_ABORT_INFO_0,10ch */
+ u32 reserved46[4]; /* 110h ~ 11ch */
+ u32 avpc_mccif_fifoctrl; /* _AVPC_MCCIF_FIFOCTRL_0, 120h */
+ u32 timeout_wcoal_avpc; /* _TIMEOUT_WCOAL_AVPC_0, 124h */
+ u32 mpcorelp_mccif_fifoctrl; /* _MPCORELP_MCCIF_FIFOCTRL_0, 128h */
+ u32 mpcore_mccif_fifoctrl; /* _MPCORE_MCCIF_FIFOCTRL_0, 12ch */
+ u32 axicif_fastsync_ctrl; /* AXICIF_FASTSYNC_CTRL_0, 130h */
+ u32 axicif_fastsync_statistics; /* _AXICIF_FASTSYNC_STATISTICS_0,134h */
+ /* _AXICIF_FASTSYNC0_CPUCLK_TO_MCCLK_0, 138h */
+ u32 axicif_fastsync0_cpuclk_to_mcclk;
+ /* _AXICIF_FASTSYNC1_CPUCLK_TO_MCCLK_0, 13ch */
+ u32 axicif_fastsync1_cpuclk_to_mcclk;
+ /* _AXICIF_FASTSYNC2_CPUCLK_TO_MCCLK_0, 140h */
+ u32 axicif_fastsync2_cpuclk_to_mcclk;
+ /* _AXICIF_FASTSYNC0_MCCLK_TO_CPUCLK_0, 144h */
+ u32 axicif_fastsync0_mcclk_to_cpuclk;
+ /* _AXICIF_FASTSYNC1_MCCLK_TO_CPUCLK_0, 148h */
+ u32 axicif_fastsync1_mcclk_to_cpuclk;
+ /* _AXICIF_FASTSYNC2_MCCLK_TO_CPUCLK_0, 14ch */
+ u32 axicif_fastsync2_mcclk_to_cpuclk;
+};
+
+#define PPSB_STOPCLK_ENABLE (1 << 2)
+
+#define GIZ_ENABLE_SPLIT (1 << 0)
+#define GIZ_ENB_FAST_REARB (1 << 2)
+#define GIZ_DONT_SPLIT_AHB_WR (1 << 7)
+
+#define GIZ_USB_IMMEDIATE (1 << 18)
+
+/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */
+#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE (1 << 2)
+
+#endif /* _TEGRA124_AHB_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/clock-tables.h b/arch/arm/include/asm/arch-tegra124/clock-tables.h
new file mode 100644
index 0000000..daf9a2b
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/clock-tables.h
@@ -0,0 +1,496 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Tegra124 clock PLL tables */
+
+#ifndef _TEGRA124_CLOCK_TABLES_H_
+#define _TEGRA124_CLOCK_TABLES_H_
+
+/* The PLLs supported by the hardware */
+enum clock_id {
+ CLOCK_ID_FIRST,
+ CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
+ CLOCK_ID_MEMORY,
+ CLOCK_ID_PERIPH,
+ CLOCK_ID_AUDIO,
+ CLOCK_ID_USB,
+ CLOCK_ID_DISPLAY,
+
+ /* now the simple ones */
+ CLOCK_ID_FIRST_SIMPLE,
+ CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
+ CLOCK_ID_EPCI,
+ CLOCK_ID_SFROM32KHZ,
+
+ /* These are the base clocks (inputs to the Tegra SoC) */
+ CLOCK_ID_32KHZ,
+ CLOCK_ID_OSC,
+
+ CLOCK_ID_COUNT, /* number of PLLs */
+
+ /*
+ * These are clock IDs that are used in table clock_source[][]
+ * but will not be assigned as a clock source for any peripheral.
+ */
+ CLOCK_ID_DISPLAY2,
+ CLOCK_ID_CGENERAL2,
+ CLOCK_ID_CGENERAL3,
+ CLOCK_ID_MEMORY2,
+ CLOCK_ID_SRC2,
+
+ CLOCK_ID_NONE = -1,
+};
+
+/* The clocks supported by the hardware */
+enum periph_id {
+ PERIPH_ID_FIRST,
+
+ /* Low word: 31:0 (DEVICES_L) */
+ PERIPH_ID_CPU = PERIPH_ID_FIRST,
+ PERIPH_ID_COP,
+ PERIPH_ID_TRIGSYS,
+ PERIPH_ID_ISPB,
+ PERIPH_ID_RESERVED4,
+ PERIPH_ID_TMR,
+ PERIPH_ID_UART1,
+ PERIPH_ID_UART2,
+
+ /* 8 */
+ PERIPH_ID_GPIO,
+ PERIPH_ID_SDMMC2,
+ PERIPH_ID_SPDIF,
+ PERIPH_ID_I2S1,
+ PERIPH_ID_I2C1,
+ PERIPH_ID_RESERVED13,
+ PERIPH_ID_SDMMC1,
+ PERIPH_ID_SDMMC4,
+
+ /* 16 */
+ PERIPH_ID_TCW,
+ PERIPH_ID_PWM,
+ PERIPH_ID_I2S2,
+ PERIPH_ID_RESERVED19,
+ PERIPH_ID_VI,
+ PERIPH_ID_RESERVED21,
+ PERIPH_ID_USBD,
+ PERIPH_ID_ISP,
+
+ /* 24 */
+ PERIPH_ID_RESERVED24,
+ PERIPH_ID_RESERVED25,
+ PERIPH_ID_DISP2,
+ PERIPH_ID_DISP1,
+ PERIPH_ID_HOST1X,
+ PERIPH_ID_VCP,
+ PERIPH_ID_I2S0,
+ PERIPH_ID_CACHE2,
+
+ /* Middle word: 63:32 (DEVICES_H) */
+ PERIPH_ID_MEM,
+ PERIPH_ID_AHBDMA,
+ PERIPH_ID_APBDMA,
+ PERIPH_ID_RESERVED35,
+ PERIPH_ID_RESERVED36,
+ PERIPH_ID_STAT_MON,
+ PERIPH_ID_RESERVED38,
+ PERIPH_ID_FUSE,
+
+ /* 40 */
+ PERIPH_ID_KFUSE,
+ PERIPH_ID_SBC1,
+ PERIPH_ID_SNOR,
+ PERIPH_ID_RESERVED43,
+ PERIPH_ID_SBC2,
+ PERIPH_ID_XIO,
+ PERIPH_ID_SBC3,
+ PERIPH_ID_I2C5,
+
+ /* 48 */
+ PERIPH_ID_DSI,
+ PERIPH_ID_RESERVED49,
+ PERIPH_ID_HSI,
+ PERIPH_ID_HDMI,
+ PERIPH_ID_CSI,
+ PERIPH_ID_RESERVED53,
+ PERIPH_ID_I2C2,
+ PERIPH_ID_UART3,
+
+ /* 56 */
+ PERIPH_ID_MIPI_CAL,
+ PERIPH_ID_EMC,
+ PERIPH_ID_USB2,
+ PERIPH_ID_USB3,
+ PERIPH_ID_RESERVED60,
+ PERIPH_ID_VDE,
+ PERIPH_ID_BSEA,
+ PERIPH_ID_BSEV,
+
+ /* Upper word 95:64 (DEVICES_U) */
+ PERIPH_ID_RESERVED64,
+ PERIPH_ID_UART4,
+ PERIPH_ID_UART5,
+ PERIPH_ID_I2C3,
+ PERIPH_ID_SBC4,
+ PERIPH_ID_SDMMC3,
+ PERIPH_ID_PCIE,
+ PERIPH_ID_OWR,
+
+ /* 72 */
+ PERIPH_ID_AFI,
+ PERIPH_ID_CORESIGHT,
+ PERIPH_ID_PCIEXCLK,
+ PERIPH_ID_AVPUCQ,
+ PERIPH_ID_LA,
+ PERIPH_ID_TRACECLKIN,
+ PERIPH_ID_SOC_THERM,
+ PERIPH_ID_DTV,
+
+ /* 80 */
+ PERIPH_ID_RESERVED80,
+ PERIPH_ID_I2CSLOW,
+ PERIPH_ID_DSIB,
+ PERIPH_ID_TSEC,
+ PERIPH_ID_RESERVED84,
+ PERIPH_ID_RESERVED85,
+ PERIPH_ID_RESERVED86,
+ PERIPH_ID_EMUCIF,
+
+ /* 88 */
+ PERIPH_ID_RESERVED88,
+ PERIPH_ID_XUSB_HOST,
+ PERIPH_ID_RESERVED90,
+ PERIPH_ID_MSENC,
+ PERIPH_ID_RESERVED92,
+ PERIPH_ID_RESERVED93,
+ PERIPH_ID_RESERVED94,
+ PERIPH_ID_XUSB_DEV,
+
+ PERIPH_ID_VW_FIRST,
+ /* V word: 31:0 */
+ PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
+ PERIPH_ID_CPULP,
+ PERIPH_ID_V_RESERVED2,
+ PERIPH_ID_MSELECT,
+ PERIPH_ID_V_RESERVED4,
+ PERIPH_ID_I2S3,
+ PERIPH_ID_I2S4,
+ PERIPH_ID_I2C4,
+
+ /* 104 */
+ PERIPH_ID_SBC5,
+ PERIPH_ID_SBC6,
+ PERIPH_ID_AUDIO,
+ PERIPH_ID_APBIF,
+ PERIPH_ID_DAM0,
+ PERIPH_ID_DAM1,
+ PERIPH_ID_DAM2,
+ PERIPH_ID_HDA2CODEC2X,
+
+ /* 112 */
+ PERIPH_ID_ATOMICS,
+ PERIPH_ID_V_RESERVED17,
+ PERIPH_ID_V_RESERVED18,
+ PERIPH_ID_V_RESERVED19,
+ PERIPH_ID_V_RESERVED20,
+ PERIPH_ID_V_RESERVED21,
+ PERIPH_ID_V_RESERVED22,
+ PERIPH_ID_ACTMON,
+
+ /* 120 */
+ PERIPH_ID_EXTPERIPH1,
+ PERIPH_ID_EXTPERIPH2,
+ PERIPH_ID_EXTPERIPH3,
+ PERIPH_ID_OOB,
+ PERIPH_ID_SATA,
+ PERIPH_ID_HDA,
+ PERIPH_ID_V_RESERVED30,
+ PERIPH_ID_V_RESERVED31,
+
+ /* W word: 31:0 */
+ PERIPH_ID_HDA2HDMICODEC,
+ PERIPH_ID_SATACOLD,
+ PERIPH_ID_W_RESERVED2,
+ PERIPH_ID_W_RESERVED3,
+ PERIPH_ID_W_RESERVED4,
+ PERIPH_ID_W_RESERVED5,
+ PERIPH_ID_W_RESERVED6,
+ PERIPH_ID_W_RESERVED7,
+
+ /* 136 */
+ PERIPH_ID_CEC,
+ PERIPH_ID_W_RESERVED9,
+ PERIPH_ID_W_RESERVED10,
+ PERIPH_ID_W_RESERVED11,
+ PERIPH_ID_W_RESERVED12,
+ PERIPH_ID_W_RESERVED13,
+ PERIPH_ID_XUSB_PADCTL,
+ PERIPH_ID_W_RESERVED15,
+
+ /* 144 */
+ PERIPH_ID_W_RESERVED16,
+ PERIPH_ID_W_RESERVED17,
+ PERIPH_ID_W_RESERVED18,
+ PERIPH_ID_W_RESERVED19,
+ PERIPH_ID_W_RESERVED20,
+ PERIPH_ID_ENTROPY,
+ PERIPH_ID_DDS,
+ PERIPH_ID_W_RESERVED23,
+
+ /* 152 */
+ PERIPH_ID_DP2,
+ PERIPH_ID_AMX0,
+ PERIPH_ID_ADX0,
+ PERIPH_ID_DVFS,
+ PERIPH_ID_XUSB_SS,
+ PERIPH_ID_W_RESERVED29,
+ PERIPH_ID_W_RESERVED30,
+ PERIPH_ID_W_RESERVED31,
+
+ PERIPH_ID_X_FIRST,
+ /* X word: 31:0 */
+ PERIPH_ID_SPARE = PERIPH_ID_X_FIRST,
+ PERIPH_ID_X_RESERVED1,
+ PERIPH_ID_X_RESERVED2,
+ PERIPH_ID_X_RESERVED3,
+ PERIPH_ID_CAM_MCLK,
+ PERIPH_ID_CAM_MCLK2,
+ PERIPH_ID_I2C6,
+ PERIPH_ID_X_RESERVED7,
+
+ /* 168 */
+ PERIPH_ID_X_RESERVED8,
+ PERIPH_ID_X_RESERVED9,
+ PERIPH_ID_X_RESERVED10,
+ PERIPH_ID_VIM2_CLK,
+ PERIPH_ID_X_RESERVED12,
+ PERIPH_ID_X_RESERVED13,
+ PERIPH_ID_EMC_DLL,
+ PERIPH_ID_X_RESERVED15,
+
+ /* 176 */
+ PERIPH_ID_HDMI_AUDIO,
+ PERIPH_ID_CLK72MHZ,
+ PERIPH_ID_VIC,
+ PERIPH_ID_X_RESERVED19,
+ PERIPH_ID_ADX1,
+ PERIPH_ID_DPAUX,
+ PERIPH_ID_SOR0,
+ PERIPH_ID_X_RESERVED23,
+
+ /* 184 */
+ PERIPH_ID_GPU,
+ PERIPH_ID_AMX1,
+ PERIPH_ID_X_RESERVED26,
+ PERIPH_ID_X_RESERVED27,
+ PERIPH_ID_X_RESERVED28,
+ PERIPH_ID_X_RESERVED29,
+ PERIPH_ID_X_RESERVED30,
+ PERIPH_ID_X_RESERVED31,
+
+ PERIPH_ID_COUNT,
+ PERIPH_ID_NONE = -1,
+};
+
+enum pll_out_id {
+ PLL_OUT1,
+ PLL_OUT2,
+ PLL_OUT3,
+ PLL_OUT4
+};
+
+/*
+ * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
+ * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
+ * confusion bewteen PERIPH_ID_... and PERIPHC_...
+ *
+ * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
+ * confusing.
+ */
+enum periphc_internal_id {
+ /* 0x00 */
+ PERIPHC_I2S1,
+ PERIPHC_I2S2,
+ PERIPHC_SPDIF_OUT,
+ PERIPHC_SPDIF_IN,
+ PERIPHC_PWM,
+ PERIPHC_05h,
+ PERIPHC_SBC2,
+ PERIPHC_SBC3,
+
+ /* 0x08 */
+ PERIPHC_08h,
+ PERIPHC_I2C1,
+ PERIPHC_I2C5,
+ PERIPHC_0bh,
+ PERIPHC_0ch,
+ PERIPHC_SBC1,
+ PERIPHC_DISP1,
+ PERIPHC_DISP2,
+
+ /* 0x10 */
+ PERIPHC_10h,
+ PERIPHC_11h,
+ PERIPHC_VI,
+ PERIPHC_13h,
+ PERIPHC_SDMMC1,
+ PERIPHC_SDMMC2,
+ PERIPHC_G3D,
+ PERIPHC_G2D,
+
+ /* 0x18 */
+ PERIPHC_18h,
+ PERIPHC_SDMMC4,
+ PERIPHC_VFIR,
+ PERIPHC_1Bh,
+ PERIPHC_1Ch,
+ PERIPHC_HSI,
+ PERIPHC_UART1,
+ PERIPHC_UART2,
+
+ /* 0x20 */
+ PERIPHC_HOST1X,
+ PERIPHC_21h,
+ PERIPHC_22h,
+ PERIPHC_HDMI,
+ PERIPHC_24h,
+ PERIPHC_25h,
+ PERIPHC_I2C2,
+ PERIPHC_EMC,
+
+ /* 0x28 */
+ PERIPHC_UART3,
+ PERIPHC_29h,
+ PERIPHC_VI_SENSOR,
+ PERIPHC_2bh,
+ PERIPHC_2ch,
+ PERIPHC_SBC4,
+ PERIPHC_I2C3,
+ PERIPHC_SDMMC3,
+
+ /* 0x30 */
+ PERIPHC_UART4,
+ PERIPHC_UART5,
+ PERIPHC_VDE,
+ PERIPHC_OWR,
+ PERIPHC_NOR,
+ PERIPHC_CSITE,
+ PERIPHC_I2S0,
+ PERIPHC_DTV,
+
+ /* 0x38 */
+ PERIPHC_38h,
+ PERIPHC_39h,
+ PERIPHC_3ah,
+ PERIPHC_3bh,
+ PERIPHC_MSENC,
+ PERIPHC_TSEC,
+ PERIPHC_3eh,
+ PERIPHC_OSC,
+
+ PERIPHC_VW_FIRST,
+ /* 0x40 */
+ PERIPHC_40h = PERIPHC_VW_FIRST,
+ PERIPHC_MSELECT,
+ PERIPHC_TSENSOR,
+ PERIPHC_I2S3,
+ PERIPHC_I2S4,
+ PERIPHC_I2C4,
+ PERIPHC_SBC5,
+ PERIPHC_SBC6,
+
+ /* 0x48 */
+ PERIPHC_AUDIO,
+ PERIPHC_49h,
+ PERIPHC_DAM0,
+ PERIPHC_DAM1,
+ PERIPHC_DAM2,
+ PERIPHC_HDA2CODEC2X,
+ PERIPHC_ACTMON,
+ PERIPHC_EXTPERIPH1,
+
+ /* 0x50 */
+ PERIPHC_EXTPERIPH2,
+ PERIPHC_EXTPERIPH3,
+ PERIPHC_52h,
+ PERIPHC_I2CSLOW,
+ PERIPHC_SYS,
+ PERIPHC_55h,
+ PERIPHC_56h,
+ PERIPHC_57h,
+
+ /* 0x58 */
+ PERIPHC_58h,
+ PERIPHC_59h,
+ PERIPHC_5ah,
+ PERIPHC_5bh,
+ PERIPHC_SATAOOB,
+ PERIPHC_SATA,
+ PERIPHC_HDA, /* 0x428 */
+ PERIPHC_5fh,
+
+ PERIPHC_X_FIRST,
+ /* 0x60 */
+ PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST, /* 0x600 */
+ PERIPHC_XUSB_FALCON,
+ PERIPHC_XUSB_FS,
+ PERIPHC_XUSB_CORE_DEV,
+ PERIPHC_XUSB_SS,
+ PERIPHC_CILAB,
+ PERIPHC_CILCD,
+ PERIPHC_CILE,
+
+ /* 0x68 */
+ PERIPHC_DSIA_LP,
+ PERIPHC_DSIB_LP,
+ PERIPHC_ENTROPY,
+ PERIPHC_DVFS_REF,
+ PERIPHC_DVFS_SOC,
+ PERIPHC_TRACECLKIN,
+ PERIPHC_ADX0,
+ PERIPHC_AMX0,
+
+ /* 0x70 */
+ PERIPHC_EMC_LATENCY,
+ PERIPHC_SOC_THERM,
+ PERIPHC_72h,
+ PERIPHC_73h,
+ PERIPHC_74h,
+ PERIPHC_75h,
+ PERIPHC_VI_SENSOR2,
+ PERIPHC_I2C6,
+
+ /* 0x78 */
+ PERIPHC_78h,
+ PERIPHC_EMC_DLL,
+ PERIPHC_HDMI_AUDIO,
+ PERIPHC_CLK72MHZ,
+ PERIPHC_ADX1,
+ PERIPHC_AMX1,
+ PERIPHC_VIC,
+ PERIPHC_7fh,
+
+ PERIPHC_COUNT,
+
+ PERIPHC_NONE = -1,
+};
+
+/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
+#define PERIPH_REG(id) \
+ (id < PERIPH_ID_VW_FIRST) ? \
+ ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
+
+/* Mask value for a clock (within PERIPH_REG(id)) */
+#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
+
+/* return 1 if a PLL ID is in range */
+#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
+
+/* return 1 if a peripheral ID is in range */
+#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
+ (id) < PERIPH_ID_COUNT)
+
+#endif /* _TEGRA124_CLOCK_TABLES_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/clock.h b/arch/arm/include/asm/arch-tegra124/clock.h
new file mode 100644
index 0000000..8e39d21
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/clock.h
@@ -0,0 +1,19 @@
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Tegra124 clock control definitions */
+
+#ifndef _TEGRA124_CLOCK_H_
+#define _TEGRA124_CLOCK_H_
+
+#include
+
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
+#define OSC_FREQ_SHIFT 28
+#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
+
+#endif /* _TEGRA124_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/flow.h b/arch/arm/include/asm/arch-tegra124/flow.h
new file mode 100644
index 0000000..0db1881
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/flow.h
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA124_FLOW_H_
+#define _TEGRA124_FLOW_H_
+
+struct flow_ctlr {
+ u32 halt_cpu_events; /* offset 0x00 */
+ u32 halt_cop_events; /* offset 0x04 */
+ u32 cpu_csr; /* offset 0x08 */
+ u32 cop_csr; /* offset 0x0c */
+ u32 xrq_events; /* offset 0x10 */
+ u32 halt_cpu1_events; /* offset 0x14 */
+ u32 cpu1_csr; /* offset 0x18 */
+ u32 halt_cpu2_events; /* offset 0x1c */
+ u32 cpu2_csr; /* offset 0x20 */
+ u32 halt_cpu3_events; /* offset 0x24 */
+ u32 cpu3_csr; /* offset 0x28 */
+ u32 cluster_control; /* offset 0x2c */
+ u32 halt_cop1_events; /* offset 0x30 */
+ u32 halt_cop1_csr; /* offset 0x34 */
+ u32 cpu_pwr_csr; /* offset 0x38 */
+ u32 mpid; /* offset 0x3c */
+ u32 ram_repair; /* offset 0x40 */
+};
+
+/* HALT_COP_EVENTS_0, 0x04 */
+#define EVENT_MSEC (1 << 24)
+#define EVENT_USEC (1 << 25)
+#define EVENT_JTAG (1 << 28)
+#define EVENT_MODE_STOP (2 << 29)
+
+/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */
+#define ACTIVE_LP (1 << 0)
+
+#endif /* _TEGRA124_FLOW_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/funcmux.h b/arch/arm/include/asm/arch-tegra124/funcmux.h
new file mode 100644
index 0000000..df94d13
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/funcmux.h
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Tegra124 high-level function multiplexing */
+
+#ifndef _TEGRA124_FUNCMUX_H_
+#define _TEGRA124_FUNCMUX_H_
+
+#include
+
+/* Configs supported by the func mux */
+enum {
+ FUNCMUX_DEFAULT = 0, /* default config */
+
+ /* UART configs */
+ FUNCMUX_UART1_KBC = 0,
+ FUNCMUX_UART4_GPIO = 0,
+};
+#endif /* _TEGRA124_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/gp_padctrl.h b/arch/arm/include/asm/arch-tegra124/gp_padctrl.h
new file mode 100644
index 0000000..440cbbf
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/gp_padctrl.h
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA124_GP_PADCTRL_H_
+#define _TEGRA124_GP_PADCTRL_H_
+
+#include
+
+/* APB_MISC_GP and padctrl registers */
+struct apb_misc_gp_ctlr {
+ u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
+ u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
+ u32 reserved0[22]; /* 0x08 - 0x5C: */
+ u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
+ u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
+ u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
+ u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
+ u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
+ u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
+ u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
+ u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
+ u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
+ u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
+ u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
+ u32 reserved1; /* 0x8C: */
+ u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
+ u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
+ u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
+ u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
+ u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
+ u32 reserved2[3]; /* 0xA4 - 0xAC: */
+ u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
+ u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
+ u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
+ u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
+ u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
+ u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
+ u32 reserved3[9]; /* 0xC8-0xE8: */
+ u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
+ u32 reserved4[3]; /* 0xF0-0xF8: */
+ u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */
+ u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */
+ u32 reserved5[3]; /* 0x104-0x10C: */
+ u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */
+ u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */
+ u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */
+ u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */
+ u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */
+ u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */
+ u32 reserved6; /* 0x128: */
+ u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */
+ u32 reserved7[2]; /* 0x130 - 0x134: */
+ u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */
+ u32 reserved8[22]; /* 0x13C - 0x190: */
+ u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */
+ u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */
+ u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */
+ u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */
+ u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */
+ u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */
+ u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */
+};
+
+/* SDMMC1/3 settings from section 27.5 of T114 TRM */
+#define SDIOCFG_DRVUP_SLWF 0
+#define SDIOCFG_DRVDN_SLWR 0
+#define SDIOCFG_DRVUP 0x24
+#define SDIOCFG_DRVDN 0x14
+
+#endif /* _TEGRA124_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/gpio.h b/arch/arm/include/asm/arch-tegra124/gpio.h
new file mode 100644
index 0000000..1a6dcb8
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/gpio.h
@@ -0,0 +1,303 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA124_GPIO_H_
+#define _TEGRA124_GPIO_H_
+
+/*
+ * The Tegra124 GPIO controller has 256 GPIOS in 8 banks of 4 ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */
+#define TEGRA_GPIO_BANKS 8 /* number of banks */
+
+#include
+
+/* GPIO Controller registers for a single bank */
+struct gpio_ctlr_bank {
+ uint gpio_config[TEGRA_GPIO_PORTS];
+ uint gpio_dir_out[TEGRA_GPIO_PORTS];
+ uint gpio_out[TEGRA_GPIO_PORTS];
+ uint gpio_in[TEGRA_GPIO_PORTS];
+ uint gpio_int_status[TEGRA_GPIO_PORTS];
+ uint gpio_int_enable[TEGRA_GPIO_PORTS];
+ uint gpio_int_level[TEGRA_GPIO_PORTS];
+ uint gpio_int_clear[TEGRA_GPIO_PORTS];
+ uint gpio_masked_config[TEGRA_GPIO_PORTS];
+ uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
+ uint gpio_masked_out[TEGRA_GPIO_PORTS];
+ uint gpio_masked_in[TEGRA_GPIO_PORTS];
+ uint gpio_masked_int_status[TEGRA_GPIO_PORTS];
+ uint gpio_masked_int_enable[TEGRA_GPIO_PORTS];
+ uint gpio_masked_int_level[TEGRA_GPIO_PORTS];
+ uint gpio_masked_int_clear[TEGRA_GPIO_PORTS];
+};
+
+struct gpio_ctlr {
+ struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
+};
+
+enum gpio_pin {
+ GPIO_PA0 = 0, /* pin 0 */
+ GPIO_PA1,
+ GPIO_PA2,
+ GPIO_PA3,
+ GPIO_PA4,
+ GPIO_PA5,
+ GPIO_PA6,
+ GPIO_PA7,
+ GPIO_PB0, /* pin 8 */
+ GPIO_PB1,
+ GPIO_PB2,
+ GPIO_PB3,
+ GPIO_PB4,
+ GPIO_PB5,
+ GPIO_PB6,
+ GPIO_PB7,
+ GPIO_PC0, /* pin 16 */
+ GPIO_PC1,
+ GPIO_PC2,
+ GPIO_PC3,
+ GPIO_PC4,
+ GPIO_PC5,
+ GPIO_PC6,
+ GPIO_PC7,
+ GPIO_PD0, /* pin 24 */
+ GPIO_PD1,
+ GPIO_PD2,
+ GPIO_PD3,
+ GPIO_PD4,
+ GPIO_PD5,
+ GPIO_PD6,
+ GPIO_PD7,
+ GPIO_PE0, /* pin 32 */
+ GPIO_PE1,
+ GPIO_PE2,
+ GPIO_PE3,
+ GPIO_PE4,
+ GPIO_PE5,
+ GPIO_PE6,
+ GPIO_PE7,
+ GPIO_PF0, /* pin 40 */
+ GPIO_PF1,
+ GPIO_PF2,
+ GPIO_PF3,
+ GPIO_PF4,
+ GPIO_PF5,
+ GPIO_PF6,
+ GPIO_PF7,
+ GPIO_PG0, /* pin 48 */
+ GPIO_PG1,
+ GPIO_PG2,
+ GPIO_PG3,
+ GPIO_PG4,
+ GPIO_PG5,
+ GPIO_PG6,
+ GPIO_PG7,
+ GPIO_PH0, /* pin 56 */
+ GPIO_PH1,
+ GPIO_PH2,
+ GPIO_PH3,
+ GPIO_PH4,
+ GPIO_PH5,
+ GPIO_PH6,
+ GPIO_PH7,
+ GPIO_PI0, /* pin 64 */
+ GPIO_PI1,
+ GPIO_PI2,
+ GPIO_PI3,
+ GPIO_PI4,
+ GPIO_PI5,
+ GPIO_PI6,
+ GPIO_PI7,
+ GPIO_PJ0, /* pin 72 */
+ GPIO_PJ1,
+ GPIO_PJ2,
+ GPIO_PJ3,
+ GPIO_PJ4,
+ GPIO_PJ5,
+ GPIO_PJ6,
+ GPIO_PJ7,
+ GPIO_PK0, /* pin 80 */
+ GPIO_PK1,
+ GPIO_PK2,
+ GPIO_PK3,
+ GPIO_PK4,
+ GPIO_PK5,
+ GPIO_PK6,
+ GPIO_PK7,
+ GPIO_PL0, /* pin 88 */
+ GPIO_PL1,
+ GPIO_PL2,
+ GPIO_PL3,
+ GPIO_PL4,
+ GPIO_PL5,
+ GPIO_PL6,
+ GPIO_PL7,
+ GPIO_PM0, /* pin 96 */
+ GPIO_PM1,
+ GPIO_PM2,
+ GPIO_PM3,
+ GPIO_PM4,
+ GPIO_PM5,
+ GPIO_PM6,
+ GPIO_PM7,
+ GPIO_PN0, /* pin 104 */
+ GPIO_PN1,
+ GPIO_PN2,
+ GPIO_PN3,
+ GPIO_PN4,
+ GPIO_PN5,
+ GPIO_PN6,
+ GPIO_PN7,
+ GPIO_PO0, /* pin 112 */
+ GPIO_PO1,
+ GPIO_PO2,
+ GPIO_PO3,
+ GPIO_PO4,
+ GPIO_PO5,
+ GPIO_PO6,
+ GPIO_PO7,
+ GPIO_PP0, /* pin 120 */
+ GPIO_PP1,
+ GPIO_PP2,
+ GPIO_PP3,
+ GPIO_PP4,
+ GPIO_PP5,
+ GPIO_PP6,
+ GPIO_PP7,
+ GPIO_PQ0, /* pin 128 */
+ GPIO_PQ1,
+ GPIO_PQ2,
+ GPIO_PQ3,
+ GPIO_PQ4,
+ GPIO_PQ5,
+ GPIO_PQ6,
+ GPIO_PQ7,
+ GPIO_PR0, /* pin 136 */
+ GPIO_PR1,
+ GPIO_PR2,
+ GPIO_PR3,
+ GPIO_PR4,
+ GPIO_PR5,
+ GPIO_PR6,
+ GPIO_PR7,
+ GPIO_PS0, /* pin 144 */
+ GPIO_PS1,
+ GPIO_PS2,
+ GPIO_PS3,
+ GPIO_PS4,
+ GPIO_PS5,
+ GPIO_PS6,
+ GPIO_PS7,
+ GPIO_PT0, /* pin 152 */
+ GPIO_PT1,
+ GPIO_PT2,
+ GPIO_PT3,
+ GPIO_PT4,
+ GPIO_PT5,
+ GPIO_PT6,
+ GPIO_PT7,
+ GPIO_PU0, /* pin 160 */
+ GPIO_PU1,
+ GPIO_PU2,
+ GPIO_PU3,
+ GPIO_PU4,
+ GPIO_PU5,
+ GPIO_PU6,
+ GPIO_PU7,
+ GPIO_PV0, /* pin 168 */
+ GPIO_PV1,
+ GPIO_PV2,
+ GPIO_PV3,
+ GPIO_PV4,
+ GPIO_PV5,
+ GPIO_PV6,
+ GPIO_PV7,
+ GPIO_PW0, /* pin 176 */
+ GPIO_PW1,
+ GPIO_PW2,
+ GPIO_PW3,
+ GPIO_PW4,
+ GPIO_PW5,
+ GPIO_PW6,
+ GPIO_PW7,
+ GPIO_PX0, /* pin 184 */
+ GPIO_PX1,
+ GPIO_PX2,
+ GPIO_PX3,
+ GPIO_PX4,
+ GPIO_PX5,
+ GPIO_PX6,
+ GPIO_PX7,
+ GPIO_PY0, /* pin 192 */
+ GPIO_PY1,
+ GPIO_PY2,
+ GPIO_PY3,
+ GPIO_PY4,
+ GPIO_PY5,
+ GPIO_PY6,
+ GPIO_PY7,
+ GPIO_PZ0, /* pin 200 */
+ GPIO_PZ1,
+ GPIO_PZ2,
+ GPIO_PZ3,
+ GPIO_PZ4,
+ GPIO_PZ5,
+ GPIO_PZ6,
+ GPIO_PZ7,
+ GPIO_PAA0, /* pin 208 */
+ GPIO_PAA1,
+ GPIO_PAA2,
+ GPIO_PAA3,
+ GPIO_PAA4,
+ GPIO_PAA5,
+ GPIO_PAA6,
+ GPIO_PAA7,
+ GPIO_PBB0, /* pin 216 */
+ GPIO_PBB1,
+ GPIO_PBB2,
+ GPIO_PBB3,
+ GPIO_PBB4,
+ GPIO_PBB5,
+ GPIO_PBB6,
+ GPIO_PBB7,
+ GPIO_PCC0, /* pin 224 */
+ GPIO_PCC1,
+ GPIO_PCC2,
+ GPIO_PCC3,
+ GPIO_PCC4,
+ GPIO_PCC5,
+ GPIO_PCC6,
+ GPIO_PCC7,
+ GPIO_PDD0, /* pin 232 */
+ GPIO_PDD1,
+ GPIO_PDD2,
+ GPIO_PDD3,
+ GPIO_PDD4,
+ GPIO_PDD5,
+ GPIO_PDD6,
+ GPIO_PDD7,
+ GPIO_PEE0, /* pin 240 */
+ GPIO_PEE1,
+ GPIO_PEE2,
+ GPIO_PEE3,
+ GPIO_PEE4,
+ GPIO_PEE5,
+ GPIO_PEE6,
+ GPIO_PEE7,
+ GPIO_PFF0, /* pin 248 */
+ GPIO_PFF1,
+ GPIO_PFF2,
+ GPIO_PFF3,
+ GPIO_PFF4,
+ GPIO_PFF5,
+ GPIO_PFF6,
+ GPIO_PFF7, /* pin 255 */
+};
+
+#endif /* _TEGRA124_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/hardware.h b/arch/arm/include/asm/arch-tegra124/hardware.h
new file mode 100644
index 0000000..114fce8
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/hardware.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA124_HARDWARE_H_
+#define _TEGRA124_HARDWARE_H_
+
+/*
+ * Include Tegra-specific hardware definitions
+ * Nothing needed currently for Tegra124
+ */
+
+#endif /* _TEGRA124_HARDWARE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h
new file mode 100644
index 0000000..9662e2b
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/pinmux.h
@@ -0,0 +1,620 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA124_PINMUX_H_
+#define _TEGRA124_PINMUX_H_
+
+/*
+ * Pin groups which we adjust. There are three basic attributes of each pin
+ * group which use this enum:
+ *
+ * - function
+ * - pullup / pulldown
+ * - tristate or normal
+ */
+enum pmux_pingrp {
+ PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
+ PINGRP_ULPI_DATA1,
+ PINGRP_ULPI_DATA2,
+ PINGRP_ULPI_DATA3,
+ PINGRP_ULPI_DATA4,
+ PINGRP_ULPI_DATA5,
+ PINGRP_ULPI_DATA6,
+ PINGRP_ULPI_DATA7,
+ PINGRP_ULPI_CLK,
+ PINGRP_ULPI_DIR,
+ PINGRP_ULPI_NXT,
+ PINGRP_ULPI_STP,
+ PINGRP_DAP3_FS,
+ PINGRP_DAP3_DIN,
+ PINGRP_DAP3_DOUT,
+ PINGRP_DAP3_SCLK,
+ PINGRP_GPIO_PV0,
+ PINGRP_GPIO_PV1,
+ PINGRP_SDMMC1_CLK,
+ PINGRP_SDMMC1_CMD,
+ PINGRP_SDMMC1_DAT3,
+ PINGRP_SDMMC1_DAT2,
+ PINGRP_SDMMC1_DAT1,
+ PINGRP_SDMMC1_DAT0,
+ PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
+ PINGRP_CLK2_REQ,
+ PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
+ PINGRP_DDC_SCL,
+ PINGRP_DDC_SDA,
+ PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
+ PINGRP_UART2_TXD,
+ PINGRP_UART2_RTS_N,
+ PINGRP_UART2_CTS_N,
+ PINGRP_UART3_TXD,
+ PINGRP_UART3_RXD,
+ PINGRP_UART3_CTS_N,
+ PINGRP_UART3_RTS_N,
+ PINGRP_GPIO_PU0,
+ PINGRP_GPIO_PU1,
+ PINGRP_GPIO_PU2,
+ PINGRP_GPIO_PU3,
+ PINGRP_GPIO_PU4,
+ PINGRP_GPIO_PU5,
+ PINGRP_GPIO_PU6,
+ PINGRP_GEN1_I2C_SDA,
+ PINGRP_GEN1_I2C_SCL,
+ PINGRP_DAP4_FS,
+ PINGRP_DAP4_DIN,
+ PINGRP_DAP4_DOUT,
+ PINGRP_DAP4_SCLK,
+ PINGRP_CLK3_OUT,
+ PINGRP_CLK3_REQ,
+ /* Renamed on Tegra124, from GMI_xx to GPIO_Pxx */
+ PINGRP_GPIO_PC7, /* offset 0x31c0 */
+ PINGRP_GPIO_PI5,
+ PINGRP_GPIO_PI7,
+ PINGRP_GPIO_PK0,
+ PINGRP_GPIO_PK1,
+ PINGRP_GPIO_PJ0,
+ PINGRP_GPIO_PJ2,
+ PINGRP_GPIO_PK3,
+ PINGRP_GPIO_PK4,
+ PINGRP_GPIO_PK2,
+ PINGRP_GPIO_PI3,
+ PINGRP_GPIO_PI6,
+ PINGRP_GPIO_PG0,
+ PINGRP_GPIO_PG1,
+ PINGRP_GPIO_PG2,
+ PINGRP_GPIO_PG3,
+ PINGRP_GPIO_PG4,
+ PINGRP_GPIO_PG5,
+ PINGRP_GPIO_PG6,
+ PINGRP_GPIO_PG7,
+ PINGRP_GPIO_PH0,
+ PINGRP_GPIO_PH1,
+ PINGRP_GPIO_PH2,
+ PINGRP_GPIO_PH3,
+ PINGRP_GPIO_PH4,
+ PINGRP_GPIO_PH5,
+ PINGRP_GPIO_PH6,
+ PINGRP_GPIO_PH7,
+ PINGRP_GPIO_PJ7,
+ PINGRP_GPIO_PB0,
+ PINGRP_GPIO_PB1,
+ PINGRP_GPIO_PK7,
+ PINGRP_GPIO_PI0,
+ PINGRP_GPIO_PI1,
+ PINGRP_GPIO_PI2,
+ PINGRP_GPIO_PI4, /* offset 0x324c */
+ PINGRP_GEN2_I2C_SCL,
+ PINGRP_GEN2_I2C_SDA,
+ PINGRP_SDMMC4_CLK,
+ PINGRP_SDMMC4_CMD,
+ PINGRP_SDMMC4_DAT0,
+ PINGRP_SDMMC4_DAT1,
+ PINGRP_SDMMC4_DAT2,
+ PINGRP_SDMMC4_DAT3,
+ PINGRP_SDMMC4_DAT4,
+ PINGRP_SDMMC4_DAT5,
+ PINGRP_SDMMC4_DAT6,
+ PINGRP_SDMMC4_DAT7,
+ PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
+ PINGRP_GPIO_PCC1,
+ PINGRP_GPIO_PBB0,
+ PINGRP_CAM_I2C_SCL,
+ PINGRP_CAM_I2C_SDA,
+ PINGRP_GPIO_PBB3,
+ PINGRP_GPIO_PBB4,
+ PINGRP_GPIO_PBB5,
+ PINGRP_GPIO_PBB6,
+ PINGRP_GPIO_PBB7,
+ PINGRP_GPIO_PCC2,
+ PINGRP_JTAG_RTCK,
+ PINGRP_PWR_I2C_SCL,
+ PINGRP_PWR_I2C_SDA,
+ PINGRP_KB_ROW0,
+ PINGRP_KB_ROW1,
+ PINGRP_KB_ROW2,
+ PINGRP_KB_ROW3,
+ PINGRP_KB_ROW4,
+ PINGRP_KB_ROW5,
+ PINGRP_KB_ROW6,
+ PINGRP_KB_ROW7,
+ PINGRP_KB_ROW8,
+ PINGRP_KB_ROW9,
+ PINGRP_KB_ROW10,
+ PINGRP_KB_ROW11,
+ PINGRP_KB_ROW12,
+ PINGRP_KB_ROW13,
+ PINGRP_KB_ROW14,
+ PINGRP_KB_ROW15,
+ PINGRP_KB_COL0, /* offset 0x32fc */
+ PINGRP_KB_COL1,
+ PINGRP_KB_COL2,
+ PINGRP_KB_COL3,
+ PINGRP_KB_COL4,
+ PINGRP_KB_COL5,
+ PINGRP_KB_COL6,
+ PINGRP_KB_COL7,
+ PINGRP_CLK_32K_OUT,
+ PINGRP_CORE_PWR_REQ = PINGRP_CLK_32K_OUT + 2, /* offset 0x3324 */
+ PINGRP_CPU_PWR_REQ,
+ PINGRP_PWR_INT_N,
+ PINGRP_CLK_32K_IN,
+ PINGRP_OWR,
+ PINGRP_DAP1_FS,
+ PINGRP_DAP1_DIN,
+ PINGRP_DAP1_DOUT,
+ PINGRP_DAP1_SCLK,
+ PINGRP_CLK1_REQ,
+ PINGRP_CLK1_OUT,
+ PINGRP_SPDIF_IN,
+ PINGRP_SPDIF_OUT,
+ PINGRP_DAP2_FS,
+ PINGRP_DAP2_DIN,
+ PINGRP_DAP2_DOUT,
+ PINGRP_DAP2_SCLK,
+ PINGRP_DVFS_PWM,
+ PINGRP_GPIO_X1_AUD,
+ PINGRP_GPIO_X3_AUD,
+ PINGRP_DVFS_CLK,
+ PINGRP_GPIO_X4_AUD,
+ PINGRP_GPIO_X5_AUD,
+ PINGRP_GPIO_X6_AUD,
+ PINGRP_GPIO_X7_AUD,
+ PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
+ PINGRP_SDMMC3_CMD,
+ PINGRP_SDMMC3_DAT0,
+ PINGRP_SDMMC3_DAT1,
+ PINGRP_SDMMC3_DAT2,
+ PINGRP_SDMMC3_DAT3,
+ PINGRP_PEX_L0_RST = PINGRP_SDMMC3_DAT3 + 6, /* offset 0x33bc */
+ PINGRP_PEX_L0_CLKREQ,
+ PINGRP_PEX_WAKE,
+ PINGRP_PEX_L1_RST = PINGRP_PEX_WAKE + 2,
+ PINGRP_PEX_L1_CLKREQ,
+ PINGRP_HDMI_CEC = PINGRP_PEX_L1_CLKREQ + 4, /* offset 0x33e0 */
+ PINGRP_SDMMC1_WP_N,
+ PINGRP_SDMMC3_CD_N,
+ PINGRP_GPIO_W2_AUD,
+ PINGRP_GPIO_W3_AUD,
+ PINGRP_USB_VBUS_EN0,
+ PINGRP_USB_VBUS_EN1,
+ PINGRP_SDMMC3_CLK_LB_IN,
+ PINGRP_SDMMC3_CLK_LB_OUT,
+ PINGRP_GMI_CLK_LB,
+ PINGRP_RESET_OUT_N,
+ PINGRP_KB_ROW16, /* offset 0x340c */
+ PINGRP_KB_ROW17,
+ PINGRP_USB_VBUS_EN2,
+ PINGRP_GPIO_PFF2,
+ PINGRP_DP_HPD, /* last reg offset = 0x3430 */
+ PINGRP_COUNT,
+};
+
+enum pdrive_pingrp {
+ PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
+ PDRIVE_PINGROUP_AO2,
+ PDRIVE_PINGROUP_AT1,
+ PDRIVE_PINGROUP_AT2,
+ PDRIVE_PINGROUP_AT3,
+ PDRIVE_PINGROUP_AT4,
+ PDRIVE_PINGROUP_AT5,
+ PDRIVE_PINGROUP_CDEV1,
+ PDRIVE_PINGROUP_CDEV2,
+ PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */
+ PDRIVE_PINGROUP_DAP2,
+ PDRIVE_PINGROUP_DAP3,
+ PDRIVE_PINGROUP_DAP4,
+ PDRIVE_PINGROUP_DBG,
+ PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */
+ PDRIVE_PINGROUP_SPI,
+ PDRIVE_PINGROUP_UAA,
+ PDRIVE_PINGROUP_UAB,
+ PDRIVE_PINGROUP_UART2,
+ PDRIVE_PINGROUP_UART3,
+ PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */
+ PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */
+ PDRIVE_PINGROUP_GMA,
+ PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */
+ PDRIVE_PINGROUP_GMF,
+ PDRIVE_PINGROUP_GMG,
+ PDRIVE_PINGROUP_GMH,
+ PDRIVE_PINGROUP_OWR,
+ PDRIVE_PINGROUP_UAD,
+ PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
+ PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
+ PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */
+ PDRIVE_PINGROUP_DAP5,
+ PDRIVE_PINGROUP_VBUS,
+ PDRIVE_PINGROUP_AO3,
+ PDRIVE_PINGROUP_HVC,
+ PDRIVE_PINGROUP_SDIO4,
+ PDRIVE_PINGROUP_AO0,
+ PDRIVE_PINGROUP_COUNT,
+};
+
+/*
+ * Functions which can be assigned to each of the pin groups. The values here
+ * bear no relation to the values programmed into pinmux registers and are
+ * purely a convenience. The translation is done through a table search.
+ */
+enum pmux_func {
+ PMUX_FUNC_AHB_CLK,
+ PMUX_FUNC_APB_CLK,
+ PMUX_FUNC_AUDIO_SYNC,
+ PMUX_FUNC_CRT,
+ PMUX_FUNC_DAP1,
+ PMUX_FUNC_DAP2,
+ PMUX_FUNC_DAP3,
+ PMUX_FUNC_DAP4,
+ PMUX_FUNC_DAP5,
+ PMUX_FUNC_DISPA,
+ PMUX_FUNC_DISPB,
+ PMUX_FUNC_EMC_TEST0_DLL,
+ PMUX_FUNC_EMC_TEST1_DLL,
+ PMUX_FUNC_GMI,
+ PMUX_FUNC_GMI_INT,
+ PMUX_FUNC_HDMI,
+ PMUX_FUNC_I2C1,
+ PMUX_FUNC_I2C2,
+ PMUX_FUNC_I2C3,
+ PMUX_FUNC_IDE,
+ PMUX_FUNC_KBC,
+ PMUX_FUNC_MIO,
+ PMUX_FUNC_MIPI_HS,
+ PMUX_FUNC_NAND,
+ PMUX_FUNC_OSC,
+ PMUX_FUNC_OWR,
+ PMUX_FUNC_PCIE,
+ PMUX_FUNC_PLLA_OUT,
+ PMUX_FUNC_PLLC_OUT1,
+ PMUX_FUNC_PLLM_OUT1,
+ PMUX_FUNC_PLLP_OUT2,
+ PMUX_FUNC_PLLP_OUT3,
+ PMUX_FUNC_PLLP_OUT4,
+ PMUX_FUNC_PWM,
+ PMUX_FUNC_PWR_INTR,
+ PMUX_FUNC_PWR_ON,
+ PMUX_FUNC_RTCK,
+ PMUX_FUNC_SDMMC1,
+ PMUX_FUNC_SDMMC2,
+ PMUX_FUNC_SDMMC3,
+ PMUX_FUNC_SDMMC4,
+ PMUX_FUNC_SFLASH,
+ PMUX_FUNC_SPDIF,
+ PMUX_FUNC_SPI1,
+ PMUX_FUNC_SPI2,
+ PMUX_FUNC_SPI2_ALT,
+ PMUX_FUNC_SPI3,
+ PMUX_FUNC_SPI4,
+ PMUX_FUNC_TRACE,
+ PMUX_FUNC_TWC,
+ PMUX_FUNC_UARTA,
+ PMUX_FUNC_UARTB,
+ PMUX_FUNC_UARTC,
+ PMUX_FUNC_UARTD,
+ PMUX_FUNC_UARTE,
+ PMUX_FUNC_ULPI,
+ PMUX_FUNC_VI,
+ PMUX_FUNC_VI_SENSOR_CLK,
+ PMUX_FUNC_XIO,
+ /* End of Tegra2 MUX selectors */
+ PMUX_FUNC_BLINK,
+ PMUX_FUNC_CEC,
+ PMUX_FUNC_CLK12,
+ PMUX_FUNC_DAP,
+ PMUX_FUNC_DAPSDMMC2,
+ PMUX_FUNC_DDR,
+ PMUX_FUNC_DEV3,
+ PMUX_FUNC_DTV,
+ PMUX_FUNC_VI_ALT1,
+ PMUX_FUNC_VI_ALT2,
+ PMUX_FUNC_VI_ALT3,
+ PMUX_FUNC_EMC_DLL,
+ PMUX_FUNC_EXTPERIPH1,
+ PMUX_FUNC_EXTPERIPH2,
+ PMUX_FUNC_EXTPERIPH3,
+ PMUX_FUNC_GMI_ALT,
+ PMUX_FUNC_HDA,
+ PMUX_FUNC_HSI,
+ PMUX_FUNC_I2C4,
+ PMUX_FUNC_I2C5,
+ PMUX_FUNC_I2CPWR,
+ PMUX_FUNC_I2S0,
+ PMUX_FUNC_I2S1,
+ PMUX_FUNC_I2S2,
+ PMUX_FUNC_I2S3,
+ PMUX_FUNC_I2S4,
+ PMUX_FUNC_NAND_ALT,
+ PMUX_FUNC_POPSDIO4,
+ PMUX_FUNC_POPSDMMC4,
+ PMUX_FUNC_PWM0,
+ PMUX_FUNC_PWM1,
+ PMUX_FUNC_PWM2,
+ PMUX_FUNC_PWM3,
+ PMUX_FUNC_SATA,
+ PMUX_FUNC_SPI5,
+ PMUX_FUNC_SPI6,
+ PMUX_FUNC_SYSCLK,
+ PMUX_FUNC_VGP1,
+ PMUX_FUNC_VGP2,
+ PMUX_FUNC_VGP3,
+ PMUX_FUNC_VGP4,
+ PMUX_FUNC_VGP5,
+ PMUX_FUNC_VGP6,
+ /* End of Tegra3 MUX selectors */
+ PMUX_FUNC_USB,
+ PMUX_FUNC_SOC,
+ PMUX_FUNC_CPU,
+ PMUX_FUNC_CLK,
+ PMUX_FUNC_PWRON,
+ PMUX_FUNC_PMI,
+ PMUX_FUNC_CLDVFS,
+ PMUX_FUNC_RESET_OUT_N,
+ /* End of Tegra114 MUX selectors */
+
+ PMUX_FUNC_SAFE,
+ PMUX_FUNC_MAX,
+
+ PMUX_FUNC_INVALID = 0x4000,
+ PMUX_FUNC_RSVD1 = 0x8000,
+ PMUX_FUNC_RSVD2 = 0x8001,
+ PMUX_FUNC_RSVD3 = 0x8002,
+ PMUX_FUNC_RSVD4 = 0x8003,
+};
+
+/* return 1 if a pmux_func is in range */
+#define pmux_func_isvalid(func) \
+ ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) || \
+ (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
+
+/* return 1 if a pingrp is in range */
+#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
+
+/* The pullup/pulldown state of a pin group */
+enum pmux_pull {
+ PMUX_PULL_NORMAL = 0,
+ PMUX_PULL_DOWN,
+ PMUX_PULL_UP,
+};
+/* return 1 if a pin_pupd_is in range */
+#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
+ ((pupd) <= PMUX_PULL_UP))
+
+/* Defines whether a pin group is tristated or in normal operation */
+enum pmux_tristate {
+ PMUX_TRI_NORMAL = 0,
+ PMUX_TRI_TRISTATE = 1,
+};
+/* return 1 if a pin_tristate_is in range */
+#define pmux_pin_tristate_isvalid(tristate) \
+ (((tristate) >= PMUX_TRI_NORMAL) && \
+ ((tristate) <= PMUX_TRI_TRISTATE))
+
+enum pmux_pin_io {
+ PMUX_PIN_OUTPUT = 0,
+ PMUX_PIN_INPUT = 1,
+ PMUX_PIN_NONE,
+};
+/* return 1 if a pin_io_is in range */
+#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
+ ((io) <= PMUX_PIN_INPUT))
+
+enum pmux_pin_lock {
+ PMUX_PIN_LOCK_DEFAULT = 0,
+ PMUX_PIN_LOCK_DISABLE,
+ PMUX_PIN_LOCK_ENABLE,
+};
+/* return 1 if a pin_lock is in range */
+#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
+ ((lock) <= PMUX_PIN_LOCK_ENABLE))
+
+enum pmux_pin_od {
+ PMUX_PIN_OD_DEFAULT = 0,
+ PMUX_PIN_OD_DISABLE,
+ PMUX_PIN_OD_ENABLE,
+};
+/* return 1 if a pin_od is in range */
+#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
+ ((od) <= PMUX_PIN_OD_ENABLE))
+
+enum pmux_pin_ioreset {
+ PMUX_PIN_IO_RESET_DEFAULT = 0,
+ PMUX_PIN_IO_RESET_DISABLE,
+ PMUX_PIN_IO_RESET_ENABLE,
+};
+/* return 1 if a pin_ioreset_is in range */
+#define pmux_pin_ioreset_isvalid(ioreset) \
+ (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
+ ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
+
+enum pmux_pin_rcv_sel {
+ PMUX_PIN_RCV_SEL_DEFAULT = 0,
+ PMUX_PIN_RCV_SEL_NORMAL,
+ PMUX_PIN_RCV_SEL_HIGH,
+};
+/* return 1 if a pin_rcv_sel_is in range */
+#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
+ (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
+ ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
+
+/* Available power domains used by pin groups */
+enum pmux_vddio {
+ PMUX_VDDIO_BB = 0,
+ PMUX_VDDIO_LCD,
+ PMUX_VDDIO_VI,
+ PMUX_VDDIO_UART,
+ PMUX_VDDIO_DDR,
+ PMUX_VDDIO_NAND,
+ PMUX_VDDIO_SYS,
+ PMUX_VDDIO_AUDIO,
+ PMUX_VDDIO_SD,
+ PMUX_VDDIO_CAM,
+ PMUX_VDDIO_GMI,
+ PMUX_VDDIO_PEXCTL,
+ PMUX_VDDIO_SDMMC1,
+ PMUX_VDDIO_SDMMC3,
+ PMUX_VDDIO_SDMMC4,
+
+ PMUX_VDDIO_NONE
+};
+
+#define PGRP_SLWF_NONE -1
+#define PGRP_SLWF_MAX 3
+#define PGRP_SLWR_NONE PGRP_SLWF_NONE
+#define PGRP_SLWR_MAX PGRP_SLWF_MAX
+
+#define PGRP_DRVUP_NONE -1
+#define PGRP_DRVUP_MAX 127
+#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE
+#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
+
+#define PGRP_SCHMT_NONE -1
+#define PGRP_HSM_NONE PGRP_SCHMT_NONE
+
+/* return 1 if a padgrp is in range */
+#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
+
+/* return 1 if a slew-rate rising/falling edge value is in range */
+#define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \
+ (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)))
+
+/* return 1 if a driver output pull-up/down strength code value is in range */
+#define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \
+ (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)))
+
+/* return 1 if a low-power mode value is in range */
+#define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \
+ (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)))
+
+/* Defines a pin group cfg's low-power mode select */
+enum pgrp_lpmd {
+ PGRP_LPMD_X8 = 0,
+ PGRP_LPMD_X4,
+ PGRP_LPMD_X2,
+ PGRP_LPMD_X,
+ PGRP_LPMD_NONE = -1,
+};
+
+/* Defines whether a pin group cfg's schmidt is enabled or not */
+enum pgrp_schmt {
+ PGRP_SCHMT_DISABLE = 0,
+ PGRP_SCHMT_ENABLE = 1,
+};
+
+/* Defines whether a pin group cfg's high-speed mode is enabled or not */
+enum pgrp_hsm {
+ PGRP_HSM_DISABLE = 0,
+ PGRP_HSM_ENABLE = 1,
+};
+
+/*
+ * This defines the configuration for a pin group's pad control config
+ */
+struct padctrl_config {
+ enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */
+ int slwf; /* falling edge slew */
+ int slwr; /* rising edge slew */
+ int drvup; /* pull-up drive strength */
+ int drvdn; /* pull-down drive strength */
+ enum pgrp_lpmd lpmd; /* low-power mode selection */
+ enum pgrp_schmt schmt; /* schmidt enable */
+ enum pgrp_hsm hsm; /* high-speed mode enable */
+};
+
+/* Tegra124 pin drive group and pin mux registers */
+#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
+#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
+ PDRIVE_PINGROUP_COUNT)
+struct pmux_tri_ctlr {
+ uint pmt_reserved0[9]; /* ABP_MISC_PP_ offsets 00-20 */
+ uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
+
+ uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */
+
+ uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */
+ uint pmt_reserved5[PMUX_OFFSET];
+ uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */
+};
+
+/*
+ * This defines the configuration for a pin, including the function assigned,
+ * pull up/down settings and tristate settings. Having set up one of these
+ * you can call pinmux_config_pingroup() to configure a pin in one step. Also
+ * available is pinmux_config_table() to configure a list of pins.
+ */
+struct pingroup_config {
+ enum pmux_pingrp pingroup; /* pin group PINGRP_... */
+ enum pmux_func func; /* function to assign FUNC_... */
+ enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
+ enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
+ enum pmux_pin_io io; /* input or output PMUX_PIN_... */
+ enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
+ enum pmux_pin_od od; /* open-drain or push-pull driver */
+ enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
+ enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */
+ /* VIL/VIH receivers */
+};
+
+/* Set a pin group to tristate */
+void pinmux_tristate_enable(enum pmux_pingrp pin);
+
+/* Set a pin group to normal (non tristate) */
+void pinmux_tristate_disable(enum pmux_pingrp pin);
+
+/* Set the pull up/down feature for a pin group */
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
+
+/* Set the mux function for a pin group */
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
+
+/* Set the complete configuration for a pin group */
+void pinmux_config_pingroup(struct pingroup_config *config);
+
+/* Set a pin group to tristate or normal */
+void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
+
+/* Set a pin group as input or output */
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
+
+/**
+ * Configure a list of pin groups
+ *
+ * @param config List of config items
+ * @param len Number of config items in list
+ */
+void pinmux_config_table(struct pingroup_config *config, int len);
+
+/* Set a group of pins from a table */
+void pinmux_init(void);
+
+/**
+ * Set the GP pad configs
+ *
+ * @param config List of config items
+ * @param len Number of config items in list
+ */
+void padgrp_config_table(struct padctrl_config *config, int len);
+
+#endif /* _TEGRA124_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/pmu.h b/arch/arm/include/asm/arch-tegra124/pmu.h
new file mode 100644
index 0000000..b10100a
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/pmu.h
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA124_PMU_H_
+#define _TEGRA124_PMU_H_
+
+/* Set core and CPU voltages to nominal levels */
+int pmu_set_nominal(void);
+
+#endif /* _TEGRA124_PMU_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/spl.h b/arch/arm/include/asm/arch-tegra124/spl.h
new file mode 100644
index 0000000..e266395
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/spl.h
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_SPL_H_
+#define _ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_RAM 1
+
+#endif /* _ASM_ARCH_SPL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/sysctr.h b/arch/arm/include/asm/arch-tegra124/sysctr.h
new file mode 100644
index 0000000..3f0309b
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/sysctr.h
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA124_SYSCTR_H_
+#define _TEGRA124_SYSCTR_H_
+
+struct sysctr_ctlr {
+ u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */
+ u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */
+ u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */
+ u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */
+ u32 reserved1[4]; /* 0x10 - 0x1C */
+ u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */
+ u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */
+ u32 reserved2[1002]; /* 0x28 - 0xFCC */
+ u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */
+};
+
+#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */
+#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */
+
+#endif /* _TEGRA124_SYSCTR_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/tegra.h b/arch/arm/include/asm/arch-tegra124/tegra.h
new file mode 100644
index 0000000..db3d837
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/tegra.h
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA124_H_
+#define _TEGRA124_H_
+
+#define NV_PA_SDRAM_BASE 0x80000000
+#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
+#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */
+#define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */
+
+#include
+
+#define BCT_ODMDATA_OFFSET 1704 /* offset to ODMDATA word */
+
+#undef NVBOOTINFOTABLE_BCTSIZE
+#undef NVBOOTINFOTABLE_BCTPTR
+#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */
+#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */
+
+#define MAX_NUM_CPU 4
+#define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8)
+
+#define TEGRA_USB1_BASE 0x7D000000
+
+#endif /* _TEGRA124_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/usb.h b/arch/arm/include/asm/arch-tegra124/usb.h
new file mode 100644
index 0000000..7a2d785
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/usb.h
@@ -0,0 +1,268 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA124_USB_H_
+#define _TEGRA124_USB_H_
+
+
+/* USB Controller (USBx_CONTROLLER_) regs */
+struct usb_ctlr {
+ /* 0x000 */
+ uint id;
+ uint reserved0;
+ uint host;
+ uint device;
+
+ /* 0x010 */
+ uint txbuf;
+ uint rxbuf;
+ uint reserved1[2];
+
+ /* 0x020 */
+ uint reserved2[56];
+
+ /* 0x100 */
+ u16 cap_length;
+ u16 hci_version;
+ uint hcs_params;
+ uint hcc_params;
+ uint reserved3[5];
+
+ /* 0x120 */
+ uint dci_version;
+ uint dcc_params;
+ uint reserved4[2];
+
+ /* 0x130 */
+ uint usb_cmd;
+ uint usb_sts;
+ uint usb_intr;
+ uint frindex;
+
+ /* 0x140 */
+ uint reserved5;
+ uint periodic_list_base;
+ uint async_list_addr;
+ uint reserved5_1;
+
+ /* 0x150 */
+ uint burst_size;
+ uint tx_fill_tuning;
+ uint reserved6;
+ uint icusb_ctrl;
+
+ /* 0x160 */
+ uint ulpi_viewport;
+ uint reserved7;
+ uint reserved7_0;
+ uint reserved7_1;
+
+ /* 0x170 */
+ uint reserved;
+ uint port_sc1;
+ uint reserved8[6];
+
+ /* 0x190 */
+ uint reserved9[8];
+
+ /* 0x1b0 */
+ uint reserved10;
+ uint hostpc1_devlc;
+ uint reserved10_1[2];
+
+ /* 0x1c0 */
+ uint reserved10_2[4];
+
+ /* 0x1d0 */
+ uint reserved10_3[4];
+
+ /* 0x1e0 */
+ uint reserved10_4[4];
+
+ /* 0x1f0 */
+ uint reserved10_5;
+ uint otgsc;
+ uint usb_mode;
+ uint reserved10_6;
+
+ /* 0x200 */
+ uint endpt_nak;
+ uint endpt_nak_enable;
+ uint endpt_setup_stat;
+ uint reserved11_1[0x7D];
+
+ /* 0x400 */
+ uint susp_ctrl;
+ uint phy_vbus_sensors;
+ uint phy_vbus_wakeup_id;
+ uint phy_alt_vbus_sys;
+
+ /* 0x410 */
+ uint usb1_legacy_ctrl;
+ uint reserved12[3];
+
+ /* 0x420 */
+ uint reserved13[56];
+
+ /* 0x500 */
+ uint reserved14[64 * 3];
+
+ /* 0x800 */
+ uint utmip_pll_cfg0;
+ uint utmip_pll_cfg1;
+ uint utmip_xcvr_cfg0;
+ uint utmip_bias_cfg0;
+
+ /* 0x810 */
+ uint utmip_hsrx_cfg0;
+ uint utmip_hsrx_cfg1;
+ uint utmip_fslsrx_cfg0;
+ uint utmip_fslsrx_cfg1;
+
+ /* 0x820 */
+ uint utmip_tx_cfg0;
+ uint utmip_misc_cfg0;
+ uint utmip_misc_cfg1;
+ uint utmip_debounce_cfg0;
+
+ /* 0x830 */
+ uint utmip_bat_chrg_cfg0;
+ uint utmip_spare_cfg0;
+ uint utmip_xcvr_cfg1;
+ uint utmip_bias_cfg1;
+};
+
+/* USB1_LEGACY_CTRL */
+#define USB1_NO_LEGACY_MODE 1
+
+#define VBUS_SENSE_CTL_SHIFT 1
+#define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT)
+#define VBUS_SENSE_CTL_VBUS_WAKEUP 0
+#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1
+#define VBUS_SENSE_CTL_AB_SESS_VLD 2
+#define VBUS_SENSE_CTL_A_SESS_VLD 3
+
+/* USBx_IF_USB_SUSP_CTRL_0 */
+#define UTMIP_PHY_ENB (1 << 12)
+#define UTMIP_RESET (1 << 11)
+#define USB_PHY_CLK_VALID (1 << 7)
+#define USB_SUSP_CLR (1 << 5)
+
+/* USBx_UTMIP_MISC_CFG0 */
+#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
+
+/* USBx_UTMIP_MISC_CFG1 */
+#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30)
+
+/* Moved to Clock and Reset register space */
+#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6
+#define UTMIP_PLLU_STABLE_COUNT_MASK \
+ (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
+/* Moved to Clock and Reset register space */
+#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18
+#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \
+ (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
+
+/* USBx_UTMIP_PLL_CFG1_0 */
+/* Moved to Clock and Reset register space */
+#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27
+#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \
+ (0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
+#define UTMIP_XTAL_FREQ_COUNT_SHIFT 0
+#define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff
+
+/* USBx_UTMIP_BIAS_CFG0_0 */
+#define UTMIP_HSDISCON_LEVEL_MSB (1 << 24)
+#define UTMIP_OTGPD (1 << 11)
+#define UTMIP_BIASPD (1 << 10)
+#define UTMIP_HSDISCON_LEVEL_SHIFT 2
+#define UTMIP_HSDISCON_LEVEL_MASK \
+ (0x3 << UTMIP_HSDISCON_LEVEL_SHIFT)
+#define UTMIP_HSSQUELCH_LEVEL_SHIFT 0
+#define UTMIP_HSSQUELCH_LEVEL_MASK \
+ (0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT)
+
+/* USBx_UTMIP_BIAS_CFG1_0 */
+#define UTMIP_FORCE_PDTRK_POWERDOWN 1
+#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3
+#define UTMIP_BIAS_PDTRK_COUNT_MASK \
+ (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
+
+/* USBx_UTMIP_DEBOUNCE_CFG0_0 */
+#define UTMIP_DEBOUNCE_CFG0_SHIFT 0
+#define UTMIP_DEBOUNCE_CFG0_MASK 0xffff
+
+/* USBx_UTMIP_TX_CFG0_0 */
+#define UTMIP_FS_PREAMBLE_J (1 << 19)
+
+/* USBx_UTMIP_BAT_CHRG_CFG0_0 */
+#define UTMIP_PD_CHRG 1
+
+/* USBx_UTMIP_SPARE_CFG0_0 */
+#define FUSE_SETUP_SEL (1 << 3)
+
+/* USBx_UTMIP_HSRX_CFG0_0 */
+#define UTMIP_IDLE_WAIT_SHIFT 15
+#define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT)
+#define UTMIP_ELASTIC_LIMIT_SHIFT 10
+#define UTMIP_ELASTIC_LIMIT_MASK \
+ (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
+
+/* USBx_UTMIP_HSRX_CFG0_1 */
+#define UTMIP_HS_SYNC_START_DLY_SHIFT 1
+#define UTMIP_HS_SYNC_START_DLY_MASK \
+ (0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT)
+
+/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
+#define IC_ENB1 (1 << 3)
+
+/* PORTSC1, USB1, defined for Tegra20 to avoid compiling error */
+#define PTS1_SHIFT 31
+#define PTS1_MASK (1 << PTS1_SHIFT)
+#define STS1 (1 << 30)
+
+/* USB2D_HOSTPC1_DEVLC_0 */
+#define PTS_SHIFT 29
+#define PTS_MASK (0x7U << PTS_SHIFT)
+#define PTS_UTMI 0
+#define PTS_RESERVED 1
+#define PTS_ULPI 2
+#define PTS_ICUSB_SER 3
+#define PTS_HSIC 4
+
+#define STS (1 << 28)
+
+/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
+#define WKOC (1 << 22)
+#define WKDS (1 << 21)
+#define WKCN (1 << 20)
+
+/* USBx_UTMIP_XCVR_CFG0_0 */
+#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
+#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
+#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
+#define UTMIP_XCVR_LSBIAS_SE (1 << 21)
+#define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25
+#define UTMIP_XCVR_HSSLEW_MSB_MASK \
+ (0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
+#define UTMIP_XCVR_SETUP_MSB_SHIFT 22
+#define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
+#define UTMIP_XCVR_SETUP_SHIFT 0
+#define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT)
+
+/* USBx_UTMIP_XCVR_CFG1_0 */
+#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18
+#define UTMIP_XCVR_TERM_RANGE_ADJ_MASK \
+ (0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
+#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
+#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
+#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
+
+/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
+#define VBUS_VLD_STS (1 << 26)
+
+#endif /* _TEGRA124_USB_H_ */
--
cgit v1.1
From 32edd2ede2bd62d27c45bd9bdbc0b4a2848f4587 Mon Sep 17 00:00:00 2001
From: Tom Warren
Date: Fri, 24 Jan 2014 12:46:14 -0700
Subject: ARM: tegra: add SPL/AVP (arm720t) CPU files for Tegra124
This provides SPL support for Tegra124 boards - AVP early init, plus
CPU (A15) init/jump to main U-Boot.
Signed-off-by: Tom Warren
Signed-off-by: Stephen Warren
Tested-by: Thierry Reding
Signed-off-by: Tom Warren
---
arch/arm/cpu/arm720t/tegra-common/cpu.c | 36 ++++-
arch/arm/cpu/arm720t/tegra-common/cpu.h | 4 +-
arch/arm/cpu/arm720t/tegra124/Makefile | 8 +
arch/arm/cpu/arm720t/tegra124/config.mk | 7 +
arch/arm/cpu/arm720t/tegra124/cpu.c | 265 ++++++++++++++++++++++++++++++++
5 files changed, 318 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/cpu/arm720t/tegra124/Makefile
create mode 100644 arch/arm/cpu/arm720t/tegra124/config.mk
create mode 100644 arch/arm/cpu/arm720t/tegra124/cpu.c
(limited to 'arch/arm')
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c
index d62bb9e..2c5cd63 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
@@ -112,8 +112,40 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
},
+
+ /*
+ * T124: 700 MHz
+ *
+ * Register Field Bits Width
+ * ------------------------------
+ * PLLX_BASE p 23:20 4
+ * PLLX_BASE n 15: 8 8
+ * PLLX_BASE m 7: 0 8
+ */
+ {
+ { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
+ { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
+ { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
+ { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
+ },
};
+static inline void pllx_set_iddq(void)
+{
+#if defined(CONFIG_TEGRA124)
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ /* Disable IDDQ */
+ reg = readl(&clkrst->crc_pllx_misc3);
+ reg &= ~PLLX_IDDQ_MASK;
+ writel(reg, &clkrst->crc_pllx_misc3);
+ udelay(2);
+ debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__,
+ readl(&clkrst->crc_pllx_misc3));
+#endif
+}
+
int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
u32 divp, u32 cpcon)
{
@@ -128,6 +160,8 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
debug(" pllx_set_rate entry\n");
+ pllx_set_iddq();
+
/* Set BYPASS, m, n and p to PLLX_BASE */
reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
@@ -323,7 +357,7 @@ void clock_enable_coresight(int enable)
if (enable) {
/*
* Put CoreSight on PLLP_OUT0 and divide it down as per
- * PLLP base frequency based on SoC type (T20/T30/T114).
+ * PLLP base frequency based on SoC type (T20/T30+).
* Clock divider request would setup CSITE clock as 144MHz
* for PLLP base 216MHz and 204MHz for PLLP base 408MHz
*/
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.h b/arch/arm/cpu/arm720t/tegra-common/cpu.h
index d1520ce..b4ca44f 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.h
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.h
@@ -13,7 +13,8 @@
#if defined(CONFIG_TEGRA20)
#define NVBL_PLLP_KHZ 216000
#define CSITE_KHZ 144000
-#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
+#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \
+ defined(CONFIG_TEGRA124)
#define NVBL_PLLP_KHZ 408000
#define CSITE_KHZ 204000
#else
@@ -70,3 +71,4 @@ int tegra_get_chip(void);
int tegra_get_sku_info(void);
int tegra_get_chip_sku(void);
void adjust_pllp_out_freqs(void);
+void pmic_enable_cpu_vdd(void);
diff --git a/arch/arm/cpu/arm720t/tegra124/Makefile b/arch/arm/cpu/arm720t/tegra124/Makefile
new file mode 100644
index 0000000..61abf45
--- /dev/null
+++ b/arch/arm/cpu/arm720t/tegra124/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cpu.o
diff --git a/arch/arm/cpu/arm720t/tegra124/config.mk b/arch/arm/cpu/arm720t/tegra124/config.mk
new file mode 100644
index 0000000..5e10701
--- /dev/null
+++ b/arch/arm/cpu/arm720t/tegra124/config.mk
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2010-2013
+# NVIDIA Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#/
+USE_PRIVATE_LIBGCC = yes
diff --git a/arch/arm/cpu/arm720t/tegra124/cpu.c b/arch/arm/cpu/arm720t/tegra124/cpu.c
new file mode 100644
index 0000000..c03aaf1
--- /dev/null
+++ b/arch/arm/cpu/arm720t/tegra124/cpu.c
@@ -0,0 +1,265 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "../tegra-common/cpu.h"
+
+/* Tegra124-specific CPU init code */
+
+static void enable_cpu_power_rail(void)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+ debug("enable_cpu_power_rail entry\n");
+
+ /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
+ pinmux_tristate_disable(PINGRP_PWR_I2C_SCL);
+ pinmux_tristate_disable(PINGRP_PWR_I2C_SDA);
+
+ pmic_enable_cpu_vdd();
+
+ /*
+ * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
+ * set it for 5ms as per SysEng (102MHz*5ms = 510000 (7C830h).
+ */
+ writel(0x7C830, &pmc->pmc_cpupwrgood_timer);
+
+ /* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
+ clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
+ setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
+}
+
+static void enable_cpu_clocks(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ debug("enable_cpu_clocks entry\n");
+
+ /* Wait for PLL-X to lock */
+ do {
+ reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
+ debug("%s: PLLX base = 0x%08X\n", __func__, reg);
+ } while ((reg & PLL_LOCK_MASK) == 0);
+
+ debug("%s: PLLX locked, delay for stable clocks\n", __func__);
+ /* Wait until all clocks are stable */
+ udelay(PLL_STABILIZATION_DELAY);
+
+ debug("%s: Setting CCLK_BURST and DIVIDER\n", __func__);
+ writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
+ writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
+
+ debug("%s: Enabling clock to all CPUs\n", __func__);
+ /* Enable the clock to all CPUs */
+ reg = CLR_CPU3_CLK_STP | CLR_CPU2_CLK_STP | CLR_CPU1_CLK_STP |
+ CLR_CPU0_CLK_STP;
+ writel(reg, &clkrst->crc_clk_cpu_cmplx_clr);
+
+ debug("%s: Enabling main CPU complex clocks\n", __func__);
+ /* Always enable the main CPU complex clocks */
+ clock_enable(PERIPH_ID_CPU);
+ clock_enable(PERIPH_ID_CPULP);
+ clock_enable(PERIPH_ID_CPUG);
+
+ debug("%s: Done\n", __func__);
+}
+
+static void remove_cpu_resets(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ debug("remove_cpu_resets entry\n");
+
+ /* Take the slow and fast partitions out of reset */
+ reg = CLR_NONCPURESET;
+ writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
+ writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
+
+ /* Clear the SW-controlled reset of the slow cluster */
+ reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
+ CLR_L2RESET | CLR_PRESETDBG;
+ writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
+
+ /* Clear the SW-controlled reset of the fast cluster */
+ reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
+ CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 |
+ CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 |
+ CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3 |
+ CLR_L2RESET | CLR_PRESETDBG;
+ writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
+}
+
+/**
+ * The Tegra124 requires some special clock initialization, including setting up
+ * the DVC I2C, turning on MSELECT and selecting the G CPU cluster
+ */
+void tegra124_init_clocks(void)
+{
+ struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 val;
+
+ debug("tegra124_init_clocks entry\n");
+
+ /* Set active CPU cluster to G */
+ clrbits_le32(&flow->cluster_control, 1);
+
+ /* Change the oscillator drive strength */
+ val = readl(&clkrst->crc_osc_ctrl);
+ val &= ~OSC_XOFS_MASK;
+ val |= (OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT);
+ writel(val, &clkrst->crc_osc_ctrl);
+
+ /* Update same value in PMC_OSC_EDPD_OVER XOFS field for warmboot */
+ val = readl(&pmc->pmc_osc_edpd_over);
+ val &= ~PMC_XOFS_MASK;
+ val |= (OSC_DRIVE_STRENGTH << PMC_XOFS_SHIFT);
+ writel(val, &pmc->pmc_osc_edpd_over);
+
+ /* Set HOLD_CKE_LOW_EN to 1 */
+ setbits_le32(&pmc->pmc_cntrl2, HOLD_CKE_LOW_EN);
+
+ debug("Setting up PLLX\n");
+ init_pllx();
+
+ val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
+ writel(val, &clkrst->crc_clk_sys_rate);
+
+ /* Enable clocks to required peripherals. TBD - minimize this list */
+ debug("Enabling clocks\n");
+
+ clock_set_enable(PERIPH_ID_CACHE2, 1);
+ clock_set_enable(PERIPH_ID_GPIO, 1);
+ clock_set_enable(PERIPH_ID_TMR, 1);
+ clock_set_enable(PERIPH_ID_CPU, 1);
+ clock_set_enable(PERIPH_ID_EMC, 1);
+ clock_set_enable(PERIPH_ID_I2C5, 1);
+ clock_set_enable(PERIPH_ID_APBDMA, 1);
+ clock_set_enable(PERIPH_ID_MEM, 1);
+ clock_set_enable(PERIPH_ID_CORESIGHT, 1);
+ clock_set_enable(PERIPH_ID_MSELECT, 1);
+ clock_set_enable(PERIPH_ID_DVFS, 1);
+
+ /*
+ * Set MSELECT clock source as PLLP (00), and ask for a clock
+ * divider that would set the MSELECT clock at 102MHz for a
+ * PLLP base of 408MHz.
+ */
+ clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
+ CLK_DIVIDER(NVBL_PLLP_KHZ, 102000));
+
+ /* Give clock time to stabilize */
+ udelay(IO_STABILIZATION_DELAY);
+
+ /* I2C5 (DVC) gets CLK_M and a divisor of 17 */
+ clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);
+
+ /* Give clock time to stabilize */
+ udelay(IO_STABILIZATION_DELAY);
+
+ /* Take required peripherals out of reset */
+ debug("Taking periphs out of reset\n");
+ reset_set_enable(PERIPH_ID_CACHE2, 0);
+ reset_set_enable(PERIPH_ID_GPIO, 0);
+ reset_set_enable(PERIPH_ID_TMR, 0);
+ reset_set_enable(PERIPH_ID_COP, 0);
+ reset_set_enable(PERIPH_ID_EMC, 0);
+ reset_set_enable(PERIPH_ID_I2C5, 0);
+ reset_set_enable(PERIPH_ID_APBDMA, 0);
+ reset_set_enable(PERIPH_ID_MEM, 0);
+ reset_set_enable(PERIPH_ID_CORESIGHT, 0);
+ reset_set_enable(PERIPH_ID_MSELECT, 0);
+ reset_set_enable(PERIPH_ID_DVFS, 0);
+
+ debug("tegra124_init_clocks exit\n");
+}
+
+static bool is_partition_powered(u32 partid)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ u32 reg;
+
+ /* Get power gate status */
+ reg = readl(&pmc->pmc_pwrgate_status);
+ return !!(reg & (1 << partid));
+}
+
+static void power_partition(u32 partid)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+ debug("%s: part ID = %08X\n", __func__, partid);
+ /* Is the partition already on? */
+ if (!is_partition_powered(partid)) {
+ /* No, toggle the partition power state (OFF -> ON) */
+ debug("power_partition, toggling state\n");
+ writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
+
+ /* Wait for the power to come up */
+ while (!is_partition_powered(partid))
+ ;
+
+ /* Give I/O signals time to stabilize */
+ udelay(IO_STABILIZATION_DELAY);
+ }
+}
+
+void powerup_cpus(void)
+{
+ debug("powerup_cpus entry\n");
+
+ /* We boot to the fast cluster */
+ debug("powerup_cpus entry: G cluster\n");
+
+ /* Power up the fast cluster rail partition */
+ debug("powerup_cpus: CRAIL\n");
+ power_partition(CRAIL);
+
+ /* Power up the fast cluster non-CPU partition */
+ debug("powerup_cpus: C0NC\n");
+ power_partition(C0NC);
+
+ /* Power up the fast cluster CPU0 partition */
+ debug("powerup_cpus: CE0\n");
+ power_partition(CE0);
+
+ debug("powerup_cpus: done\n");
+}
+
+void start_cpu(u32 reset_vector)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+ debug("start_cpu entry, reset_vector = %x\n", reset_vector);
+
+ tegra124_init_clocks();
+
+ /* Set power-gating timer multiplier */
+ clrbits_le32(&pmc->pmc_pwrgate_timer_mult, TIMER_MULT_MASK);
+ setbits_le32(&pmc->pmc_pwrgate_timer_mult, MULT_8);
+
+ enable_cpu_power_rail();
+ enable_cpu_clocks();
+ clock_enable_coresight(1);
+ remove_cpu_resets();
+ writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
+ powerup_cpus();
+ debug("start_cpu exit, should continue @ reset_vector\n");
+}
--
cgit v1.1
From 52ef43b052964c15e051c119641d81e1f7051c14 Mon Sep 17 00:00:00 2001
From: Tom Warren
Date: Fri, 24 Jan 2014 12:46:15 -0700
Subject: ARM: tegra: Add CPU (armv7) files for Tegra124
These files are for code that runs on the CPU (A15) on Tegra124 boards.
At this time, there is no A15-specific code here. The warmboot/LP0 files
aren't included as that code hasn't been ported yet.
Signed-off-by: Tom Warren
Signed-off-by: Stephen Warren
Tested-by: Thierry Reding
Signed-off-by: Tom Warren
---
arch/arm/cpu/armv7/tegra124/Makefile | 6 +
arch/arm/cpu/armv7/tegra124/config.mk | 10 +
arch/arm/cpu/tegra124-common/Makefile | 10 +
arch/arm/cpu/tegra124-common/clock.c | 826 +++++++++++++++++++++++++++++++++
arch/arm/cpu/tegra124-common/funcmux.c | 69 +++
arch/arm/cpu/tegra124-common/pinmux.c | 730 +++++++++++++++++++++++++++++
6 files changed, 1651 insertions(+)
create mode 100644 arch/arm/cpu/armv7/tegra124/Makefile
create mode 100644 arch/arm/cpu/armv7/tegra124/config.mk
create mode 100644 arch/arm/cpu/tegra124-common/Makefile
create mode 100644 arch/arm/cpu/tegra124-common/clock.c
create mode 100644 arch/arm/cpu/tegra124-common/funcmux.c
create mode 100644 arch/arm/cpu/tegra124-common/pinmux.c
(limited to 'arch/arm')
diff --git a/arch/arm/cpu/armv7/tegra124/Makefile b/arch/arm/cpu/armv7/tegra124/Makefile
new file mode 100644
index 0000000..7f127b1
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra124/Makefile
@@ -0,0 +1,6 @@
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
diff --git a/arch/arm/cpu/armv7/tegra124/config.mk b/arch/arm/cpu/armv7/tegra124/config.mk
new file mode 100644
index 0000000..2f1c645
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra124/config.mk
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2013
+# NVIDIA Corporation
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering,
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+CONFIG_ARCH_DEVICE_TREE := tegra124
diff --git a/arch/arm/cpu/tegra124-common/Makefile b/arch/arm/cpu/tegra124-common/Makefile
new file mode 100644
index 0000000..ff77992
--- /dev/null
+++ b/arch/arm/cpu/tegra124-common/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += clock.o
+obj-y += funcmux.o
+obj-y += pinmux.o
diff --git a/arch/arm/cpu/tegra124-common/clock.c b/arch/arm/cpu/tegra124-common/clock.c
new file mode 100644
index 0000000..7394363
--- /dev/null
+++ b/arch/arm/cpu/tegra124-common/clock.c
@@ -0,0 +1,826 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Tegra124 Clock control functions */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*
+ * Clock types that we can use as a source. The Tegra124 has muxes for the
+ * peripheral clocks, and in most cases there are four options for the clock
+ * source. This gives us a clock 'type' and exploits what commonality exists
+ * in the device.
+ *
+ * Letters are obvious, except for T which means CLK_M, and S which means the
+ * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
+ * datasheet) and PLL_M are different things. The former is the basic
+ * clock supplied to the SOC from an external oscillator. The latter is the
+ * memory clock PLL.
+ *
+ * See definitions in clock_id in the header file.
+ */
+enum clock_type_id {
+ CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
+ CLOCK_TYPE_MCPA, /* and so on */
+ CLOCK_TYPE_MCPT,
+ CLOCK_TYPE_PCM,
+ CLOCK_TYPE_PCMT,
+ CLOCK_TYPE_PDCT,
+ CLOCK_TYPE_ACPT,
+ CLOCK_TYPE_ASPTE,
+ CLOCK_TYPE_PMDACD2T,
+ CLOCK_TYPE_PCST,
+
+ CLOCK_TYPE_PC2CC3M,
+ CLOCK_TYPE_PC2CC3S_T,
+ CLOCK_TYPE_PC2CC3M_T,
+ CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
+ CLOCK_TYPE_MC2CC3P_A,
+ CLOCK_TYPE_M,
+ CLOCK_TYPE_MCPTM2C2C3,
+ CLOCK_TYPE_PC2CC3T_S,
+ CLOCK_TYPE_AC2CC3P_TS2,
+
+ CLOCK_TYPE_COUNT,
+ CLOCK_TYPE_NONE = -1, /* invalid clock type */
+};
+
+enum {
+ CLOCK_MAX_MUX = 8 /* number of source options for each clock */
+};
+
+/*
+ * Clock source mux for each clock type. This just converts our enum into
+ * a list of mux sources for use by the code.
+ *
+ * Note:
+ * The extra column in each clock source array is used to store the mask
+ * bits in its register for the source.
+ */
+#define CLK(x) CLOCK_ID_ ## x
+static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
+ { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
+ CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_29},
+ { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
+ CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
+ MASK_BITS_31_29},
+ { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_28},
+
+ /* Additional clock types on Tegra114+ */
+ /* CLOCK_TYPE_PC2CC3M */
+ { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
+ CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_29},
+ /* CLOCK_TYPE_PC2CC3S_T */
+ { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
+ CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE),
+ MASK_BITS_31_29},
+ /* CLOCK_TYPE_PC2CC3M_T */
+ { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
+ CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
+ MASK_BITS_31_29},
+ /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
+ { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
+ CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
+ MASK_BITS_31_29},
+ /* CLOCK_TYPE_MC2CC3P_A */
+ { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
+ CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE),
+ MASK_BITS_31_29},
+ /* CLOCK_TYPE_M */
+ { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ /* CLOCK_TYPE_MCPTM2C2C3 */
+ { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
+ CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE),
+ MASK_BITS_31_29},
+ /* CLOCK_TYPE_PC2CC3T_S */
+ { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
+ CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE),
+ MASK_BITS_31_29},
+ /* CLOCK_TYPE_AC2CC3P_TS2 */
+ { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
+ CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2),
+ MASK_BITS_31_29},
+};
+
+/*
+ * Clock type for each peripheral clock source. We put the name in each
+ * record just so it is easy to match things up
+ */
+#define TYPE(name, type) type
+static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
+ /* 0x00 */
+ TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M),
+ TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T),
+ TYPE(PERIPHC_05h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T),
+
+ /* 0x08 */
+ TYPE(PERIPHC_08h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16),
+ TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16),
+ TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
+ TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
+
+ /* 0x10 */
+ TYPE(PERIPHC_10h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_11h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A),
+ TYPE(PERIPHC_13h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_16h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_17h, CLOCK_TYPE_NONE),
+
+ /* 0x18 */
+ TYPE(PERIPHC_18h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_1Bh, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_1Ch, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T),
+
+ /* 0x20 */
+ TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A),
+ TYPE(PERIPHC_21h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_22h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
+ TYPE(PERIPHC_24h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_25h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16),
+ TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3),
+
+ /* 0x28 */
+ TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_29h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A),
+ TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16),
+ TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T),
+
+ /* 0x30 */
+ TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE),
+
+ /* 0x38 */
+ TYPE(PERIPHC_38h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_39h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A),
+ TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE),
+
+ /* 0x40 */
+ TYPE(PERIPHC_40h, CLOCK_TYPE_NONE), /* start with 0x3b0 */
+ TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S),
+ TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16),
+ TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T),
+
+ /* 0x48 */
+ TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2),
+ TYPE(PERIPHC_49h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_DAM0, CLOCK_TYPE_AC2CC3P_TS2),
+ TYPE(PERIPHC_DAM1, CLOCK_TYPE_AC2CC3P_TS2),
+ TYPE(PERIPHC_DAM2, CLOCK_TYPE_AC2CC3P_TS2),
+ TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T),
+ TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
+
+ /* 0x50 */
+ TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
+ TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
+ TYPE(PERIPHC_52h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T),
+ TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_55h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_56h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_57h, CLOCK_TYPE_NONE),
+
+ /* 0x58 */
+ TYPE(PERIPHC_58h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_59h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T),
+ TYPE(PERIPHC_5fh, CLOCK_TYPE_NONE),
+
+ /* 0x60 */
+ TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_XUSB_FS, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_XUSB_SS, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_CILAB, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_CILCD, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_CILE, CLOCK_TYPE_NONE),
+
+ /* 0x68 */
+ TYPE(PERIPHC_DSIA_LP, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_DSIB_LP, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_ENTROPY, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_DVFS_REF, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_DVFS_SOC, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_ADX0, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_AMX0, CLOCK_TYPE_NONE),
+
+ /* 0x70 */
+ TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SOC_THERM, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_72h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_73h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_74h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_75h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_I2C6, CLOCK_TYPE_PC2CC3M_T16),
+
+ /* 0x78 */
+ TYPE(PERIPHC_78h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_EMC_DLL, CLOCK_TYPE_MCPTM2C2C3),
+ TYPE(PERIPHC_HDMI_AUDIO, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_CLK72MHZ, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_ADX1, CLOCK_TYPE_AC2CC3P_TS2),
+ TYPE(PERIPHC_AMX1, CLOCK_TYPE_AC2CC3P_TS2),
+ TYPE(PERIPHC_VIC, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_7Fh, CLOCK_TYPE_NONE),
+};
+
+/*
+ * This array translates a periph_id to a periphc_internal_id
+ *
+ * Not present/matched up:
+ * uint vi_sensor; _VI_SENSOR_0, 0x1A8
+ * SPDIF - which is both 0x08 and 0x0c
+ *
+ */
+#define NONE(name) (-1)
+#define OFFSET(name, value) PERIPHC_ ## name
+static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
+ /* Low word: 31:0 */
+ NONE(CPU),
+ NONE(COP),
+ NONE(TRIGSYS),
+ NONE(ISPB),
+ NONE(RESERVED4),
+ NONE(TMR),
+ PERIPHC_UART1,
+ PERIPHC_UART2, /* and vfir 0x68 */
+
+ /* 8 */
+ NONE(GPIO),
+ PERIPHC_SDMMC2,
+ PERIPHC_SPDIF_IN,
+ PERIPHC_I2S1,
+ PERIPHC_I2C1,
+ NONE(RESERVED13),
+ PERIPHC_SDMMC1,
+ PERIPHC_SDMMC4,
+
+ /* 16 */
+ NONE(TCW),
+ PERIPHC_PWM,
+ PERIPHC_I2S2,
+ NONE(RESERVED19),
+ PERIPHC_VI,
+ NONE(RESERVED21),
+ NONE(USBD),
+ NONE(ISP),
+
+ /* 24 */
+ NONE(RESERVED24),
+ NONE(RESERVED25),
+ PERIPHC_DISP2,
+ PERIPHC_DISP1,
+ PERIPHC_HOST1X,
+ NONE(VCP),
+ PERIPHC_I2S0,
+ NONE(CACHE2),
+
+ /* Middle word: 63:32 */
+ NONE(MEM),
+ NONE(AHBDMA),
+ NONE(APBDMA),
+ NONE(RESERVED35),
+ NONE(RESERVED36),
+ NONE(STAT_MON),
+ NONE(RESERVED38),
+ NONE(FUSE),
+
+ /* 40 */
+ NONE(KFUSE),
+ PERIPHC_SBC1, /* SBCx = SPIx */
+ PERIPHC_NOR,
+ NONE(RESERVED43),
+ PERIPHC_SBC2,
+ NONE(XIO),
+ PERIPHC_SBC3,
+ PERIPHC_I2C5,
+
+ /* 48 */
+ NONE(DSI),
+ NONE(RESERVED49),
+ PERIPHC_HSI,
+ PERIPHC_HDMI,
+ NONE(CSI),
+ NONE(RESERVED53),
+ PERIPHC_I2C2,
+ PERIPHC_UART3,
+
+ /* 56 */
+ NONE(MIPI_CAL),
+ PERIPHC_EMC,
+ NONE(USB2),
+ NONE(USB3),
+ NONE(RESERVED60),
+ PERIPHC_VDE,
+ NONE(BSEA),
+ NONE(BSEV),
+
+ /* Upper word 95:64 */
+ NONE(RESERVED64),
+ PERIPHC_UART4,
+ PERIPHC_UART5,
+ PERIPHC_I2C3,
+ PERIPHC_SBC4,
+ PERIPHC_SDMMC3,
+ NONE(PCIE),
+ PERIPHC_OWR,
+
+ /* 72 */
+ NONE(AFI),
+ PERIPHC_CSITE,
+ NONE(PCIEXCLK),
+ NONE(AVPUCQ),
+ NONE(LA),
+ NONE(TRACECLKIN),
+ NONE(SOC_THERM),
+ NONE(DTV),
+
+ /* 80 */
+ NONE(RESERVED80),
+ PERIPHC_I2CSLOW,
+ NONE(DSIB),
+ PERIPHC_TSEC,
+ NONE(RESERVED84),
+ NONE(RESERVED85),
+ NONE(RESERVED86),
+ NONE(EMUCIF),
+
+ /* 88 */
+ NONE(RESERVED88),
+ NONE(XUSB_HOST),
+ NONE(RESERVED90),
+ PERIPHC_MSENC,
+ NONE(RESERVED92),
+ NONE(RESERVED93),
+ NONE(RESERVED94),
+ NONE(XUSB_DEV),
+
+ /* V word: 31:0 */
+ NONE(CPUG),
+ NONE(CPULP),
+ NONE(V_RESERVED2),
+ PERIPHC_MSELECT,
+ NONE(V_RESERVED4),
+ PERIPHC_I2S3,
+ PERIPHC_I2S4,
+ PERIPHC_I2C4,
+
+ /* 104 */
+ PERIPHC_SBC5,
+ PERIPHC_SBC6,
+ PERIPHC_AUDIO,
+ NONE(APBIF),
+ PERIPHC_DAM0,
+ PERIPHC_DAM1,
+ PERIPHC_DAM2,
+ PERIPHC_HDA2CODEC2X,
+
+ /* 112 */
+ NONE(ATOMICS),
+ NONE(V_RESERVED17),
+ NONE(V_RESERVED18),
+ NONE(V_RESERVED19),
+ NONE(V_RESERVED20),
+ NONE(V_RESERVED21),
+ NONE(V_RESERVED22),
+ PERIPHC_ACTMON,
+
+ /* 120 */
+ NONE(EXTPERIPH1),
+ NONE(EXTPERIPH2),
+ NONE(EXTPERIPH3),
+ NONE(OOB),
+ PERIPHC_SATA,
+ PERIPHC_HDA,
+ NONE(TZRAM),
+ NONE(SE),
+
+ /* W word: 31:0 */
+ NONE(HDA2HDMICODEC),
+ NONE(SATACOLD),
+ NONE(W_RESERVED2),
+ NONE(W_RESERVED3),
+ NONE(W_RESERVED4),
+ NONE(W_RESERVED5),
+ NONE(W_RESERVED6),
+ NONE(W_RESERVED7),
+
+ /* 136 */
+ NONE(CEC),
+ NONE(W_RESERVED9),
+ NONE(W_RESERVED10),
+ NONE(W_RESERVED11),
+ NONE(W_RESERVED12),
+ NONE(W_RESERVED13),
+ NONE(XUSB_PADCTL),
+ NONE(W_RESERVED15),
+
+ /* 144 */
+ NONE(W_RESERVED16),
+ NONE(W_RESERVED17),
+ NONE(W_RESERVED18),
+ NONE(W_RESERVED19),
+ NONE(W_RESERVED20),
+ NONE(ENTROPY),
+ NONE(DDS),
+ NONE(W_RESERVED23),
+
+ /* 152 */
+ NONE(DP2),
+ NONE(AMX0),
+ NONE(ADX0),
+ NONE(DVFS),
+ NONE(XUSB_SS),
+ NONE(W_RESERVED29),
+ NONE(W_RESERVED30),
+ NONE(W_RESERVED31),
+
+ /* X word: 31:0 */
+ NONE(SPARE),
+ NONE(X_RESERVED1),
+ NONE(X_RESERVED2),
+ NONE(X_RESERVED3),
+ NONE(CAM_MCLK),
+ NONE(CAM_MCLK2),
+ PERIPHC_I2C6,
+ NONE(X_RESERVED7),
+
+ /* 168 */
+ NONE(X_RESERVED8),
+ NONE(X_RESERVED9),
+ NONE(X_RESERVED10),
+ NONE(VIM2_CLK),
+ NONE(X_RESERVED12),
+ NONE(X_RESERVED13),
+ NONE(EMC_DLL),
+ NONE(X_RESERVED15),
+
+ /* 176 */
+ NONE(HDMI_AUDIO),
+ NONE(CLK72MHZ),
+ NONE(VIC),
+ NONE(X_RESERVED19),
+ NONE(ADX1),
+ NONE(DPAUX),
+ NONE(SOR0),
+ NONE(X_RESERVED23),
+
+ /* 184 */
+ NONE(GPU),
+ NONE(AMX1),
+ NONE(X_RESERVED26),
+ NONE(X_RESERVED27),
+ NONE(X_RESERVED28),
+ NONE(X_RESERVED29),
+ NONE(X_RESERVED30),
+ NONE(X_RESERVED31),
+};
+
+/*
+ * Get the oscillator frequency, from the corresponding hardware configuration
+ * field. Note that Tegra30+ support 3 new higher freqs, but we map back
+ * to the old T20 freqs. Support for the higher oscillators is TBD.
+ */
+enum clock_osc_freq clock_get_osc_freq(void)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ reg = readl(&clkrst->crc_osc_ctrl);
+ reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
+
+ if (reg & 1) /* one of the newer freqs */
+ printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
+
+ return reg >> 2; /* Map to most common (T20) freqs */
+}
+
+/* Returns a pointer to the clock source register for a peripheral */
+u32 *get_periph_source_reg(enum periph_id periph_id)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ enum periphc_internal_id internal_id;
+
+ /* Coresight is a special case */
+ if (periph_id == PERIPH_ID_CSI)
+ return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
+
+ assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
+ internal_id = periph_id_to_internal_id[periph_id];
+ assert(internal_id != -1);
+ if (internal_id >= PERIPHC_VW_FIRST) {
+ internal_id -= PERIPHC_VW_FIRST;
+ return &clkrst->crc_clk_src_vw[internal_id];
+ } else {
+ return &clkrst->crc_clk_src[internal_id];
+ }
+}
+
+/**
+ * Given a peripheral ID and the required source clock, this returns which
+ * value should be programmed into the source mux for that peripheral.
+ *
+ * There is special code here to handle the one source type with 5 sources.
+ *
+ * @param periph_id peripheral to start
+ * @param source PLL id of required parent clock
+ * @param mux_bits Set to number of bits in mux register: 2 or 4
+ * @param divider_bits Set to number of divider bits (8 or 16)
+ * @return mux value (0-4, or -1 if not found)
+ */
+int get_periph_clock_source(enum periph_id periph_id,
+ enum clock_id parent, int *mux_bits, int *divider_bits)
+{
+ enum clock_type_id type;
+ enum periphc_internal_id internal_id;
+ int mux;
+
+ assert(clock_periph_id_isvalid(periph_id));
+
+ internal_id = periph_id_to_internal_id[periph_id];
+ assert(periphc_internal_id_isvalid(internal_id));
+
+ type = clock_periph_type[internal_id];
+ assert(clock_type_id_isvalid(type));
+
+ *mux_bits = clock_source[type][CLOCK_MAX_MUX];
+
+ if (type == CLOCK_TYPE_PC2CC3M_T16)
+ *divider_bits = 16;
+ else
+ *divider_bits = 8;
+
+ for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
+ if (clock_source[type][mux] == parent)
+ return mux;
+
+ /* if we get here, either us or the caller has made a mistake */
+ printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
+ parent);
+ return -1;
+}
+
+void clock_set_enable(enum periph_id periph_id, int enable)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 *clk;
+ u32 reg;
+
+ /* Enable/disable the clock to this peripheral */
+ assert(clock_periph_id_isvalid(periph_id));
+ if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
+ clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
+ else
+ clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
+ reg = readl(clk);
+ if (enable)
+ reg |= PERIPH_MASK(periph_id);
+ else
+ reg &= ~PERIPH_MASK(periph_id);
+ writel(reg, clk);
+}
+
+void reset_set_enable(enum periph_id periph_id, int enable)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 *reset;
+ u32 reg;
+
+ /* Enable/disable reset to the peripheral */
+ assert(clock_periph_id_isvalid(periph_id));
+ if (periph_id < PERIPH_ID_VW_FIRST)
+ reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
+ else
+ reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
+ reg = readl(reset);
+ if (enable)
+ reg |= PERIPH_MASK(periph_id);
+ else
+ reg &= ~PERIPH_MASK(periph_id);
+ writel(reg, reset);
+}
+
+#ifdef CONFIG_OF_CONTROL
+/*
+ * Convert a device tree clock ID to our peripheral ID. They are mostly
+ * the same but we are very cautious so we check that a valid clock ID is
+ * provided.
+ *
+ * @param clk_id Clock ID according to tegra124 device tree binding
+ * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
+ */
+enum periph_id clk_id_to_periph_id(int clk_id)
+{
+ if (clk_id > PERIPH_ID_COUNT)
+ return PERIPH_ID_NONE;
+
+ switch (clk_id) {
+ case PERIPH_ID_RESERVED4:
+ case PERIPH_ID_RESERVED25:
+ case PERIPH_ID_RESERVED35:
+ case PERIPH_ID_RESERVED36:
+ case PERIPH_ID_RESERVED38:
+ case PERIPH_ID_RESERVED43:
+ case PERIPH_ID_RESERVED49:
+ case PERIPH_ID_RESERVED53:
+ case PERIPH_ID_RESERVED64:
+ case PERIPH_ID_RESERVED84:
+ case PERIPH_ID_RESERVED85:
+ case PERIPH_ID_RESERVED86:
+ case PERIPH_ID_RESERVED88:
+ case PERIPH_ID_RESERVED90:
+ case PERIPH_ID_RESERVED92:
+ case PERIPH_ID_RESERVED93:
+ case PERIPH_ID_RESERVED94:
+ case PERIPH_ID_V_RESERVED2:
+ case PERIPH_ID_V_RESERVED4:
+ case PERIPH_ID_V_RESERVED17:
+ case PERIPH_ID_V_RESERVED18:
+ case PERIPH_ID_V_RESERVED19:
+ case PERIPH_ID_V_RESERVED20:
+ case PERIPH_ID_V_RESERVED21:
+ case PERIPH_ID_V_RESERVED22:
+ case PERIPH_ID_W_RESERVED2:
+ case PERIPH_ID_W_RESERVED3:
+ case PERIPH_ID_W_RESERVED4:
+ case PERIPH_ID_W_RESERVED5:
+ case PERIPH_ID_W_RESERVED6:
+ case PERIPH_ID_W_RESERVED7:
+ case PERIPH_ID_W_RESERVED9:
+ case PERIPH_ID_W_RESERVED10:
+ case PERIPH_ID_W_RESERVED11:
+ case PERIPH_ID_W_RESERVED12:
+ case PERIPH_ID_W_RESERVED13:
+ case PERIPH_ID_W_RESERVED15:
+ case PERIPH_ID_W_RESERVED16:
+ case PERIPH_ID_W_RESERVED17:
+ case PERIPH_ID_W_RESERVED18:
+ case PERIPH_ID_W_RESERVED19:
+ case PERIPH_ID_W_RESERVED20:
+ case PERIPH_ID_W_RESERVED23:
+ case PERIPH_ID_W_RESERVED29:
+ case PERIPH_ID_W_RESERVED30:
+ case PERIPH_ID_W_RESERVED31:
+ return PERIPH_ID_NONE;
+ default:
+ return clk_id;
+ }
+}
+#endif /* CONFIG_OF_CONTROL */
+
+void clock_early_init(void)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+
+ tegra30_set_up_pllp();
+
+ /*
+ * PLLC output frequency set to 600Mhz
+ * PLLD output frequency set to 925Mhz
+ */
+ switch (clock_get_osc_freq()) {
+ case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+ clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
+ clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
+ break;
+
+ case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
+ clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
+ clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
+ break;
+
+ case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+ clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
+ clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
+ break;
+ case CLOCK_OSC_FREQ_19_2:
+ default:
+ /*
+ * These are not supported. It is too early to print a
+ * message and the UART likely won't work anyway due to the
+ * oscillator being wrong.
+ */
+ break;
+ }
+
+ /* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
+ writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);
+
+ /* PLLC_MISC: Set LOCK_ENABLE */
+ writel(0x01000000, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc);
+ udelay(2);
+
+ /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1 */
+ writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
+ udelay(2);
+}
+
+void arch_timer_init(void)
+{
+ struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
+ u32 freq, val;
+
+ freq = clock_get_rate(CLOCK_ID_OSC);
+ debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq);
+
+ /* ARM CNTFRQ */
+ asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
+
+ /* Only Tegra114+ has the System Counter regs */
+ debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
+ writel(freq, &sysctr->cntfid0);
+
+ val = readl(&sysctr->cntcr);
+ val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
+ writel(val, &sysctr->cntcr);
+ debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
+}
diff --git a/arch/arm/cpu/tegra124-common/funcmux.c b/arch/arm/cpu/tegra124-common/funcmux.c
new file mode 100644
index 0000000..d19fda0
--- /dev/null
+++ b/arch/arm/cpu/tegra124-common/funcmux.c
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Tegra124 high-level function multiplexing */
+
+#include
+#include
+#include
+#include
+
+int funcmux_select(enum periph_id id, int config)
+{
+ int bad_config = config != FUNCMUX_DEFAULT;
+
+ switch (id) {
+ case PERIPH_ID_UART4:
+ switch (config) {
+ case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */
+ pinmux_set_func(PINGRP_GPIO_PJ7, PMUX_FUNC_UARTD);
+ pinmux_set_func(PINGRP_GPIO_PB0, PMUX_FUNC_UARTD);
+ pinmux_set_func(PINGRP_GPIO_PB1, PMUX_FUNC_UARTD);
+ pinmux_set_func(PINGRP_GPIO_PK7, PMUX_FUNC_UARTD);
+
+ pinmux_set_io(PINGRP_GPIO_PJ7, PMUX_PIN_OUTPUT);
+ pinmux_set_io(PINGRP_GPIO_PB0, PMUX_PIN_INPUT);
+ pinmux_set_io(PINGRP_GPIO_PB1, PMUX_PIN_INPUT);
+ pinmux_set_io(PINGRP_GPIO_PK7, PMUX_PIN_OUTPUT);
+
+ pinmux_tristate_disable(PINGRP_GPIO_PJ7);
+ pinmux_tristate_disable(PINGRP_GPIO_PB0);
+ pinmux_tristate_disable(PINGRP_GPIO_PB1);
+ pinmux_tristate_disable(PINGRP_GPIO_PK7);
+ break;
+ }
+ break;
+
+ case PERIPH_ID_UART1:
+ switch (config) {
+ case FUNCMUX_UART1_KBC:
+ pinmux_set_func(PINGRP_KB_ROW9, PMUX_FUNC_UARTA);
+ pinmux_set_func(PINGRP_KB_ROW10, PMUX_FUNC_UARTA);
+
+ pinmux_set_io(PINGRP_KB_ROW9, PMUX_PIN_OUTPUT);
+ pinmux_set_io(PINGRP_KB_ROW10, PMUX_PIN_INPUT);
+
+ pinmux_tristate_disable(PINGRP_KB_ROW9);
+ pinmux_tristate_disable(PINGRP_KB_ROW10);
+ break;
+ }
+ break;
+
+ /* Add other periph IDs here as needed */
+
+ default:
+ debug("%s: invalid periph_id %d", __func__, id);
+ return -1;
+ }
+
+ if (bad_config) {
+ debug("%s: invalid config %d for periph_id %d", __func__,
+ config, id);
+ return -1;
+ }
+ return 0;
+}
diff --git a/arch/arm/cpu/tegra124-common/pinmux.c b/arch/arm/cpu/tegra124-common/pinmux.c
new file mode 100644
index 0000000..a4ab4ea
--- /dev/null
+++ b/arch/arm/cpu/tegra124-common/pinmux.c
@@ -0,0 +1,730 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Tegra124 pin multiplexing functions */
+
+#include
+#include
+#include
+#include
+
+struct tegra_pingroup_desc {
+ const char *name;
+ enum pmux_func funcs[4];
+ enum pmux_func func_safe;
+ enum pmux_vddio vddio;
+ enum pmux_pin_io io;
+};
+
+#define PMUX_MUXCTL_SHIFT 0
+#define PMUX_PULL_SHIFT 2
+#define PMUX_TRISTATE_SHIFT 4
+#define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT)
+#define PMUX_IO_SHIFT 5
+#define PMUX_OD_SHIFT 6
+#define PMUX_LOCK_SHIFT 7
+#define PMUX_IO_RESET_SHIFT 8
+#define PMUX_RCV_SEL_SHIFT 9
+
+#define PGRP_HSM_SHIFT 2
+#define PGRP_SCHMT_SHIFT 3
+#define PGRP_LPMD_SHIFT 4
+#define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT)
+#define PGRP_DRVDN_SHIFT 12
+#define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT)
+#define PGRP_DRVUP_SHIFT 20
+#define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT)
+#define PGRP_SLWR_SHIFT 28
+#define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT)
+#define PGRP_SLWF_SHIFT 30
+#define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT)
+
+/* Convenient macro for defining pin group properties */
+#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
+ { \
+ .vddio = PMUX_VDDIO_ ## vdd, \
+ .funcs = { \
+ PMUX_FUNC_ ## f0, \
+ PMUX_FUNC_ ## f1, \
+ PMUX_FUNC_ ## f2, \
+ PMUX_FUNC_ ## f3, \
+ }, \
+ .func_safe = PMUX_FUNC_RSVD1, \
+ .io = PMUX_PIN_ ## iod, \
+ }
+
+/* Input and output pins */
+#define PINI(pg_name, vdd, f0, f1, f2, f3) \
+ PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
+#define PINO(pg_name, vdd, f0, f1, f2, f3) \
+ PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
+
+/* A pin group number which is not used */
+#define PIN_RESERVED \
+ PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
+
+const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
+ /* NAME VDD f0 f1 f2 f3 */
+ PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),
+ PINI(ULPI_CLK, BB, SPI1, SPI5, UARTD, ULPI),
+ PINI(ULPI_DIR, BB, SPI1, SPI5, UARTD, ULPI),
+ PINI(ULPI_NXT, BB, SPI1, SPI5, UARTD, ULPI),
+ PINI(ULPI_STP, BB, SPI1, SPI5, UARTD, ULPI),
+ PINI(DAP3_FS, BB, I2S2, SPI5, DISPA, DISPB),
+ PINI(DAP3_DIN, BB, I2S2, SPI5, DISPA, DISPB),
+ PINI(DAP3_DOUT, BB, I2S2, SPI5, DISPA, DISPB),
+ PINI(DAP3_SCLK, BB, I2S2, SPI5, DISPA, DISPB),
+ PINI(GPIO_PV0, BB, USB, RSVD2, RSVD3, RSVD4),
+ PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(SDMMC1_CLK, SDMMC1, SDMMC1, CLK12, RSVD3, RSVD4),
+ PINI(SDMMC1_CMD, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
+ PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
+ PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, PWM0, SPI4, UARTA),
+ PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, PWM1, SPI4, UARTA),
+ PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, SPI4, UARTA),
+ PIN_RESERVED, /* Reserved: 0x3060 - 0x3064 */
+ PIN_RESERVED,
+ PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
+ PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
+ PIN_RESERVED, /* Reserved: 0x3070 - 0x310c */
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PINI(HDMI_INT, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
+ PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
+ PIN_RESERVED, /* Reserved: 0x311c - 0x3160 */
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
+ PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
+ PINI(UART2_RTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
+ PINI(UART2_CTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
+ PINI(UART3_TXD, UART, UARTC, RSVD2, RSVD3, SPI4),
+ PINI(UART3_RXD, UART, UARTC, RSVD2, RSVD3, SPI4),
+ PINI(UART3_CTS_N, UART, UARTC, SDMMC1, DTV, SPI4),
+ PINI(UART3_RTS_N, UART, UARTC, PWM0, DTV, DISPA),
+ PINI(GPIO_PU0, UART, OWR, UARTA, RSVD3, RSVD4),
+ PINI(GPIO_PU1, UART, RSVD1, UARTA, RSVD3, RSVD4),
+ PINI(GPIO_PU2, UART, RSVD1, UARTA, RSVD3, RSVD4),
+ PINI(GPIO_PU3, UART, PWM0, UARTA, DISPA, DISPB),
+ PINI(GPIO_PU4, UART, PWM1, UARTA, DISPA, DISPB),
+ PINI(GPIO_PU5, UART, PWM2, UARTA, DISPA, DISPB),
+ PINI(GPIO_PU6, UART, PWM3, UARTA, USB, DISPB),
+ PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),
+ PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),
+ PINI(DAP4_FS, UART, I2S3, RSVD2, DTV, RSVD4),
+ PINI(DAP4_DIN, UART, I2S3, RSVD2, RSVD3, RSVD4),
+ PINI(DAP4_DOUT, UART, I2S3, RSVD2, DTV, RSVD4),
+ PINI(DAP4_SCLK, UART, I2S3, RSVD2, RSVD3, RSVD4),
+ PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
+ PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),
+ PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
+ PINI(GMI_IORDY, GMI, SDMMC2, RSVD2, GMI, TRACE),
+ PINI(GMI_WAIT, GMI, SPI4, NAND, GMI, DTV),
+ PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, TRACE),
+ PINI(GMI_CLK, GMI, SDMMC2, NAND, GMI, TRACE),
+ PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, USB),
+ PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, SOC),
+ PINI(GMI_CS2_N, GMI, SDMMC2, NAND, GMI, TRACE),
+ PINI(GMI_CS3_N, GMI, SDMMC2, NAND, GMI, GMI_ALT),
+ PINI(GMI_CS4_N, GMI, USB, NAND, GMI, TRACE),
+ PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SPI4),
+ PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, SDMMC2),
+ PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, SPI4),
+ PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, SPI4),
+ PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, SPI4),
+ PINI(GMI_AD8, GMI, PWM0, NAND, GMI, DTV),
+ PINI(GMI_AD9, GMI, PWM1, NAND, GMI, CLDVFS),
+ PINI(GMI_AD10, GMI, PWM2, NAND, GMI, CLDVFS),
+ PINI(GMI_AD11, GMI, PWM3, NAND, GMI, USB),
+ PINI(GMI_AD12, GMI, SDMMC2, NAND, GMI, RSVD4),
+ PINI(GMI_AD13, GMI, SDMMC2, NAND, GMI, RSVD4),
+ PINI(GMI_AD14, GMI, SDMMC2, NAND, GMI, DTV),
+ PINI(GMI_AD15, GMI, SDMMC2, NAND, GMI, DTV),
+ PINI(GMI_A16, GMI, UARTD, TRACE, GMI, GMI_ALT),
+ PINI(GMI_A17, GMI, UARTD, RSVD2, GMI, TRACE),
+ PINI(GMI_A18, GMI, UARTD, RSVD2, GMI, TRACE),
+ PINI(GMI_A19, GMI, UARTD, SPI4, GMI, TRACE),
+ PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, SPI4),
+ PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, SOC),
+ PINI(GMI_DQS, GMI, SDMMC2, NAND, GMI, TRACE),
+ PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),
+ PINI(GEN2_I2C_SCL, GMI, I2C2, RSVD2, GMI, RSVD4),
+ PINI(GEN2_I2C_SDA, GMI, I2C2, RSVD2, GMI, RSVD4),
+ PINI(SDMMC4_CLK, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
+ PINI(SDMMC4_CMD, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
+ PINI(SDMMC4_DAT0, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
+ PINI(SDMMC4_DAT1, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
+ PINI(SDMMC4_DAT2, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
+ PINI(SDMMC4_DAT3, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
+ PINI(SDMMC4_DAT4, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
+ PINI(SDMMC4_DAT5, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
+ PINI(SDMMC4_DAT6, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
+ PINI(SDMMC4_DAT7, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
+ PIN_RESERVED, /* Reserved: 0x3280 */
+ PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT3, RSVD4),
+ PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, RSVD4),
+ PINI(GPIO_PBB0, CAM, I2S4, VI, VI_ALT1, VI_ALT3),
+ PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, RSVD4),
+ PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, RSVD4),
+ PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, RSVD4),
+ PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, RSVD4),
+ PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, RSVD4),
+ PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, RSVD4),
+ PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, RSVD4),
+ PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),
+ PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),
+ PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
+ PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
+ PINI(KB_ROW0, SYS, KBC, RSVD2, DTV, RSVD4),
+ PINI(KB_ROW1, SYS, KBC, RSVD2, DTV, RSVD4),
+ PINI(KB_ROW2, SYS, KBC, RSVD2, DTV, SOC),
+ PINI(KB_ROW3, SYS, KBC, DISPA, RSVD3, DISPB),
+ PINI(KB_ROW4, SYS, KBC, DISPA, SPI2, DISPB),
+ PINI(KB_ROW5, SYS, KBC, DISPA, SPI2, DISPB),
+ PINI(KB_ROW6, SYS, KBC, DISPA, RSVD3, DISPB),
+ PINI(KB_ROW7, SYS, KBC, RSVD2, CLDVFS, UARTA),
+ PINI(KB_ROW8, SYS, KBC, RSVD2, RSVD3, UARTA),
+ PINI(KB_ROW9, SYS, KBC, RSVD2, RSVD3, UARTA),
+ PINI(KB_ROW10, SYS, KBC, RSVD2, RSVD3, UARTA),
+ PIN_RESERVED, /* Reserved: 0x32e8 - 0x32f8 */
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PINI(KB_COL0, SYS, KBC, USB, SPI2, EMC_DLL),
+ PINI(KB_COL1, SYS, KBC, RSVD2, SPI2, EMC_DLL),
+ PINI(KB_COL2, SYS, KBC, RSVD2, SPI2, RSVD4),
+ PINI(KB_COL3, SYS, KBC, DISPA, PWM2, UARTA),
+ PINI(KB_COL4, SYS, KBC, OWR, SDMMC3, UARTA),
+ PINI(KB_COL5, SYS, KBC, RSVD2, SDMMC1, RSVD4),
+ PINI(KB_COL6, SYS, KBC, RSVD2, SPI2, RSVD4),
+ PINI(KB_COL7, SYS, KBC, RSVD2, SPI2, RSVD4),
+ PINI(CLK_32K_OUT, SYS, BLINK, SOC, RSVD3, RSVD4),
+ PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),
+ PINI(CORE_PWR_REQ, SYS, PWRON, RSVD2, RSVD3, RSVD4),
+ PINI(CPU_PWR_REQ, SYS, CPU, RSVD2, RSVD3, RSVD4),
+ PINI(PWR_INT_N, SYS, PMI, RSVD2, RSVD3, RSVD4),
+ PINI(CLK_32K_IN, SYS, CLK, RSVD2, RSVD3, RSVD4),
+ PINI(OWR, SYS, OWR, RSVD2, RSVD3, RSVD4),
+ PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, RSVD4),
+ PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, RSVD4),
+ PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, RSVD4),
+ PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, RSVD4),
+ PINI(CLK1_REQ, AUDIO, DAP, DAP1, RSVD3, RSVD4),
+ PINI(CLK1_OUT, AUDIO, EXTPERIPH1, DAP2, RSVD3, RSVD4),
+ PINI(SPDIF_IN, AUDIO, SPDIF, USB, RSVD3, RSVD4),
+ PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, RSVD3, RSVD4),
+ PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, RSVD4),
+ PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, RSVD4),
+ PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, RSVD4),
+ PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, RSVD4),
+ PINI(DVFS_PWM, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
+ PINI(GPIO_X1_AUD, AUDIO, SPI6, RSVD2, RSVD3, RSVD4),
+ PINI(GPIO_X3_AUD, AUDIO, SPI6, SPI1, RSVD3, RSVD4),
+ PINI(DVFS_CLK, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
+ PINI(GPIO_X4_AUD, AUDIO, RSVD1, SPI1, SPI2, DAP2),
+ PINI(GPIO_X5_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
+ PINI(GPIO_X6_AUD, AUDIO, SPI6, SPI1, SPI2, RSVD4),
+ PINI(GPIO_X7_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
+ PIN_RESERVED, /* Reserved: 0x3388 - 0x338c */
+ PIN_RESERVED,
+ PINI(SDMMC3_CLK, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
+ PINI(SDMMC3_CMD, SDMMC3, SDMMC3, PWM3, UARTA, SPI3),
+ PINI(SDMMC3_DAT0, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
+ PINI(SDMMC3_DAT1, SDMMC3, SDMMC3, PWM2, UARTA, SPI3),
+ PINI(SDMMC3_DAT2, SDMMC3, SDMMC3, PWM1, DISPA, SPI3),
+ PINI(SDMMC3_DAT3, SDMMC3, SDMMC3, PWM0, DISPB, SPI3),
+ PIN_RESERVED, /* Reserved: 0x33a8 - 0x33dc */
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PIN_RESERVED,
+ PINI(HDMI_CEC, SYS, CEC, SDMMC3, RSVD3, SOC),
+ PINI(SDMMC1_WP_N, SDMMC1, SDMMC1, CLK12, SPI4, UARTA),
+ PINI(SDMMC3_CD_N, SYS, SDMMC3, OWR, RSVD3, RSVD4),
+ PINI(GPIO_W2_AUD, AUDIO, SPI6, RSVD2, SPI2, I2C1),
+ PINI(GPIO_W3_AUD, AUDIO, SPI6, SPI1, SPI2, I2C1),
+ PINI(USB_VBUS_EN0, LCD, USB, RSVD2, RSVD3, RSVD4),
+ PINI(USB_VBUS_EN1, LCD, USB, RSVD2, RSVD3, RSVD4),
+ PINI(SDMMC3_CLK_LB_IN, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
+ PINI(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
+ PIN_RESERVED, /* Reserved: 0x3404 */
+ PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
+};
+
+void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *tri = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin */
+ assert(pmux_pingrp_isvalid(pin));
+
+ reg = readl(tri);
+ if (enable)
+ reg |= PMUX_TRISTATE_MASK;
+ else
+ reg &= ~PMUX_TRISTATE_MASK;
+ writel(reg, tri);
+}
+
+void pinmux_tristate_enable(enum pmux_pingrp pin)
+{
+ pinmux_set_tristate(pin, 1);
+}
+
+void pinmux_tristate_disable(enum pmux_pingrp pin)
+{
+ pinmux_set_tristate(pin, 0);
+}
+
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pull = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and pupd */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_pupd_isvalid(pupd));
+
+ reg = readl(pull);
+ reg &= ~(0x3 << PMUX_PULL_SHIFT);
+ reg |= (pupd << PMUX_PULL_SHIFT);
+ writel(reg, pull);
+}
+
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *muxctl = &pmt->pmt_ctl[pin];
+ int i, mux = -1;
+ u32 reg;
+
+ /* Error check on pin and func */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_func_isvalid(func));
+
+ /* Handle special values */
+ if (func == PMUX_FUNC_SAFE)
+ func = tegra_soc_pingroups[pin].func_safe;
+
+ if (func & PMUX_FUNC_RSVD1) {
+ mux = func & 0x3;
+ } else {
+ /* Search for the appropriate function */
+ for (i = 0; i < 4; i++) {
+ if (tegra_soc_pingroups[pin].funcs[i] == func) {
+ mux = i;
+ break;
+ }
+ }
+ }
+ assert(mux != -1);
+
+ reg = readl(muxctl);
+ reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
+ reg |= (mux << PMUX_MUXCTL_SHIFT);
+ writel(reg, muxctl);
+}
+
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pin_io = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and io */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_io_isvalid(io));
+
+ reg = readl(pin_io);
+ reg &= ~(0x1 << PMUX_IO_SHIFT);
+ reg |= (io & 0x1) << PMUX_IO_SHIFT;
+ writel(reg, pin_io);
+}
+
+static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pin_lock = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and lock */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_lock_isvalid(lock));
+
+ if (lock == PMUX_PIN_LOCK_DEFAULT)
+ return 0;
+
+ reg = readl(pin_lock);
+ reg &= ~(0x1 << PMUX_LOCK_SHIFT);
+ if (lock == PMUX_PIN_LOCK_ENABLE) {
+ reg |= (0x1 << PMUX_LOCK_SHIFT);
+ } else {
+ /* lock == DISABLE, which isn't possible */
+ printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
+ __func__, lock);
+ }
+ writel(reg, pin_lock);
+
+ return 0;
+}
+
+static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pin_od = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and od */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_od_isvalid(od));
+
+ if (od == PMUX_PIN_OD_DEFAULT)
+ return 0;
+
+ reg = readl(pin_od);
+ reg &= ~(0x1 << PMUX_OD_SHIFT);
+ if (od == PMUX_PIN_OD_ENABLE)
+ reg |= (0x1 << PMUX_OD_SHIFT);
+ writel(reg, pin_od);
+
+ return 0;
+}
+
+static int pinmux_set_ioreset(enum pmux_pingrp pin,
+ enum pmux_pin_ioreset ioreset)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pin_ioreset = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and ioreset */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_ioreset_isvalid(ioreset));
+
+ if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
+ return 0;
+
+ reg = readl(pin_ioreset);
+ reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
+ if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
+ reg |= (0x1 << PMUX_IO_RESET_SHIFT);
+ writel(reg, pin_ioreset);
+
+ return 0;
+}
+
+static int pinmux_set_rcv_sel(enum pmux_pingrp pin,
+ enum pmux_pin_rcv_sel rcv_sel)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pin_rcv_sel = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and rcv_sel */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
+
+ if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
+ return 0;
+
+ reg = readl(pin_rcv_sel);
+ reg &= ~(0x1 << PMUX_RCV_SEL_SHIFT);
+ if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
+ reg |= (0x1 << PMUX_RCV_SEL_SHIFT);
+ writel(reg, pin_rcv_sel);
+
+ return 0;
+}
+
+void pinmux_config_pingroup(struct pingroup_config *config)
+{
+ enum pmux_pingrp pin = config->pingroup;
+
+ pinmux_set_func(pin, config->func);
+ pinmux_set_pullupdown(pin, config->pull);
+ pinmux_set_tristate(pin, config->tristate);
+ pinmux_set_io(pin, config->io);
+ pinmux_set_lock(pin, config->lock);
+ pinmux_set_od(pin, config->od);
+ pinmux_set_ioreset(pin, config->ioreset);
+ pinmux_set_rcv_sel(pin, config->rcv_sel);
+}
+
+void pinmux_config_table(struct pingroup_config *config, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ pinmux_config_pingroup(&config[i]);
+}
+
+static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, int slwf)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_slwf = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check on pad and slwf */
+ assert(pmux_padgrp_isvalid(pad));
+ assert(pmux_pad_slw_isvalid(slwf));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (slwf == PGRP_SLWF_NONE)
+ return 0;
+
+ reg = readl(pad_slwf);
+ reg &= ~PGRP_SLWF_MASK;
+ reg |= (slwf << PGRP_SLWF_SHIFT);
+ writel(reg, pad_slwf);
+
+ return 0;
+}
+
+static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_slwr = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check on pad and slwr */
+ assert(pmux_padgrp_isvalid(pad));
+ assert(pmux_pad_slw_isvalid(slwr));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (slwr == PGRP_SLWR_NONE)
+ return 0;
+
+ reg = readl(pad_slwr);
+ reg &= ~PGRP_SLWR_MASK;
+ reg |= (slwr << PGRP_SLWR_SHIFT);
+ writel(reg, pad_slwr);
+
+ return 0;
+}
+
+static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_drvup = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check on pad and drvup */
+ assert(pmux_padgrp_isvalid(pad));
+ assert(pmux_pad_drv_isvalid(drvup));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (drvup == PGRP_DRVUP_NONE)
+ return 0;
+
+ reg = readl(pad_drvup);
+ reg &= ~PGRP_DRVUP_MASK;
+ reg |= (drvup << PGRP_DRVUP_SHIFT);
+ writel(reg, pad_drvup);
+
+ return 0;
+}
+
+static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_drvdn = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check on pad and drvdn */
+ assert(pmux_padgrp_isvalid(pad));
+ assert(pmux_pad_drv_isvalid(drvdn));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (drvdn == PGRP_DRVDN_NONE)
+ return 0;
+
+ reg = readl(pad_drvdn);
+ reg &= ~PGRP_DRVDN_MASK;
+ reg |= (drvdn << PGRP_DRVDN_SHIFT);
+ writel(reg, pad_drvdn);
+
+ return 0;
+}
+
+static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_lpmd = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check pad and lpmd value */
+ assert(pmux_padgrp_isvalid(pad));
+ assert(pmux_pad_lpmd_isvalid(lpmd));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (lpmd == PGRP_LPMD_NONE)
+ return 0;
+
+ reg = readl(pad_lpmd);
+ reg &= ~PGRP_LPMD_MASK;
+ reg |= (lpmd << PGRP_LPMD_SHIFT);
+ writel(reg, pad_lpmd);
+
+ return 0;
+}
+
+static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_schmt = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check pad */
+ assert(pmux_padgrp_isvalid(pad));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (schmt == PGRP_SCHMT_NONE)
+ return 0;
+
+ reg = readl(pad_schmt);
+ reg &= ~(1 << PGRP_SCHMT_SHIFT);
+ if (schmt == PGRP_SCHMT_ENABLE)
+ reg |= (0x1 << PGRP_SCHMT_SHIFT);
+ writel(reg, pad_schmt);
+
+ return 0;
+}
+static int padgrp_set_hsm(enum pdrive_pingrp pad, enum pgrp_hsm hsm)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pad_hsm = &pmt->pmt_drive[pad];
+ u32 reg;
+
+ /* Error check pad */
+ assert(pmux_padgrp_isvalid(pad));
+
+ /* NONE means unspecified/do not change/use POR value */
+ if (hsm == PGRP_HSM_NONE)
+ return 0;
+
+ reg = readl(pad_hsm);
+ reg &= ~(1 << PGRP_HSM_SHIFT);
+ if (hsm == PGRP_HSM_ENABLE)
+ reg |= (0x1 << PGRP_HSM_SHIFT);
+ writel(reg, pad_hsm);
+
+ return 0;
+}
+
+void padctrl_config_pingroup(struct padctrl_config *config)
+{
+ enum pdrive_pingrp pad = config->padgrp;
+
+ padgrp_set_drvup_slwf(pad, config->slwf);
+ padgrp_set_drvdn_slwr(pad, config->slwr);
+ padgrp_set_drvup(pad, config->drvup);
+ padgrp_set_drvdn(pad, config->drvdn);
+ padgrp_set_lpmd(pad, config->lpmd);
+ padgrp_set_schmt(pad, config->schmt);
+ padgrp_set_hsm(pad, config->hsm);
+}
+
+void padgrp_config_table(struct padctrl_config *config, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ padctrl_config_pingroup(&config[i]);
+}
--
cgit v1.1
From 2f5dac9214391efc58dc7ea5267b1322d3b18df6 Mon Sep 17 00:00:00 2001
From: Tom Warren
Date: Fri, 24 Jan 2014 12:46:16 -0700
Subject: ARM: tegra: add common (shared) CPU files
These files are used by both SPL and main U-Boot.
Signed-off-by: Tom Warren
Signed-off-by: Stephen Warren
Tested-by: Thierry Reding
Signed-off-by: Tom Warren
---
arch/arm/cpu/tegra-common/ap.c | 16 ++++++++++++----
arch/arm/cpu/tegra-common/board.c | 10 ++++++++--
arch/arm/cpu/tegra-common/cache.c | 10 ++++------
3 files changed, 24 insertions(+), 12 deletions(-)
(limited to 'arch/arm')
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index f205be4..91d70da 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -1,5 +1,5 @@
/*
-* (C) Copyright 2010-2011
+* (C) Copyright 2010-2014
* NVIDIA Corporation
*
* SPDX-License-Identifier: GPL-2.0+
@@ -27,7 +27,7 @@ int tegra_get_chip(void)
/*
* This is undocumented, Chip ID is bits 15:8 of the register
* APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
- * Tegra30, and 0x35 for T114.
+ * Tegra30, 0x35 for T114, and 0x40 for Tegra124.
*/
rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
debug("%s: CHIPID is 0x%02X\n", __func__, rev);
@@ -84,7 +84,15 @@ int tegra_get_chip_sku(void)
return TEGRA_SOC_T114;
}
break;
+ case CHIPID_TEGRA124:
+ switch (sku_id) {
+ case SKU_ID_T124_ENG:
+ default:
+ return TEGRA_SOC_T124;
+ }
+ break;
}
+
/* unknown chip/sku id */
printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n",
__func__, chip_id, sku_id);
@@ -119,8 +127,8 @@ static u32 get_odmdata(void)
* ODMDATA is stored in the BCT in IRAM by the BootROM.
* The BCT start and size are stored in the BIT in IRAM.
* Read the data @ bct_start + (bct_size - 12). This works
- * on T20 and T30 BCTs, which are locked down. If this changes
- * in new chips (T114, etc.), we can revisit this algorithm.
+ * on BCTs for currently supported SoCs, which are locked down.
+ * If this changes in new chips, we can revisit this algorithm.
*/
u32 bct_start, odmdata;
diff --git a/arch/arm/cpu/tegra-common/board.c b/arch/arm/cpu/tegra-common/board.c
index d9cbda8..6a6faf4 100644
--- a/arch/arm/cpu/tegra-common/board.c
+++ b/arch/arm/cpu/tegra-common/board.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2010,2011
+ * (C) Copyright 2010-2014
* NVIDIA Corporation
*
* SPDX-License-Identifier: GPL-2.0+
@@ -109,12 +109,18 @@ static int uart_configs[] = {
-1,
-1,
-1,
-#else /* Tegra114 */
+#elif defined(CONFIG_TEGRA114)
-1,
-1,
-1,
FUNCMUX_UART4_GMI, /* UARTD */
-1,
+#else /* Tegra124 */
+ FUNCMUX_UART1_KBC, /* UARTA */
+ -1,
+ -1,
+ FUNCMUX_UART4_GPIO, /* UARTD */
+ -1,
#endif
};
diff --git a/arch/arm/cpu/tegra-common/cache.c b/arch/arm/cpu/tegra-common/cache.c
index 48e9319..94f5bce 100644
--- a/arch/arm/cpu/tegra-common/cache.c
+++ b/arch/arm/cpu/tegra-common/cache.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -23,8 +23,6 @@
void config_cache(void)
{
- struct apb_misc_gp_ctlr *gp =
- (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
u32 reg = 0;
/* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
@@ -33,10 +31,10 @@ void config_cache(void)
"orr r0, r0, #0x41\n"
"mcr p15, 0, r0, c1, c0, 1\n");
- /* Currently, only T114 needs this L2 cache change to boot Linux */
- reg = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK);
- if (reg != (CHIPID_TEGRA114 << HIDREV_CHIPID_SHIFT))
+ /* Currently, only Tegra114+ needs this L2 cache change to boot Linux */
+ if (tegra_get_chip() < CHIPID_TEGRA114)
return;
+
/*
* Systems with an architectural L2 cache must not use the PL310.
* Config L2CTLR here for a data RAM latency of 3 cycles.
--
cgit v1.1
From a57c5846a21e774c3421b7048dde6e1b763e780c Mon Sep 17 00:00:00 2001
From: Tom Warren
Date: Fri, 24 Jan 2014 12:46:17 -0700
Subject: ARM: tegra: add DT files for Tegra124 and Venice2
These are fairly complete, and near-clones of Tegra114 Venice, with an
additional I2C port, and MMC address changes for Tegra124.
Signed-off-by: Tom Warren
Signed-off-by: Stephen Warren
Tested-by: Thierry Reding
Signed-off-by: Tom Warren
---
arch/arm/dts/tegra124.dtsi | 250 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 250 insertions(+)
create mode 100644 arch/arm/dts/tegra124.dtsi
(limited to 'arch/arm')
diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi
new file mode 100644
index 0000000..18a8b24
--- /dev/null
+++ b/arch/arm/dts/tegra124.dtsi
@@ -0,0 +1,250 @@
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "nvidia,tegra124";
+
+ tegra_car: clock@60006000 {
+ compatible = "nvidia,tegra124-car";
+ reg = <0x60006000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ apbdma: dma@60020000 {
+ compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
+ reg = <0x60020000 0x1400>;
+ interrupts = <0 104 0x04
+ 0 105 0x04
+ 0 106 0x04
+ 0 107 0x04
+ 0 108 0x04
+ 0 109 0x04
+ 0 110 0x04
+ 0 111 0x04
+ 0 112 0x04
+ 0 113 0x04
+ 0 114 0x04
+ 0 115 0x04
+ 0 116 0x04
+ 0 117 0x04
+ 0 118 0x04
+ 0 119 0x04
+ 0 128 0x04
+ 0 129 0x04
+ 0 130 0x04
+ 0 131 0x04
+ 0 132 0x04
+ 0 133 0x04
+ 0 134 0x04
+ 0 135 0x04
+ 0 136 0x04
+ 0 137 0x04
+ 0 138 0x04
+ 0 139 0x04
+ 0 140 0x04
+ 0 141 0x04
+ 0 142 0x04
+ 0 143 0x04>;
+ };
+
+ gpio: gpio@6000d000 {
+ compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
+ reg = <0x6000d000 0x1000>;
+ interrupts = <0 32 0x04
+ 0 33 0x04
+ 0 34 0x04
+ 0 35 0x04
+ 0 55 0x04
+ 0 87 0x04
+ 0 89 0x04
+ 0 125 0x04>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ };
+
+ i2c@7000c000 {
+ compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+ reg = <0x7000c000 0x100>;
+ interrupts = <0 38 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 12>;
+ status = "disabled";
+ };
+
+ i2c@7000c400 {
+ compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+ reg = <0x7000c400 0x100>;
+ interrupts = <0 84 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 54>;
+ status = "disabled";
+ };
+
+ i2c@7000c500 {
+ compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+ reg = <0x7000c500 0x100>;
+ interrupts = <0 92 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 67>;
+ status = "disabled";
+ };
+
+ i2c@7000c700 {
+ compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+ reg = <0x7000c700 0x100>;
+ interrupts = <0 120 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 103>;
+ status = "disabled";
+ };
+
+ i2c@7000d000 {
+ compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+ reg = <0x7000d000 0x100>;
+ interrupts = <0 53 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 47>;
+ status = "disabled";
+ };
+
+ i2c@7000d100 {
+ compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
+ reg = <0x7000d100 0x100>;
+ interrupts = <0 53 0x04>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 47>;
+ status = "disabled";
+ };
+
+ spi@7000d400 {
+ compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+ reg = <0x7000d400 0x200>;
+ interrupts = <0 59 0x04>;
+ nvidia,dma-request-selector = <&apbdma 15>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ clocks = <&tegra_car 41>;
+ };
+
+ spi@7000d600 {
+ compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+ reg = <0x7000d600 0x200>;
+ interrupts = <0 82 0x04>;
+ nvidia,dma-request-selector = <&apbdma 16>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ clocks = <&tegra_car 44>;
+ };
+
+ spi@7000d800 {
+ compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+ reg = <0x7000d800 0x200>;
+ interrupts = <0 83 0x04>;
+ nvidia,dma-request-selector = <&apbdma 17>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ clocks = <&tegra_car 46>;
+ };
+
+ spi@7000da00 {
+ compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+ reg = <0x7000da00 0x200>;
+ interrupts = <0 93 0x04>;
+ nvidia,dma-request-selector = <&apbdma 18>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ clocks = <&tegra_car 68>;
+ };
+
+ spi@7000dc00 {
+ compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+ reg = <0x7000dc00 0x200>;
+ interrupts = <0 94 0x04>;
+ nvidia,dma-request-selector = <&apbdma 27>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ clocks = <&tegra_car 104>;
+ };
+
+ spi@7000de00 {
+ compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
+ reg = <0x7000de00 0x200>;
+ interrupts = <0 79 0x04>;
+ nvidia,dma-request-selector = <&apbdma 28>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ clocks = <&tegra_car 105>;
+ };
+
+ sdhci@700b0000 {
+ compatible = "nvidia,tegra124-sdhci";
+ reg = <0x700b0000 0x200>;
+ interrupts = <0 14 0x04>;
+ clocks = <&tegra_car 14>;
+ status = "disabled";
+ };
+
+ sdhci@700b0200 {
+ compatible = "nvidia,tegra124-sdhci";
+ reg = <0x700b0200 0x200>;
+ interrupts = <0 15 0x04>;
+ clocks = <&tegra_car 9>;
+ status = "disabled";
+ };
+
+ sdhci@700b0400 {
+ compatible = "nvidia,tegra124-sdhci";
+ reg = <0x700b0400 0x200>;
+ interrupts = <0 19 0x04>;
+ clocks = <&tegra_car 69>;
+ status = "disabled";
+ };
+
+ sdhci@700b0600 {
+ compatible = "nvidia,tegra124-sdhci";
+ reg = <0x700b0600 0x200>;
+ interrupts = <0 31 0x04>;
+ clocks = <&tegra_car 15>;
+ status = "disabled";
+ };
+
+ usb@7d000000 {
+ compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
+ reg = <0x7d000000 0x4000>;
+ interrupts = < 52 >;
+ phy_type = "utmi";
+ clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
+ status = "disabled";
+ };
+
+ usb@7d004000 {
+ compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
+ reg = <0x7d004000 0x4000>;
+ interrupts = < 53 >;
+ phy_type = "hsic";
+ clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
+ status = "disabled";
+ };
+
+ usb@7d008000 {
+ compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
+ reg = <0x7d008000 0x4000>;
+ interrupts = < 129 >;
+ phy_type = "utmi";
+ clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
+ status = "disabled";
+ };
+};
--
cgit v1.1
From 790991b0e1391c91662bda56f98fd280015f9628 Mon Sep 17 00:00:00 2001
From: Minkyu Kang
Date: Wed, 29 Jan 2014 17:03:55 +0900
Subject: exynos: pinmux: sort the list of peripherals
Signed-off-by: Minkyu Kang
Acked-by: Rajehswari Shinde
---
arch/arm/include/asm/arch-exynos/periph.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm')
diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h
index 30c7f18..6d77d80 100644
--- a/arch/arm/include/asm/arch-exynos/periph.h
+++ b/arch/arm/include/asm/arch-exynos/periph.h
@@ -36,7 +36,6 @@ enum periph_id {
PERIPH_ID_SDMMC3,
PERIPH_ID_I2C8 = 87,
PERIPH_ID_I2C9,
- PERIPH_ID_I2C10 = 203,
PERIPH_ID_I2S0 = 98,
PERIPH_ID_I2S1 = 99,
@@ -54,6 +53,7 @@ enum periph_id {
PERIPH_ID_PWM2,
PERIPH_ID_PWM3,
PERIPH_ID_PWM4,
+ PERIPH_ID_I2C10 = 203,
PERIPH_ID_COUNT,
PERIPH_ID_NONE = -1,
--
cgit v1.1
From 1501cc94162ded8712c6e854969809ff5a0ab595 Mon Sep 17 00:00:00 2001
From: Minkyu Kang
Date: Wed, 29 Jan 2014 17:03:58 +0900
Subject: exynos: pinmux: remove unnecessary define
The value of PERIPH_ID_COUNT was wrong, and unnecessary.
Signed-off-by: Minkyu Kang
---
arch/arm/cpu/armv7/exynos/clock.c | 2 +-
arch/arm/include/asm/arch-exynos/periph.h | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
(limited to 'arch/arm')
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 5bde9d1..6807ff3 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -26,7 +26,7 @@ struct clk_bit_info {
};
/* src_bit div_bit prediv_bit */
-static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = {
+static struct clk_bit_info clk_bit_info[] = {
{0, 0, -1},
{4, 4, -1},
{8, 8, -1},
diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h
index 6d77d80..5c1c3d4 100644
--- a/arch/arm/include/asm/arch-exynos/periph.h
+++ b/arch/arm/include/asm/arch-exynos/periph.h
@@ -55,7 +55,6 @@ enum periph_id {
PERIPH_ID_PWM4,
PERIPH_ID_I2C10 = 203,
- PERIPH_ID_COUNT,
PERIPH_ID_NONE = -1,
};
--
cgit v1.1
From 0ab9a03ca4af90c52640df23242188e32d40ec83 Mon Sep 17 00:00:00 2001
From: Minkyu Kang
Date: Wed, 29 Jan 2014 17:04:17 +0900
Subject: exynos: pinmux: remove unnecessary routine
Because of the list of peripherals is not sequential,
such a routine does not check for valid correctly.
Error check will be done when call the exynos_pinmux_config function.
Signed-off-by: Minkyu Kang
Acked-by: Jaehoon Chung
Acked-by: Rajeshwari Shinde
---
arch/arm/cpu/armv7/exynos/pinmux.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
(limited to 'arch/arm')
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
index 904177a..645c497 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -751,12 +751,7 @@ static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
if (err)
return PERIPH_ID_NONE;
- /* check for invalid peripheral id */
- if ((PERIPH_ID_SDMMC4 > cell[1]) || (cell[1] < PERIPH_ID_UART0))
- return cell[1];
-
- debug(" invalid peripheral id\n");
- return PERIPH_ID_NONE;
+ return cell[1];
}
int pinmux_decode_periph_id(const void *blob, int node)
--
cgit v1.1
From c8d4b2f8266fac1bcbf9101838939054b8a23011 Mon Sep 17 00:00:00 2001
From: Marek Vasut
Date: Tue, 28 Jan 2014 00:14:28 +0100
Subject: ARM: IXP: Remove the IXP architecture support
The architecture is unmaintained and dead, remove it.
Signed-off-by: Marek Vasut
Cc: Albert Aribaud
Cc: Michael Schwingen
Cc: Tom Rini
---
arch/arm/cpu/ixp/Makefile | 12 -
arch/arm/cpu/ixp/config.mk | 16 -
arch/arm/cpu/ixp/cpu.c | 100 ------
arch/arm/cpu/ixp/interrupts.c | 66 ----
arch/arm/cpu/ixp/start.S | 430 -----------------------
arch/arm/cpu/ixp/timer.c | 101 ------
arch/arm/cpu/ixp/u-boot.lds | 91 -----
arch/arm/include/asm/arch-ixp/ixp425.h | 548 ------------------------------
arch/arm/include/asm/arch-ixp/ixp425pci.h | 174 ----------
arch/arm/include/asm/global_data.h | 3 -
10 files changed, 1541 deletions(-)
delete mode 100644 arch/arm/cpu/ixp/Makefile
delete mode 100644 arch/arm/cpu/ixp/config.mk
delete mode 100644 arch/arm/cpu/ixp/cpu.c
delete mode 100644 arch/arm/cpu/ixp/interrupts.c
delete mode 100644 arch/arm/cpu/ixp/start.S
delete mode 100644 arch/arm/cpu/ixp/timer.c
delete mode 100644 arch/arm/cpu/ixp/u-boot.lds
delete mode 100644 arch/arm/include/asm/arch-ixp/ixp425.h
delete mode 100644 arch/arm/include/asm/arch-ixp/ixp425pci.h
(limited to 'arch/arm')
diff --git a/arch/arm/cpu/ixp/Makefile b/arch/arm/cpu/ixp/Makefile
deleted file mode 100644
index 4e66523..0000000
--- a/arch/arm/cpu/ixp/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-extra-y = start.o
-
-obj-y += cpu.o
-obj-$(CONFIG_USE_IRQ) += interrupts.o
-obj-y += timer.o
diff --git a/arch/arm/cpu/ixp/config.mk b/arch/arm/cpu/ixp/config.mk
deleted file mode 100644
index 894861f..0000000
--- a/arch/arm/cpu/ixp/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH
-# Marius Groeger
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-BIG_ENDIAN = y
-
-PLATFORM_RELFLAGS += -mbig-endian
-
-PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100
-
-PLATFORM_LDFLAGS += -EB
-USE_PRIVATE_LIBGCC = yes
diff --git a/arch/arm/cpu/ixp/cpu.c b/arch/arm/cpu/ixp/cpu.c
deleted file mode 100644
index 4387c18..0000000
--- a/arch/arm/cpu/ixp/cpu.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH
- * Marius Groeger
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH
- * Alex Zuepke
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * CPU specific code
- */
-
-#include
-#include
-#include
-#include
-#include
-
-static void cache_flush(void);
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo (void)
-{
- unsigned long id;
- int speed = 0;
-
- asm ("mrc p15, 0, %0, c0, c0, 0":"=r" (id));
-
- puts("CPU: Intel IXP425 at ");
- switch ((id & 0x000003f0) >> 4) {
- case 0x1c:
- speed = 533;
- break;
-
- case 0x1d:
- speed = 400;
- break;
-
- case 0x1f:
- speed = 266;
- break;
- }
-
- if (speed)
- printf("%d MHz\n", speed);
- else
- puts("unknown revision\n");
-
- return 0;
-}
-#endif /* CONFIG_DISPLAY_CPUINFO */
-
-int cleanup_before_linux (void)
-{
- /*
- * this function is called just before we call linux
- * it prepares the processor for linux
- *
- * just disable everything that can disturb booting linux
- */
-
- disable_interrupts ();
-
- /* turn off I-cache */
- icache_disable();
- dcache_disable();
-
- /* flush I-cache */
- cache_flush();
-
- return 0;
-}
-
-/* flush I/D-cache */
-static void cache_flush (void)
-{
- unsigned long i = 0;
-
- asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
-}
-
-/* FIXME */
-/*
-void pci_init(void)
-{
- return;
-}
-*/
-
-int cpu_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_IXP4XX_NPE
- npe_initialize(bis);
-#endif
- return 0;
-}
diff --git a/arch/arm/cpu/ixp/interrupts.c b/arch/arm/cpu/ixp/interrupts.c
deleted file mode 100644
index 7694c6a..0000000
--- a/arch/arm/cpu/ixp/interrupts.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH
- * Marius Groeger
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH
- * Alex Zuepke
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include
-#include
-#include
-
-struct _irq_handler {
- void *m_data;
- void (*m_func)( void *data);
-};
-
-static struct _irq_handler IRQ_HANDLER[N_IRQS];
-
-static void default_isr(void *data)
-{
- printf("default_isr(): called for IRQ %d, Interrupt Status=%x PR=%x\n",
- (int)data, *IXP425_ICIP, *IXP425_ICIH);
-}
-
-static int next_irq(void)
-{
- return (((*IXP425_ICIH & 0x000000fc) >> 2) - 1);
-}
-
-void do_irq (struct pt_regs *pt_regs)
-{
- int irq = next_irq();
-
- IRQ_HANDLER[irq].m_func(IRQ_HANDLER[irq].m_data);
-}
-
-void irq_install_handler (int irq, interrupt_handler_t handle_irq, void *data)
-{
- if (irq >= N_IRQS || !handle_irq)
- return;
-
- IRQ_HANDLER[irq].m_data = data;
- IRQ_HANDLER[irq].m_func = handle_irq;
-}
-
-int arch_interrupt_init (void)
-{
- int i;
-
- /* install default interrupt handlers */
- for (i = 0; i < N_IRQS; i++)
- irq_install_handler(i, default_isr, (void *)i);
-
- /* configure interrupts for IRQ mode */
- *IXP425_ICLR = 0x00000000;
-
- return (0);
-}
diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S
deleted file mode 100644
index 82c868a..0000000
--- a/arch/arm/cpu/ixp/start.S
+++ /dev/null
@@ -1,430 +0,0 @@
-/* vi: set ts=8 sw=8 noet: */
-/*
- * u-boot - Startup Code for XScale IXP
- *
- * Copyright (C) 2003 Kyle Harris
- *
- * Based on startup code example contained in the
- * Intel IXP4xx Programmer's Guide and past u-boot Start.S
- * samples.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include
-#include
-#include
-#include
-
-#define MMU_Control_M 0x001 /* Enable MMU */
-#define MMU_Control_A 0x002 /* Enable address alignment faults */
-#define MMU_Control_C 0x004 /* Enable cache */
-#define MMU_Control_W 0x008 /* Enable write-buffer */
-#define MMU_Control_P 0x010 /* Compatability: 32 bit code */
-#define MMU_Control_D 0x020 /* Compatability: 32 bit data */
-#define MMU_Control_L 0x040 /* Compatability: */
-#define MMU_Control_B 0x080 /* Enable Big-Endian */
-#define MMU_Control_S 0x100 /* Enable system protection */
-#define MMU_Control_R 0x200 /* Enable ROM protection */
-#define MMU_Control_I 0x1000 /* Enable Instruction cache */
-#define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */
-#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
-
-
-/*
- * Macro definitions
- */
- /* Delay a bit */
- .macro DELAY_FOR cycles, reg0
- ldr \reg0, =\cycles
- subs \reg0, \reg0, #1
- subne pc, pc, #0xc
- .endm
-
- /* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-.globl _start
-_start:
- ldr pc, _reset
- ldr pc, _undefined_instruction
- ldr pc, _software_interrupt
- ldr pc, _prefetch_abort
- ldr pc, _data_abort
- ldr pc, _not_used
- ldr pc, _irq
- ldr pc, _fiq
-
-_reset: .word reset
-_undefined_instruction: .word undefined_instruction
-_software_interrupt: .word software_interrupt
-_prefetch_abort: .word prefetch_abort
-_data_abort: .word data_abort
-_not_used: .word not_used
-_irq: .word irq
-_fiq: .word fiq
-
- .balignl 16,0xdeadbeef
-
-
-/*
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * - relocate armboot to ram
- * - setup stack
- * - jump to second stage
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
- .word CONFIG_SPL_TEXT_BASE
-#else
- .word CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
- .word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
- .word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
- .word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
- .word 0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
- .word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
- .word 0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
- /* disable mmu, set big-endian */
- mov r0, #0xf8
- mcr p15, 0, r0, c1, c0, 0
- CPWAIT r0
-
- /* invalidate I & D caches & BTB */
- mcr p15, 0, r0, c7, c7, 0
- CPWAIT r0
-
- /* invalidate I & Data TLB */
- mcr p15, 0, r0, c8, c7, 0
- CPWAIT r0
-
- /* drain write and fill buffers */
- mcr p15, 0, r0, c7, c10, 4
- CPWAIT r0
-
- /* disable write buffer coalescing */
- mrc p15, 0, r0, c1, c0, 1
- orr r0, r0, #1
- mcr p15, 0, r0, c1, c0, 1
- CPWAIT r0
-
- /* set EXP CS0 to the optimum timing */
- ldr r1, =CONFIG_SYS_EXP_CS0
- ldr r2, =IXP425_EXP_CS0
- str r1, [r2]
-
- /* make sure flash is visible at 0 */
- mov r1, #CONFIG_SYS_SDR_CONFIG
- ldr r2, =IXP425_SDR_CONFIG
- str r1, [r2]
-
- /* disable refresh cycles */
- mov r1, #0
- ldr r3, =IXP425_SDR_REFRESH
- str r1, [r3]
-
- /* send nop command */
- mov r1, #3
- ldr r4, =IXP425_SDR_IR
- str r1, [r4]
- DELAY_FOR 0x4000, r0
-
- /* set SDRAM internal refresh val */
- ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
- str r1, [r3]
- DELAY_FOR 0x4000, r0
-
- /* send precharge-all command to close all open banks */
- mov r1, #2
- str r1, [r4]
- DELAY_FOR 0x4000, r0
-
- /* provide 8 auto-refresh cycles */
- mov r1, #4
- mov r5, #8
-111: str r1, [r4]
- DELAY_FOR 0x100, r0
- subs r5, r5, #1
- bne 111b
-
- /* set mode register in sdram */
- mov r1, #CONFIG_SYS_SDR_MODE_CONFIG
- str r1, [r4]
- DELAY_FOR 0x4000, r0
-
- /* send normal operation command */
- mov r1, #6
- str r1, [r4]
- DELAY_FOR 0x4000, r0
-
- /* invalidate I & D caches & BTB */
- mcr p15, 0, r0, c7, c7, 0
- CPWAIT r0
-
- /* invalidate I & Data TLB */
- mcr p15, 0, r0, c8, c7, 0
- CPWAIT r0
-
- /* drain write and fill buffers */
- mcr p15, 0, r0, c7, c10, 4
- CPWAIT r0
-
- /* remove flash mirror at 0x00000000 */
- ldr r2, =IXP425_EXP_CFG0
- ldr r1, [r2]
- bic r1, r1, #0x80000000
- str r1, [r2]
-
- /* invalidate I & Data TLB */
- mcr p15, 0, r0, c8, c7, 0
- CPWAIT r0
-
- /* enable I cache */
- mrc p15, 0, r0, c1, c0, 0
- orr r0, r0, #MMU_Control_I
- mcr p15, 0, r0, c1, c0, 0
- CPWAIT r0
-
- mrs r0,cpsr /* set the cpu to SVC32 mode */
- bic r0,r0,#0x1f /* (superviser mode, M=10011) */
- orr r0,r0,#0x13
- msr cpsr,r0
-
- bl _main
-
-/*------------------------------------------------------------------------------*/
-
- .globl c_runtime_cpu_setup
-c_runtime_cpu_setup:
-
- bx lr
-
-/****************************************************************************/
-/* */
-/* Interrupt handling */
-/* */
-/****************************************************************************/
-
-/* IRQ stack frame */
-
-#define S_FRAME_SIZE 72
-
-#define S_OLD_R0 68
-#define S_PSR 64
-#define S_PC 60
-#define S_LR 56
-#define S_SP 52
-
-#define S_IP 48
-#define S_FP 44
-#define S_R10 40
-#define S_R9 36
-#define S_R8 32
-#define S_R7 28
-#define S_R6 24
-#define S_R5 20
-#define S_R4 16
-#define S_R3 12
-#define S_R2 8
-#define S_R1 4
-#define S_R0 0
-
-#define MODE_SVC 0x13
-
- /* use bad_save_user_regs for abort/prefetch/undef/swi ... */
-
- .macro bad_save_user_regs
- sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} /* Calling r0-r12 */
- add r8, sp, #S_PC
-
- ldr r2, IRQ_STACK_START_IN
- ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
- add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
-
- add r5, sp, #S_SP
- mov r1, lr
- stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
- mov r0, sp
- .endm
-
-
- /* use irq_save_user_regs / irq_restore_user_regs for */
- /* IRQ/FIQ handling */
-
- .macro irq_save_user_regs
- sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} /* Calling r0-r12 */
- add r8, sp, #S_PC
- stmdb r8, {sp, lr}^ /* Calling SP, LR */
- str lr, [r8, #0] /* Save calling PC */
- mrs r6, spsr
- str r6, [r8, #4] /* Save CPSR */
- str r0, [r8, #8] /* Save OLD_R0 */
- mov r0, sp
- .endm
-
- .macro irq_restore_user_regs
- ldmia sp, {r0 - lr}^ @ Calling r0 - lr
- mov r0, r0
- ldr lr, [sp, #S_PC] @ Get PC
- add sp, sp, #S_FRAME_SIZE
- subs pc, lr, #4 @ return & move spsr_svc into cpsr
- .endm
-
- .macro get_bad_stack
- ldr r13, IRQ_STACK_START_IN @ setup our mode stack
-
- str lr, [r13] @ save caller lr / spsr
- mrs lr, spsr
- str lr, [r13, #4]
-
- mov r13, #MODE_SVC @ prepare SVC-Mode
- msr spsr_c, r13
- mov lr, pc
- movs pc, lr
- .endm
-
- .macro get_irq_stack @ setup IRQ stack
- ldr sp, IRQ_STACK_START
- .endm
-
- .macro get_fiq_stack @ setup FIQ stack
- ldr sp, FIQ_STACK_START
- .endm
-
-
-/****************************************************************************/
-/* */
-/* exception handlers */
-/* */
-/****************************************************************************/
-
- .align 5
-undefined_instruction:
- get_bad_stack
- bad_save_user_regs
- bl do_undefined_instruction
-
- .align 5
-software_interrupt:
- get_bad_stack
- bad_save_user_regs
- bl do_software_interrupt
-
- .align 5
-prefetch_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_prefetch_abort
-
- .align 5
-data_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_data_abort
-
- .align 5
-not_used:
- get_bad_stack
- bad_save_user_regs
- bl do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
- .align 5
-irq:
- get_irq_stack
- irq_save_user_regs
- bl do_irq
- irq_restore_user_regs
-
- .align 5
-fiq:
- get_fiq_stack
- irq_save_user_regs /* someone ought to write a more */
- bl do_fiq /* effiction fiq_save_user_regs */
- irq_restore_user_regs
-
-#else
-
- .align 5
-irq:
- get_bad_stack
- bad_save_user_regs
- bl do_irq
-
- .align 5
-fiq:
- get_bad_stack
- bad_save_user_regs
- bl do_fiq
-
-#endif
-
-/****************************************************************************/
-/* */
-/* Reset function: Use Watchdog to reset */
-/* */
-/****************************************************************************/
-
- .align 5
-.globl reset_cpu
-
-reset_cpu:
- ldr r1, =0x482e
- ldr r2, =IXP425_OSWK
- str r1, [r2]
- ldr r1, =0x0fff
- ldr r2, =IXP425_OSWT
- str r1, [r2]
- ldr r1, =0x5
- ldr r2, =IXP425_OSWE
- str r1, [r2]
- b reset_endless
-
-reset_endless:
- b reset_endless
diff --git a/arch/arm/cpu/ixp/timer.c b/arch/arm/cpu/ixp/timer.c
deleted file mode 100644
index 38e2e28..0000000
--- a/arch/arm/cpu/ixp/timer.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * (C) Copyright 2010
- * Michael Schwingen, michael@schwingen.org
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH
- * Marius Groeger
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH
- * Alex Zuepke
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include
-#include
-#include
-#include
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * The IXP42x time-stamp timer runs at 2*OSC_IN (66.666MHz when using a
- * 33.333MHz crystal).
- */
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
- tick *= CONFIG_SYS_HZ;
- do_div(tick, CONFIG_IXP425_TIMER_CLK);
- return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
- time *= CONFIG_IXP425_TIMER_CLK;
- do_div(time, CONFIG_SYS_HZ);
- return time;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
- us = us * CONFIG_IXP425_TIMER_CLK + 999999;
- do_div(us, 1000000);
- return us;
-}
-
-unsigned long long get_ticks(void)
-{
- ulong now = readl(IXP425_OSTS_B);
-
- if (readl(IXP425_OSST) & IXP425_OSST_TIMER_TS_PEND) {
- /* rollover of timestamp timer register */
- gd->arch.timestamp += (0xFFFFFFFF - gd->arch.lastinc) + now + 1;
- writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST);
- } else {
- /* move stamp forward with absolut diff ticks */
- gd->arch.timestamp += (now - gd->arch.lastinc);
- }
- gd->arch.lastinc = now;
- return gd->arch.timestamp;
-}
-
-
-void reset_timer_masked(void)
-{
- /* capture current timestamp counter */
- gd->arch.lastinc = readl(IXP425_OSTS_B);
- /* start "advancing" time stamp from 0 */
- gd->arch.timestamp = 0;
-}
-
-ulong get_timer_masked(void)
-{
- return tick_to_time(get_ticks());
-}
-
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay(unsigned long usec)
-{
- unsigned long long tmp;
-
- tmp = get_ticks() + us_to_tick(usec);
-
- while (get_ticks() < tmp)
- ;
-}
-
-int timer_init(void)
-{
- writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST);
- return 0;
-}
diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds
deleted file mode 100644
index 676ae2c..0000000
--- a/arch/arm/cpu/ixp/u-boot.lds
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * (C) Copyright 2000-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- *(.__image_copy_start)
- arch/arm/cpu/ixp/start.o(.text*)
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(4);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN(4);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rel.dyn : {
- *(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
- }
-
- _end = .;
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
- *(.bss*)
- . = ALIGN(4);
- __bss_limit = .;
- }
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
- }
-
- .dynsym _end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .hash : { *(.hash*) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
-}
diff --git a/arch/arm/include/asm/arch-ixp/ixp425.h b/arch/arm/include/asm/arch-ixp/ixp425.h
deleted file mode 100644
index c2e9c82..0000000
--- a/arch/arm/include/asm/arch-ixp/ixp425.h
+++ /dev/null
@@ -1,548 +0,0 @@
-/*
- * include/asm-arm/arch-ixp425/ixp425.h
- *
- * Register definitions for IXP425
- *
- * Copyright (C) 2002 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef _ASM_ARM_IXP425_H_
-#define _ASM_ARM_IXP425_H_
-
-#define BIT(x) (1<<(x))
-
-/* FIXME: Only this does work for u-boot... find out why... [RS] */
-#define UBOOT_REG_FIX 1
-#ifdef UBOOT_REG_FIX
-# undef io_p2v
-# undef __REG
-# ifndef __ASSEMBLY__
-# define io_p2v(PhAdd) (PhAdd)
-# define __REG(x) (*((volatile u32 *)io_p2v(x)))
-# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
-# else
-# define __REG(x) (x)
-# endif
-#endif /* UBOOT_REG_FIX */
-
-/*
- *
- * IXP425 Memory map:
- *
- * Phy Phy Size Map Size Virt Description
- * =========================================================================
- *
- * 0x00000000 0x10000000 SDRAM 1
- *
- * 0x10000000 0x10000000 SDRAM 2
- *
- * 0x20000000 0x10000000 SDRAM 3
- *
- * 0x30000000 0x10000000 SDRAM 4
- *
- * The above four are aliases to the same memory location (0x00000000)
- *
- * 0x48000000 0x4000000 PCI Memory
- *
- * 0x50000000 0x10000000 Not Mapped EXP BUS
- *
- * 0x6000000 0x00004000 0x4000 0xFFFEB000 QMgr
- *
- * 0xC0000000 0x100 0x1000 0xFFFDD000 PCI CFG
- *
- * 0xC4000000 0x100 0x1000 0xFFFDE000 EXP CFG
- *
- * 0xC8000000 0xC000 0xC000 0xFFFDF000 PERIPHERAL
- *
- * 0xCC000000 0x100 0x1000 Not Mapped SDRAM CFG
- */
-
-/*
- * SDRAM
- */
-#define IXP425_SDRAM_BASE (0x00000000)
-#define IXP425_SDRAM_BASE_ALT (0x10000000)
-
-
-/*
- * PCI Configuration space
- */
-#define IXP425_PCI_CFG_BASE_PHYS (0xC0000000)
-#define IXP425_PCI_CFG_REGION_SIZE (0x00001000)
-
-/*
- * Expansion BUS Configuration registers
- */
-#define IXP425_EXP_CFG_BASE_PHYS (0xC4000000)
-#define IXP425_EXP_CFG_REGION_SIZE (0x00001000)
-
-/*
- * Peripheral space
- */
-#define IXP425_PERIPHERAL_BASE_PHYS (0xC8000000)
-#define IXP425_PERIPHERAL_REGION_SIZE (0x0000C000)
-
-/*
- * SDRAM configuration registers
- */
-#define IXP425_SDRAM_CFG_BASE_PHYS (0xCC000000)
-
-/*
- * Q Manager space .. not static mapped
- */
-#define IXP425_QMGR_BASE_PHYS (0x60000000)
-#define IXP425_QMGR_REGION_SIZE (0x00004000)
-
-/*
- * Expansion BUS
- *
- * Expansion Bus 'lives' at either base1 or base 2 depending on the value of
- * Exp Bus config registers:
- *
- * Setting bit 31 of IXP425_EXP_CFG0 puts SDRAM at zero,
- * and The expansion bus to IXP425_EXP_BUS_BASE2
- */
-#define IXP425_EXP_BUS_BASE1_PHYS (0x00000000)
-#define IXP425_EXP_BUS_BASE2_PHYS (0x50000000)
-
-#define IXP425_EXP_BUS_BASE_PHYS IXP425_EXP_BUS_BASE2_PHYS
-
-#define IXP425_EXP_BUS_REGION_SIZE (0x08000000)
-#define IXP425_EXP_BUS_CSX_REGION_SIZE (0x01000000)
-
-#define IXP425_EXP_BUS_CS0_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x00000000)
-#define IXP425_EXP_BUS_CS1_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x01000000)
-#define IXP425_EXP_BUS_CS2_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x02000000)
-#define IXP425_EXP_BUS_CS3_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x03000000)
-#define IXP425_EXP_BUS_CS4_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x04000000)
-#define IXP425_EXP_BUS_CS5_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x05000000)
-#define IXP425_EXP_BUS_CS6_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x06000000)
-#define IXP425_EXP_BUS_CS7_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x07000000)
-
-#define IXP425_FLASH_WRITABLE (0x2)
-#define IXP425_FLASH_DEFAULT (0xbcd23c40)
-#define IXP425_FLASH_WRITE (0xbcd23c42)
-
-#define IXP425_EXP_CS0_OFFSET 0x00
-#define IXP425_EXP_CS1_OFFSET 0x04
-#define IXP425_EXP_CS2_OFFSET 0x08
-#define IXP425_EXP_CS3_OFFSET 0x0C
-#define IXP425_EXP_CS4_OFFSET 0x10
-#define IXP425_EXP_CS5_OFFSET 0x14
-#define IXP425_EXP_CS6_OFFSET 0x18
-#define IXP425_EXP_CS7_OFFSET 0x1C
-#define IXP425_EXP_CFG0_OFFSET 0x20
-#define IXP425_EXP_CFG1_OFFSET 0x24
-#define IXP425_EXP_CFG2_OFFSET 0x28
-#define IXP425_EXP_CFG3_OFFSET 0x2C
-
-/*
- * Expansion Bus Controller registers.
- */
-#ifndef __ASSEMBLY__
-#define IXP425_EXP_REG(x) ((volatile u32 *)(IXP425_EXP_CFG_BASE_PHYS+(x)))
-#else
-#define IXP425_EXP_REG(x) (IXP425_EXP_CFG_BASE_PHYS+(x))
-#endif
-
-#define IXP425_EXP_CS0 IXP425_EXP_REG(IXP425_EXP_CS0_OFFSET)
-#define IXP425_EXP_CS1 IXP425_EXP_REG(IXP425_EXP_CS1_OFFSET)
-#define IXP425_EXP_CS2 IXP425_EXP_REG(IXP425_EXP_CS2_OFFSET)
-#define IXP425_EXP_CS3 IXP425_EXP_REG(IXP425_EXP_CS3_OFFSET)
-#define IXP425_EXP_CS4 IXP425_EXP_REG(IXP425_EXP_CS4_OFFSET)
-#define IXP425_EXP_CS5 IXP425_EXP_REG(IXP425_EXP_CS5_OFFSET)
-#define IXP425_EXP_CS6 IXP425_EXP_REG(IXP425_EXP_CS6_OFFSET)
-#define IXP425_EXP_CS7 IXP425_EXP_REG(IXP425_EXP_CS7_OFFSET)
-
-#define IXP425_EXP_CFG0 IXP425_EXP_REG(IXP425_EXP_CFG0_OFFSET)
-#define IXP425_EXP_CFG1 IXP425_EXP_REG(IXP425_EXP_CFG1_OFFSET)
-#define IXP425_EXP_CFG2 IXP425_EXP_REG(IXP425_EXP_CFG2_OFFSET)
-#define IXP425_EXP_CFG3 IXP425_EXP_REG(IXP425_EXP_CFG3_OFFSET)
-
-/*
- * SDRAM Controller registers.
- */
-#define IXP425_SDR_CONFIG_OFFSET 0x00
-#define IXP425_SDR_REFRESH_OFFSET 0x04
-#define IXP425_SDR_IR_OFFSET 0x08
-
-#define IXP425_SDRAM_REG(x) (IXP425_SDRAM_CFG_BASE_PHYS+(x))
-
-#define IXP425_SDR_CONFIG IXP425_SDRAM_REG(IXP425_SDR_CONFIG_OFFSET)
-#define IXP425_SDR_REFRESH IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET)
-#define IXP425_SDR_IR IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET)
-
-/*
- * UART registers
- */
-#define IXP425_UART1 0
-#define IXP425_UART2 0x1000
-
-#define IXP425_UART_RBR_OFFSET 0x00
-#define IXP425_UART_THR_OFFSET 0x00
-#define IXP425_UART_DLL_OFFSET 0x00
-#define IXP425_UART_IER_OFFSET 0x04
-#define IXP425_UART_DLH_OFFSET 0x04
-#define IXP425_UART_IIR_OFFSET 0x08
-#define IXP425_UART_FCR_OFFSET 0x00
-#define IXP425_UART_LCR_OFFSET 0x0c
-#define IXP425_UART_MCR_OFFSET 0x10
-#define IXP425_UART_LSR_OFFSET 0x14
-#define IXP425_UART_MSR_OFFSET 0x18
-#define IXP425_UART_SPR_OFFSET 0x1c
-#define IXP425_UART_ISR_OFFSET 0x20
-
-#define IXP425_UART_CFG_BASE_PHYS (0xc8000000)
-
-#define RBR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_RBR_OFFSET)
-#define THR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_THR_OFFSET)
-#define DLL(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLL_OFFSET)
-#define IER(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IER_OFFSET)
-#define DLH(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLH_OFFSET)
-#define IIR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IIR_OFFSET)
-#define FCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_FCR_OFFSET)
-#define LCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LCR_OFFSET)
-#define MCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MCR_OFFSET)
-#define LSR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LSR_OFFSET)
-#define MSR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MSR_OFFSET)
-#define SPR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_SPR_OFFSET)
-#define ISR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_ISR_OFFSET)
-
-#define IER_DMAE (1 << 7) /* DMA Requests Enable */
-#define IER_UUE (1 << 6) /* UART Unit Enable */
-#define IER_NRZE (1 << 5) /* NRZ coding Enable */
-#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
-#define IER_MIE (1 << 3) /* Modem Interrupt Enable */
-#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
-#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
-#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
-
-#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
-#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
-#define IIR_TOD (1 << 3) /* Time Out Detected */
-#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
-#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
-#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
-
-#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
-#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
-#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
-#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
-#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
-#define FCR_ITL_1 (0)
-#define FCR_ITL_8 (FCR_ITL1)
-#define FCR_ITL_16 (FCR_ITL2)
-#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
-
-#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
-#define LCR_SB (1 << 6) /* Set Break */
-#define LCR_STKYP (1 << 5) /* Sticky Parity */
-#define LCR_EPS (1 << 4) /* Even Parity Select */
-#define LCR_PEN (1 << 3) /* Parity Enable */
-#define LCR_STB (1 << 2) /* Stop Bit */
-#define LCR_WLS1 (1 << 1) /* Word Length Select */
-#define LCR_WLS0 (1 << 0) /* Word Length Select */
-
-#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
-#define LSR_TEMT (1 << 6) /* Transmitter Empty */
-#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
-#define LSR_BI (1 << 4) /* Break Interrupt */
-#define LSR_FE (1 << 3) /* Framing Error */
-#define LSR_PE (1 << 2) /* Parity Error */
-#define LSR_OE (1 << 1) /* Overrun Error */
-#define LSR_DR (1 << 0) /* Data Ready */
-
-#define MCR_LOOP (1 << 4) */
-#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
-#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
-#define MCR_RTS (1 << 1) /* Request to Send */
-#define MCR_DTR (1 << 0) /* Data Terminal Ready */
-
-#define MSR_DCD (1 << 7) /* Data Carrier Detect */
-#define MSR_RI (1 << 6) /* Ring Indicator */
-#define MSR_DSR (1 << 5) /* Data Set Ready */
-#define MSR_CTS (1 << 4) /* Clear To Send */
-#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
-#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
-#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
-#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
-
-#define IXP425_CONSOLE_UART_BASE_PHYS IXP425_UART1_BASE_PHYS
-/*
- * Peripheral Space Registers
- */
-#define IXP425_UART1_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x0000)
-#define IXP425_UART2_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x1000)
-#define IXP425_PMU_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x2000)
-#define IXP425_INTC_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x3000)
-#define IXP425_GPIO_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x4000)
-#define IXP425_TIMER_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x5000)
-#define IXP425_NPEA_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x6000)
-#define IXP425_NPEB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x7000)
-#define IXP425_NPEC_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x8000)
-#define IXP425_EthA_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x9000)
-#define IXP425_EthB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xA000)
-#define IXP425_USB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xB000)
-
-/*
- * UART Register Definitions , Offsets only as there are 2 UARTS.
- * IXP425_UART1_BASE , IXP425_UART2_BASE.
- */
-
-#undef UART_NO_RX_INTERRUPT
-
-#define IXP425_UART_XTAL 14745600
-
-/*
- * Constants to make it easy to access Interrupt Controller registers
- */
-#define IXP425_ICPR_OFFSET 0x00 /* Interrupt Status */
-#define IXP425_ICMR_OFFSET 0x04 /* Interrupt Enable */
-#define IXP425_ICLR_OFFSET 0x08 /* Interrupt IRQ/FIQ Select */
-#define IXP425_ICIP_OFFSET 0x0C /* IRQ Status */
-#define IXP425_ICFP_OFFSET 0x10 /* FIQ Status */
-#define IXP425_ICHR_OFFSET 0x14 /* Interrupt Priority */
-#define IXP425_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */
-#define IXP425_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */
-
-#define N_IRQS 32
-#define IXP425_TIMER_2_IRQ 11
-
-/*
- * Interrupt Controller Register Definitions.
- */
-#ifndef __ASSEMBLY__
-#define IXP425_INTC_REG(x) ((volatile u32 *)(IXP425_INTC_BASE_PHYS+(x)))
-#else
-#define IXP425_INTC_REG(x) (IXP425_INTC_BASE_PHYS+(x))
-#endif
-
-#define IXP425_ICPR IXP425_INTC_REG(IXP425_ICPR_OFFSET)
-#define IXP425_ICMR IXP425_INTC_REG(IXP425_ICMR_OFFSET)
-#define IXP425_ICLR IXP425_INTC_REG(IXP425_ICLR_OFFSET)
-#define IXP425_ICIP IXP425_INTC_REG(IXP425_ICIP_OFFSET)
-#define IXP425_ICFP IXP425_INTC_REG(IXP425_ICFP_OFFSET)
-#define IXP425_ICHR IXP425_INTC_REG(IXP425_ICHR_OFFSET)
-#define IXP425_ICIH IXP425_INTC_REG(IXP425_ICIH_OFFSET)
-#define IXP425_ICFH IXP425_INTC_REG(IXP425_ICFH_OFFSET)
-
-/*
- * Constants to make it easy to access GPIO registers
- */
-#define IXP425_GPIO_GPOUTR_OFFSET 0x00
-#define IXP425_GPIO_GPOER_OFFSET 0x04
-#define IXP425_GPIO_GPINR_OFFSET 0x08
-#define IXP425_GPIO_GPISR_OFFSET 0x0C
-#define IXP425_GPIO_GPIT1R_OFFSET 0x10
-#define IXP425_GPIO_GPIT2R_OFFSET 0x14
-#define IXP425_GPIO_GPCLKR_OFFSET 0x18
-#define IXP425_GPIO_GPDBSELR_OFFSET 0x1C
-
-/*
- * GPIO Register Definitions.
- * [Only perform 32bit reads/writes]
- */
-#define IXP425_GPIO_REG(x) ((volatile u32 *)(IXP425_GPIO_BASE_PHYS+(x)))
-
-#define IXP425_GPIO_GPOUTR IXP425_GPIO_REG(IXP425_GPIO_GPOUTR_OFFSET)
-#define IXP425_GPIO_GPOER IXP425_GPIO_REG(IXP425_GPIO_GPOER_OFFSET)
-#define IXP425_GPIO_GPINR IXP425_GPIO_REG(IXP425_GPIO_GPINR_OFFSET)
-#define IXP425_GPIO_GPISR IXP425_GPIO_REG(IXP425_GPIO_GPISR_OFFSET)
-#define IXP425_GPIO_GPIT1R IXP425_GPIO_REG(IXP425_GPIO_GPIT1R_OFFSET)
-#define IXP425_GPIO_GPIT2R IXP425_GPIO_REG(IXP425_GPIO_GPIT2R_OFFSET)
-#define IXP425_GPIO_GPCLKR IXP425_GPIO_REG(IXP425_GPIO_GPCLKR_OFFSET)
-#define IXP425_GPIO_GPDBSELR IXP425_GPIO_REG(IXP425_GPIO_GPDBSELR_OFFSET)
-
-#define IXP425_GPIO_GPITR(line) (((line) >= 8) ? \
- IXP425_GPIO_GPIT2R : IXP425_GPIO_GPIT1R)
-
-/*
- * Macros to make it easy to access the GPIO registers
- */
-#define GPIO_OUTPUT_ENABLE(line) *IXP425_GPIO_GPOER &= ~(1 << (line))
-#define GPIO_OUTPUT_DISABLE(line) *IXP425_GPIO_GPOER |= (1 << (line))
-#define GPIO_OUTPUT_SET(line) *IXP425_GPIO_GPOUTR |= (1 << (line))
-#define GPIO_OUTPUT_CLEAR(line) *IXP425_GPIO_GPOUTR &= ~(1 << (line))
-#define GPIO_INT_ACT_LOW_SET(line) \
- *IXP425_GPIO_GPITR(line) = \
- (*IXP425_GPIO_GPITR(line) & \
- ~(0x7 << (((line) & 0x7) * 3))) | \
- (0x1 << (((line) & 0x7) * 3)) \
-
-/*
- * Constants to make it easy to access Timer Control/Status registers
- */
-#define IXP425_OSTS_OFFSET 0x00 /* Continious TimeStamp */
-#define IXP425_OST1_OFFSET 0x04 /* Timer 1 Timestamp */
-#define IXP425_OSRT1_OFFSET 0x08 /* Timer 1 Reload */
-#define IXP425_OST2_OFFSET 0x0C /* Timer 2 Timestamp */
-#define IXP425_OSRT2_OFFSET 0x10 /* Timer 2 Reload */
-#define IXP425_OSWT_OFFSET 0x14 /* Watchdog Timer */
-#define IXP425_OSWE_OFFSET 0x18 /* Watchdog Enable */
-#define IXP425_OSWK_OFFSET 0x1C /* Watchdog Key */
-#define IXP425_OSST_OFFSET 0x20 /* Timer Status */
-
-/*
- * Operating System Timer Register Definitions.
- */
-
-#ifndef __ASSEMBLY__
-#define IXP425_TIMER_REG(x) ((volatile u32 *)(IXP425_TIMER_BASE_PHYS+(x)))
-#else
-#define IXP425_TIMER_REG(x) (IXP425_TIMER_BASE_PHYS+(x))
-#endif
-
-/* _B to avoid collision: also defined in npe/include/... */
-#define IXP425_OSTS_B IXP425_TIMER_REG(IXP425_OSTS_OFFSET)
-#define IXP425_OST1 IXP425_TIMER_REG(IXP425_OST1_OFFSET)
-#define IXP425_OSRT1 IXP425_TIMER_REG(IXP425_OSRT1_OFFSET)
-#define IXP425_OST2 IXP425_TIMER_REG(IXP425_OST2_OFFSET)
-#define IXP425_OSRT2 IXP425_TIMER_REG(IXP425_OSRT2_OFFSET)
-#define IXP425_OSWT IXP425_TIMER_REG(IXP425_OSWT_OFFSET)
-#define IXP425_OSWE IXP425_TIMER_REG(IXP425_OSWE_OFFSET)
-#define IXP425_OSWK IXP425_TIMER_REG(IXP425_OSWK_OFFSET)
-#define IXP425_OSST IXP425_TIMER_REG(IXP425_OSST_OFFSET)
-
-/*
- * Timer register values and bit definitions
- */
-#define IXP425_OST_ENABLE BIT(0)
-#define IXP425_OST_ONE_SHOT BIT(1)
-/* Low order bits of reload value ignored */
-#define IXP425_OST_RELOAD_MASK (0x3)
-#define IXP425_OST_DISABLED (0x0)
-#define IXP425_OSST_TIMER_1_PEND BIT(0)
-#define IXP425_OSST_TIMER_2_PEND BIT(1)
-#define IXP425_OSST_TIMER_TS_PEND BIT(2)
-#define IXP425_OSST_TIMER_WDOG_PEND BIT(3)
-#define IXP425_OSST_TIMER_WARM_RESET BIT(4)
-
-/*
- * Constants to make it easy to access PCI Control/Status registers
- */
-#define PCI_NP_AD_OFFSET 0x00
-#define PCI_NP_CBE_OFFSET 0x04
-#define PCI_NP_WDATA_OFFSET 0x08
-#define PCI_NP_RDATA_OFFSET 0x0c
-#define PCI_CRP_AD_CBE_OFFSET 0x10
-#define PCI_CRP_WDATA_OFFSET 0x14
-#define PCI_CRP_RDATA_OFFSET 0x18
-#define PCI_CSR_OFFSET 0x1c
-#define PCI_ISR_OFFSET 0x20
-#define PCI_INTEN_OFFSET 0x24
-#define PCI_DMACTRL_OFFSET 0x28
-#define PCI_AHBMEMBASE_OFFSET 0x2c
-#define PCI_AHBIOBASE_OFFSET 0x30
-#define PCI_PCIMEMBASE_OFFSET 0x34
-#define PCI_AHBDOORBELL_OFFSET 0x38
-#define PCI_PCIDOORBELL_OFFSET 0x3C
-#define PCI_ATPDMA0_AHBADDR_OFFSET 0x40
-#define PCI_ATPDMA0_PCIADDR_OFFSET 0x44
-#define PCI_ATPDMA0_LENADDR_OFFSET 0x48
-#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C
-#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50
-#define PCI_ATPDMA1_LENADDR_OFFSET 0x54
-
-/*
- * PCI Control/Status Registers
- */
-#define IXP425_PCI_CSR(x) ((volatile u32 *)(IXP425_PCI_CFG_BASE_PHYS+(x)))
-
-#define PCI_NP_AD IXP425_PCI_CSR(PCI_NP_AD_OFFSET)
-#define PCI_NP_CBE IXP425_PCI_CSR(PCI_NP_CBE_OFFSET)
-#define PCI_NP_WDATA IXP425_PCI_CSR(PCI_NP_WDATA_OFFSET)
-#define PCI_NP_RDATA IXP425_PCI_CSR(PCI_NP_RDATA_OFFSET)
-#define PCI_CRP_AD_CBE IXP425_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
-#define PCI_CRP_WDATA IXP425_PCI_CSR(PCI_CRP_WDATA_OFFSET)
-#define PCI_CRP_RDATA IXP425_PCI_CSR(PCI_CRP_RDATA_OFFSET)
-#define PCI_CSR IXP425_PCI_CSR(PCI_CSR_OFFSET)
-#define PCI_ISR IXP425_PCI_CSR(PCI_ISR_OFFSET)
-#define PCI_INTEN IXP425_PCI_CSR(PCI_INTEN_OFFSET)
-#define PCI_DMACTRL IXP425_PCI_CSR(PCI_DMACTRL_OFFSET)
-#define PCI_AHBMEMBASE IXP425_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
-#define PCI_AHBIOBASE IXP425_PCI_CSR(PCI_AHBIOBASE_OFFSET)
-#define PCI_PCIMEMBASE IXP425_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
-#define PCI_AHBDOORBELL IXP425_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
-#define PCI_PCIDOORBELL IXP425_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
-#define PCI_ATPDMA0_AHBADDR IXP425_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
-#define PCI_ATPDMA0_PCIADDR IXP425_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
-#define PCI_ATPDMA0_LENADDR IXP425_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
-#define PCI_ATPDMA1_AHBADDR IXP425_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
-#define PCI_ATPDMA1_PCIADDR IXP425_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
-#define PCI_ATPDMA1_LENADDR IXP425_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
-
-/*
- * PCI register values and bit definitions
- */
-
-/* CSR bit definitions */
-#define PCI_CSR_HOST BIT(0)
-#define PCI_CSR_ARBEN BIT(1)
-#define PCI_CSR_ADS BIT(2)
-#define PCI_CSR_PDS BIT(3)
-#define PCI_CSR_ABE BIT(4)
-#define PCI_CSR_DBT BIT(5)
-#define PCI_CSR_ASE BIT(8)
-#define PCI_CSR_IC BIT(15)
-
-/* ISR (Interrupt status) Register bit definitions */
-#define PCI_ISR_PSE BIT(0)
-#define PCI_ISR_PFE BIT(1)
-#define PCI_ISR_PPE BIT(2)
-#define PCI_ISR_AHBE BIT(3)
-#define PCI_ISR_APDC BIT(4)
-#define PCI_ISR_PADC BIT(5)
-#define PCI_ISR_ADB BIT(6)
-#define PCI_ISR_PDB BIT(7)
-
-/* INTEN (Interrupt Enable) Register bit definitions */
-#define PCI_INTEN_PSE BIT(0)
-#define PCI_INTEN_PFE BIT(1)
-#define PCI_INTEN_PPE BIT(2)
-#define PCI_INTEN_AHBE BIT(3)
-#define PCI_INTEN_APDC BIT(4)
-#define PCI_INTEN_PADC BIT(5)
-#define PCI_INTEN_ADB BIT(6)
-#define PCI_INTEN_PDB BIT(7)
-
-/*
- * Shift value for byte enable on NP cmd/byte enable register
- */
-#define IXP425_PCI_NP_CBE_BESL 4
-
-/*
- * PCI commands supported by NP access unit
- */
-#define NP_CMD_IOREAD 0x2
-#define NP_CMD_IOWRITE 0x3
-#define NP_CMD_CONFIGREAD 0xa
-#define NP_CMD_CONFIGWRITE 0xb
-#define NP_CMD_MEMREAD 0x6
-#define NP_CMD_MEMWRITE 0x7
-
-#if 0
-#ifndef __ASSEMBLY__
-extern int ixp425_pci_read(u32 addr, u32 cmd, u32* data);
-extern int ixp425_pci_write(u32 addr, u32 cmd, u32 data);
-extern void ixp425_pci_init(void *);
-#endif
-#endif
-
-/*
- * Constants for CRP access into local config space
- */
-#define CRP_AD_CBE_BESL 20
-#define CRP_AD_CBE_WRITE BIT(16)
-
-/*
- * Clock Speed Definitions.
- */
-#define IXP425_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */
-
-
-#endif
diff --git a/arch/arm/include/asm/arch-ixp/ixp425pci.h b/arch/arm/include/asm/arch-ixp/ixp425pci.h
deleted file mode 100644
index f499883..0000000
--- a/arch/arm/include/asm/arch-ixp/ixp425pci.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * IXP PCI Init
- * (C) Copyright 2004 eslab.whut.edu.cn
- * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _IXP425PCI_H
-#define _IXP425PCI_H
-
-#define OK 0
-#define ERROR -1
-
-struct pci_controller;
-extern void pci_ixp_init(struct pci_controller *hose);
-
-/* Mask definitions*/
-#define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK 0x0000000f
-
-#define PCI_NP_CBE_BESL (4)
-#define PCI_NP_AD_FUNCSL (8)
-
-/*Register addressing definitions for PCI controller configuration
- and status registers*/
-
-#define PCI_CSR_BASE (0xC0000000)
-/*
-#define PCI_NP_AD_OFFSET (0x00)
-#define PCI_NP_CBE_OFFSET (0x04)
-#define PCI_NP_WDATA_OFFSET (0x08)
-#define PCI_NP_RDATA_OFFSET (0x0C)
-#define PCI_CRP_OFFSET (0x10)
-#define PCI_CRP_WDATA_OFFSET (0x14)
-#define PCI_CRP_RDATA_OFFSET (0x18)
-#define PCI_CSR_OFFSET (0x1C)
-#define PCI_ISR_OFFSET (0x20)
-#define PCI_INTEN_OFFSET (0x24)
-#define PCI_DMACTRL_OFFSET (0x28)
-#define PCI_AHBMEMBASE_OFFSET (0x2C)
-#define PCI_AHBIOBASE_OFFSET (0x30)
-#define PCI_PCIMEMBASE_OFFSET (0x34)
-#define PCI_AHBDOORBELL_OFFSET (0x38)
-#define PCI_PCIDOORBELL_OFFSET (0x3C)
-#define PCI_ATPDMA0_AHBADDR (0x40)
-#define PCI_ATPDMA0_PCIADDR (0x44)
-#define PCI_ATPDMA0_LENADDR (0x48)
-#define PCI_ATPDMA1_AHBADDR (0x4C)
-#define PCI_ATPDMA1_PCIADDR (0x50)
-#define PCI_ATPDMA1_LENADDR (0x54)
-#define PCI_PTADMA0_AHBADDR (0x58)
-#define PCI_PTADMA0_PCIADDR (0x5C)
-#define PCI_PTADMA0_LENADDR (0x60)
-#define PCI_PTADMA1_AHBADDR (0x64)
-#define PCI_PTADMA1_PCIADDR (0x68)
-#define PCI_PTADMA1_LENADDR (0x6C)
-*/
-/*Non prefetch registers bit definitions*/
-/*
-#define NP_CMD_INTACK (0x0)
-#define NP_CMD_SPECIAL (0x1)
-#define NP_CMD_IOREAD (0x2)
-#define NP_CMD_IOWRITE (0x3)
-#define NP_CMD_MEMREAD (0x6)
-#define NP_CMD_MEMWRITE (0x7)
-#define NP_CMD_CONFIGREAD (0xa)
-#define NP_CMD_CONFIGWRITE (0xb)
-*/
-
-/*Configuration Port register bit definitions*/
-#define PCI_CRP_WRITE BIT(16)
-
-/*ISR (Interrupt status) Register bit definitions*/
-#define PCI_ISR_PSE BIT(0)
-#define PCI_ISR_PFE BIT(1)
-#define PCI_ISR_PPE BIT(2)
-#define PCI_ISR_AHBE BIT(3)
-#define PCI_ISR_APDC BIT(4)
-#define PCI_ISR_PADC BIT(5)
-#define PCI_ISR_ADB BIT(6)
-#define PCI_ISR_PDB BIT(7)
-
-/*INTEN (Interrupt Enable) Register bit definitions*/
-#define PCI_INTEN_PSE BIT(0)
-#define PCI_INTEN_PFE BIT(1)
-#define PCI_INTEN_PPE BIT(2)
-#define PCI_INTEN_AHBE BIT(3)
-#define PCI_INTEN_APDC BIT(4)
-#define PCI_INTEN_PADC BIT(5)
-#define PCI_INTEN_ADB BIT(6)
-#define PCI_INTEN_PDB BIT(7)
-
-/*PCI configuration regs.*/
-
-#define PCI_CFG_VENDOR_ID 0x00
-#define PCI_CFG_DEVICE_ID 0x02
-#define PCI_CFG_COMMAND 0x04
-#define PCI_CFG_STATUS 0x06
-#define PCI_CFG_REVISION 0x08
-#define PCI_CFG_PROGRAMMING_IF 0x09
-#define PCI_CFG_SUBCLASS 0x0a
-#define PCI_CFG_CLASS 0x0b
-#define PCI_CFG_CACHE_LINE_SIZE 0x0c
-#define PCI_CFG_LATENCY_TIMER 0x0d
-#define PCI_CFG_HEADER_TYPE 0x0e
-#define PCI_CFG_BIST 0x0f
-#define PCI_CFG_BASE_ADDRESS_0 0x10
-#define PCI_CFG_BASE_ADDRESS_1 0x14
-#define PCI_CFG_BASE_ADDRESS_2 0x18
-#define PCI_CFG_BASE_ADDRESS_3 0x1c
-#define PCI_CFG_BASE_ADDRESS_4 0x20
-#define PCI_CFG_BASE_ADDRESS_5 0x24
-#define PCI_CFG_CIS 0x28
-#define PCI_CFG_SUB_VENDOR_ID 0x2c
-#define PCI_CFG_SUB_SYSTEM_ID 0x2e
-#define PCI_CFG_EXPANSION_ROM 0x30
-#define PCI_CFG_RESERVED_0 0x34
-#define PCI_CFG_RESERVED_1 0x38
-#define PCI_CFG_DEV_INT_LINE 0x3c
-#define PCI_CFG_DEV_INT_PIN 0x3d
-#define PCI_CFG_MIN_GRANT 0x3e
-#define PCI_CFG_MAX_LATENCY 0x3f
-#define PCI_CFG_SPECIAL_USE 0x41
-#define PCI_CFG_MODE 0x43
-
-#define PCI_CMD_IO_ENABLE 0x0001 /* IO access enable */
-#define PCI_CMD_MEM_ENABLE 0x0002 /* memory access enable */
-#define PCI_CMD_MASTER_ENABLE 0x0004 /* bus master enable */
-#define PCI_CMD_MON_ENABLE 0x0008 /* monitor special cycles enable */
-#define PCI_CMD_WI_ENABLE 0x0010 /* write and invalidate enable */
-#define PCI_CMD_SNOOP_ENABLE 0x0020 /* palette snoop enable */
-#define PCI_CMD_PERR_ENABLE 0x0040 /* parity error enable */
-#define PCI_CMD_WC_ENABLE 0x0080 /* wait cycle enable */
-#define PCI_CMD_SERR_ENABLE 0x0100 /* system error enable */
-#define PCI_CMD_FBTB_ENABLE 0x0200 /* fast back to back enable */
-
-
-/*CSR Register bit definitions*/
-#define PCI_CSR_HOST BIT(0)
-#define PCI_CSR_ARBEN BIT(1)
-#define PCI_CSR_ADS BIT(2)
-#define PCI_CSR_PDS BIT(3)
-#define PCI_CSR_ABE BIT(4)
-#define PCI_CSR_DBT BIT(5)
-#define PCI_CSR_ASE BIT(8)
-#define PCI_CSR_IC BIT(15)
-
-/*Configuration command bit definitions*/
-#define PCI_CFG_CMD_IOAE BIT(0)
-#define PCI_CFG_CMD_MAE BIT(1)
-#define PCI_CFG_CMD_BME BIT(2)
-#define PCI_CFG_CMD_MWIE BIT(4)
-#define PCI_CFG_CMD_SER BIT(8)
-#define PCI_CFG_CMD_FBBE BIT(9)
-#define PCI_CFG_CMD_MDPE BIT(24)
-#define PCI_CFG_CMD_STA BIT(27)
-#define PCI_CFG_CMD_RTA BIT(28)
-#define PCI_CFG_CMD_RMA BIT(29)
-#define PCI_CFG_CMD_SSE BIT(30)
-#define PCI_CFG_CMD_DPE BIT(31)
-
-/*DMACTRL DMA Control and status Register*/
-#define PCI_DMACTRL_APDCEN BIT(0)
-#define PCI_DMACTRL_APDC0 BIT(4)
-#define PCI_DMACTRL_APDE0 BIT(5)
-#define PCI_DMACTRL_APDC1 BIT(6)
-#define PCI_DMACTRL_APDE1 BIT(7)
-#define PCI_DMACTRL_PADCEN BIT(8)
-#define PCI_DMACTRL_PADC0 BIT(12)
-#define PCI_DMACTRL_PADE0 BIT(13)
-#define PCI_DMACTRL_PADC1 BIT(14)
-#define PCI_DMACTRL_PADE1 BIT(15)
-
-#endif
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 60e8726..63e4ad5 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -32,9 +32,6 @@ struct arch_global_data {
unsigned long tbl;
unsigned long lastinc;
unsigned long long timer_reset_value;
-#ifdef CONFIG_IXP425
- unsigned long timestamp;
-#endif
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
unsigned long tlb_addr;
unsigned long tlb_size;
--
cgit v1.1
From 34991bbf471bb126988e611596a163135852d3c4 Mon Sep 17 00:00:00 2001
From: Piotr Wilczek
Date: Wed, 22 Jan 2014 15:54:30 +0100
Subject: arm:exynos: add cpu revision
This patch enables to read cpu revision on Exynos CPU.
Signed-off-by: Piotr Wilczek
Signed-off-by: Kyungmin Park
Signed-off-by: Minkyu Kang
---
arch/arm/include/asm/arch-exynos/cpu.h | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
(limited to 'arch/arm')
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index 573f755..bccce63 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -185,9 +185,11 @@ static inline int s5p_get_cpu_rev(void)
static inline void s5p_set_cpu_id(void)
{
- unsigned int pro_id = (readl(EXYNOS4_PRO_ID) & 0x00FFF000) >> 12;
+ unsigned int pro_id = readl(EXYNOS4_PRO_ID);
+ unsigned int cpu_id = (pro_id & 0x00FFF000) >> 12;
+ unsigned int cpu_rev = pro_id & 0x000000FF;
- switch (pro_id) {
+ switch (cpu_id) {
case 0x200:
/* Exynos4210 EVT0 */
s5p_cpu_id = 0x4210;
@@ -196,10 +198,12 @@ static inline void s5p_set_cpu_id(void)
case 0x210:
/* Exynos4210 EVT1 */
s5p_cpu_id = 0x4210;
+ s5p_cpu_rev = cpu_rev;
break;
case 0x412:
/* Exynos4412 */
s5p_cpu_id = 0x4412;
+ s5p_cpu_rev = cpu_rev;
break;
case 0x520:
/* Exynos5250 */
--
cgit v1.1
From d1cbf0a5ad8af65c8c1b9a0c848363de7ede91fe Mon Sep 17 00:00:00 2001
From: Piotr Wilczek
Date: Wed, 22 Jan 2014 15:54:31 +0100
Subject: arm:s5pc110: add cpu revision
This patch adds s5p_cpu_rev.
Signed-off-by: Piotr Wilczek
Signed-off-by: Kyungmin Park
Signed-off-by: Minkyu Kang
---
arch/arm/include/asm/arch-s5pc1xx/cpu.h | 7 +++++++
1 file changed, 7 insertions(+)
(limited to 'arch/arm')
diff --git a/arch/arm/include/asm/arch-s5pc1xx/cpu.h b/arch/arm/include/asm/arch-s5pc1xx/cpu.h
index 4fc5a0c..5ae5c87 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/cpu.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/cpu.h
@@ -51,10 +51,17 @@
#include
/* CPU detection macros */
extern unsigned int s5p_cpu_id;
+extern unsigned int s5p_cpu_rev;
+
+static inline int s5p_get_cpu_rev(void)
+{
+ return s5p_cpu_rev;
+}
static inline void s5p_set_cpu_id(void)
{
s5p_cpu_id = readl(S5PC100_PRO_ID);
+ s5p_cpu_rev = s5p_cpu_id & 0x000000FF;
s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12);
}
--
cgit v1.1
From d3e016cc28684cd32d826a9414a0e89ccf80861a Mon Sep 17 00:00:00 2001
From: Rajeshwari S Shinde
Date: Wed, 5 Feb 2014 10:48:15 +0530
Subject: MMC: DWMMC: Correct the CLKDIV register value
This patch corrects the divider value written to CLKDIV register.
Since SDCLKIN is divided inside controller by the DIVRATIO value set
in the CLKSEL register, we need to use the same output clock value to
calculate the CLKDIV value.
as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1)
Input parameter to mmc_clk is changed to dwmci_host, since
we need the same to read DWMCI_CLKSEL register.
This improves the read timing values for channel 0 on SMDK5250
from 0.288sec to 0.144sec
Signed-off-by: Rajeshwari S Shinde
Acked-by: Jaehoon Chung
Signed-off-by: Pantelis Antoniou
---
arch/arm/include/asm/arch-exynos/dwmmc.h | 4 ++++
1 file changed, 4 insertions(+)
(limited to 'arch/arm')
diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h
index 09d739d..a7ca12c 100644
--- a/arch/arm/include/asm/arch-exynos/dwmmc.h
+++ b/arch/arm/include/asm/arch-exynos/dwmmc.h
@@ -23,6 +23,10 @@
#define MPSCTRL_ENCRYPTION (0x1<<1)
#define MPSCTRL_VALID (0x1<<0)
+/* CLKSEL Register */
+#define DWMCI_DIVRATIO_BIT 24
+#define DWMCI_DIVRATIO_MASK 0x7
+
#ifdef CONFIG_OF_CONTROL
int exynos_dwmmc_init(const void *blob);
#endif
--
cgit v1.1
From 7dbe63bc950bbd12d021f72bf04104688cd324a9 Mon Sep 17 00:00:00 2001
From: Tom Rini
Date: Wed, 5 Feb 2014 10:24:18 -0500
Subject: SPL: Add CONFIG_SUPPORT_EMMC_BOOT support to CONFIG_SPL_FRAMEWORK
We use the switch CONFIG_SUPPORT_EMMC_BOOT today to enable some
additional features of the eMMC boot partitions. Add support for being
told that we have booted from one of these partitions to the spl
framework and implement this on TI OMAP/related.
Cc: Pantelis Antoniou
Signed-off-by: Tom Rini
Signed-off-by: Pantelis Antoniou
---
arch/arm/cpu/armv7/omap-common/boot-common.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
(limited to 'arch/arm')
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 69fff32..52e0f4a 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -66,7 +66,18 @@ u32 spl_boot_device(void)
u32 spl_boot_mode(void)
{
- return gd->arch.omap_boot_params.omap_bootmode;
+ u32 val = gd->arch.omap_boot_params.omap_bootmode;
+
+ if (val == MMCSD_MODE_RAW)
+ return MMCSD_MODE_RAW;
+ else if (val == MMCSD_MODE_FAT)
+ return MMCSD_MODE_FAT;
+ else
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+ return MMCSD_MODE_EMMCBOOT;
+#else
+ return MMCSD_MODE_UNDEFINED;
+#endif
}
void spl_board_init(void)
--
cgit v1.1
From 3cb007a9f298ff632ea37d86441da238f599dfbe Mon Sep 17 00:00:00 2001
From: Inha Song
Date: Thu, 6 Feb 2014 14:20:10 +0900
Subject: exynos: clock: fixed that cfg is set to wrong value.
This patch fixed that cfg value is set to wrong value.
Because it didn't read the related register.
Signed-off-by: Inha Song
Signed-off-by: Jaehoon Chung
Signed-off-by: Minkyu Kang
---
arch/arm/cpu/armv7/exynos/clock.c | 3 +++
1 file changed, 3 insertions(+)
(limited to 'arch/arm')
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 6807ff3..61cd8cf 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -1114,6 +1114,7 @@ void exynos4_set_lcd_clk(void)
* MIPI0_PRE_RATIO [23:20]
* set fimd ratio
*/
+ cfg = readl(&clk->div_lcd0);
cfg &= ~(0xf);
cfg |= 0x1;
writel(cfg, &clk->div_lcd0);
@@ -1176,6 +1177,7 @@ void exynos5_set_lcd_clk(void)
* MIPI0_PRE_RATIO [23:20]
* set fimd ratio
*/
+ cfg = readl(&clk->div_disp1_0);
cfg &= ~(0xf);
cfg |= 0x0;
writel(cfg, &clk->div_disp1_0);
@@ -1236,6 +1238,7 @@ void exynos4_set_mipi_clk(void)
* MIPI0_PRE_RATIO [23:20]
* set mipi ratio
*/
+ cfg = readl(&clk->div_lcd0);
cfg &= ~(0xf << 16);
cfg |= (0x1 << 16);
writel(cfg, &clk->div_lcd0);
--
cgit v1.1
From e25bfecf7ba54a5b56cf991af8a2f2bb22994293 Mon Sep 17 00:00:00 2001
From: Inha Song
Date: Thu, 6 Feb 2014 14:20:12 +0900
Subject: exynos: clock: use the clear and set bits macros.
Use setbits/clrbits macro instead of readl/writel function.
(Suggested by Wolfgang)
Signed-off-by: Inha Song
Signed-off-by: Jaehoon Chung
Signed-off-by: Minkyu Kang
---
arch/arm/cpu/armv7/exynos/clock.c | 85 +++++++++------------------------------
1 file changed, 20 insertions(+), 65 deletions(-)
(limited to 'arch/arm')
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 61cd8cf..1fea4d6 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -870,7 +870,6 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
unsigned int addr;
- unsigned int val;
/*
* CLK_DIV_FSYS1
@@ -890,10 +889,8 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
dev_index -= 2;
}
- val = readl(addr);
- val &= ~(0xff << ((dev_index << 4) + 8));
- val |= (div & 0xff) << ((dev_index << 4) + 8);
- writel(val, addr);
+ clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
+ (div & 0xff) << ((dev_index << 4) + 8));
}
/* exynos4x12: set the mmc clock */
@@ -902,7 +899,6 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
struct exynos4x12_clock *clk =
(struct exynos4x12_clock *)samsung_get_base_clock();
unsigned int addr;
- unsigned int val;
/*
* CLK_DIV_FSYS1
@@ -917,10 +913,8 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
dev_index -= 2;
}
- val = readl(addr);
- val &= ~(0xff << ((dev_index << 4) + 8));
- val |= (div & 0xff) << ((dev_index << 4) + 8);
- writel(val, addr);
+ clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
+ (div & 0xff) << ((dev_index << 4) + 8));
}
/* exynos5: set the mmc clock */
@@ -929,7 +923,6 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
unsigned int addr;
- unsigned int val;
/*
* CLK_DIV_FSYS1
@@ -944,10 +937,8 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
dev_index -= 2;
}
- val = readl(addr);
- val &= ~(0xff << ((dev_index << 4) + 8));
- val |= (div & 0xff) << ((dev_index << 4) + 8);
- writel(val, addr);
+ clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
+ (div & 0xff) << ((dev_index << 4) + 8));
}
/* exynos5: set the mmc clock */
@@ -956,7 +947,7 @@ static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
struct exynos5420_clock *clk =
(struct exynos5420_clock *)samsung_get_base_clock();
unsigned int addr;
- unsigned int val, shift;
+ unsigned int shift;
/*
* CLK_DIV_FSYS1
@@ -967,10 +958,7 @@ static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
addr = (unsigned int)&clk->div_fsys1;
shift = dev_index * 10;
- val = readl(addr);
- val &= ~(0x3ff << shift);
- val |= (div & 0x3ff) << shift;
- writel(val, addr);
+ clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift);
}
/* get_lcd_clk: return lcd clock frequency */
@@ -1061,7 +1049,6 @@ void exynos4_set_lcd_clk(void)
{
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
- unsigned int cfg = 0;
/*
* CLK_GATE_BLOCK
@@ -1073,9 +1060,7 @@ void exynos4_set_lcd_clk(void)
* CLK_LCD1 [5]
* CLK_GPS [7]
*/
- cfg = readl(&clk->gate_block);
- cfg |= 1 << 4;
- writel(cfg, &clk->gate_block);
+ setbits_le32(&clk->gate_block, 1 << 4);
/*
* CLK_SRC_LCD0
@@ -1085,10 +1070,7 @@ void exynos4_set_lcd_clk(void)
* MIPI0_SEL [12:15]
* set lcd0 src clock 0x6: SCLK_MPLL
*/
- cfg = readl(&clk->src_lcd0);
- cfg &= ~(0xf);
- cfg |= 0x6;
- writel(cfg, &clk->src_lcd0);
+ clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6);
/*
* CLK_GATE_IP_LCD0
@@ -1100,9 +1082,7 @@ void exynos4_set_lcd_clk(void)
* CLK_PPMULCD0 [5]
* Gating all clocks for FIMD0
*/
- cfg = readl(&clk->gate_ip_lcd0);
- cfg |= 1 << 0;
- writel(cfg, &clk->gate_ip_lcd0);
+ setbits_le32(&clk->gate_ip_lcd0, 1 << 0);
/*
* CLK_DIV_LCD0
@@ -1114,17 +1094,13 @@ void exynos4_set_lcd_clk(void)
* MIPI0_PRE_RATIO [23:20]
* set fimd ratio
*/
- cfg = readl(&clk->div_lcd0);
- cfg &= ~(0xf);
- cfg |= 0x1;
- writel(cfg, &clk->div_lcd0);
+ clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1);
}
void exynos5_set_lcd_clk(void)
{
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
- unsigned int cfg = 0;
/*
* CLK_GATE_BLOCK
@@ -1136,9 +1112,7 @@ void exynos5_set_lcd_clk(void)
* CLK_LCD1 [5]
* CLK_GPS [7]
*/
- cfg = readl(&clk->gate_block);
- cfg |= 1 << 4;
- writel(cfg, &clk->gate_block);
+ setbits_le32(&clk->gate_block, 1 << 4);
/*
* CLK_SRC_LCD0
@@ -1148,10 +1122,7 @@ void exynos5_set_lcd_clk(void)
* MIPI0_SEL [12:15]
* set lcd0 src clock 0x6: SCLK_MPLL
*/
- cfg = readl(&clk->src_disp1_0);
- cfg &= ~(0xf);
- cfg |= 0x6;
- writel(cfg, &clk->src_disp1_0);
+ clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6);
/*
* CLK_GATE_IP_LCD0
@@ -1163,9 +1134,7 @@ void exynos5_set_lcd_clk(void)
* CLK_PPMULCD0 [5]
* Gating all clocks for FIMD0
*/
- cfg = readl(&clk->gate_ip_disp1);
- cfg |= 1 << 0;
- writel(cfg, &clk->gate_ip_disp1);
+ setbits_le32(&clk->gate_ip_disp1, 1 << 0);
/*
* CLK_DIV_LCD0
@@ -1177,17 +1146,13 @@ void exynos5_set_lcd_clk(void)
* MIPI0_PRE_RATIO [23:20]
* set fimd ratio
*/
- cfg = readl(&clk->div_disp1_0);
- cfg &= ~(0xf);
- cfg |= 0x0;
- writel(cfg, &clk->div_disp1_0);
+ clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
}
void exynos4_set_mipi_clk(void)
{
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
- unsigned int cfg = 0;
/*
* CLK_SRC_LCD0
@@ -1197,10 +1162,7 @@ void exynos4_set_mipi_clk(void)
* MIPI0_SEL [12:15]
* set mipi0 src clock 0x6: SCLK_MPLL
*/
- cfg = readl(&clk->src_lcd0);
- cfg &= ~(0xf << 12);
- cfg |= (0x6 << 12);
- writel(cfg, &clk->src_lcd0);
+ clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12);
/*
* CLK_SRC_MASK_LCD0
@@ -1210,9 +1172,7 @@ void exynos4_set_mipi_clk(void)
* MIPI0_MASK [12]
* set src mask mipi0 0x1: Unmask
*/
- cfg = readl(&clk->src_mask_lcd0);
- cfg |= (0x1 << 12);
- writel(cfg, &clk->src_mask_lcd0);
+ setbits_le32(&clk->src_mask_lcd0, 0x1 << 12);
/*
* CLK_GATE_IP_LCD0
@@ -1224,9 +1184,7 @@ void exynos4_set_mipi_clk(void)
* CLK_PPMULCD0 [5]
* Gating all clocks for MIPI0
*/
- cfg = readl(&clk->gate_ip_lcd0);
- cfg |= 1 << 3;
- writel(cfg, &clk->gate_ip_lcd0);
+ setbits_le32(&clk->gate_ip_lcd0, 1 << 3);
/*
* CLK_DIV_LCD0
@@ -1238,10 +1196,7 @@ void exynos4_set_mipi_clk(void)
* MIPI0_PRE_RATIO [23:20]
* set mipi ratio
*/
- cfg = readl(&clk->div_lcd0);
- cfg &= ~(0xf << 16);
- cfg |= (0x1 << 16);
- writel(cfg, &clk->div_lcd0);
+ clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16);
}
/*
--
cgit v1.1
From 3cd534e4552770c1a8282c94832777a9ede75260 Mon Sep 17 00:00:00 2001
From: Stephen Warren
Date: Tue, 28 Jan 2014 22:42:06 -0700
Subject: ARM: bcm2835: config.mk isn't needed
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The entries in config.mk were needed so that U-Boot could be built
with an old version of the Raspberry Pi Foundation's toolchain. Without
them, the build would error out with:
...-ld: error: .../libgcc.a(_bswapsi2.o) uses VFP register arguments,
u-boot does not
However, none of the 3 toolchains in the latest version of their
tools.git, nor the Ubuntu/Linaro ARM compilers in at least Ubuntu Quantal
or Saucy, need these options set in order to compile a working U-Boot.
Hence, remove the options for simplicity.
Reported-by: Tom Rini
Signed-off-by: Stephen Warren
Reviewed-by: Andreas Färber
---
arch/arm/cpu/arm1176/bcm2835/config.mk | 19 -------------------
1 file changed, 19 deletions(-)
delete mode 100644 arch/arm/cpu/arm1176/bcm2835/config.mk
(limited to 'arch/arm')
diff --git a/arch/arm/cpu/arm1176/bcm2835/config.mk b/arch/arm/cpu/arm1176/bcm2835/config.mk
deleted file mode 100644
index b87ce24..0000000
--- a/arch/arm/cpu/arm1176/bcm2835/config.mk
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# (C) Copyright 2012 Stephen Warren
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# version 2 as published by the Free Software Foundation.
-#
-# This program is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-
-# Don't attempt to override the target CPU/ABI options;
-# the Raspberry Pi toolchain does the right thing by default.
-PLATFORM_RELFLAGS := $(filter-out -msoft-float,$(PLATFORM_RELFLAGS))
-PLATFORM_CPPFLAGS := $(filter-out -march=armv5t,$(PLATFORM_CPPFLAGS))
--
cgit v1.1
From 38716189d439c3ed8707e7bc1f430322ba7a810d Mon Sep 17 00:00:00 2001
From: Michal Simek
Date: Wed, 5 Feb 2014 08:06:29 +0100
Subject: zynq: Fix elf header generation
This patch is here because of:
"arm: keep all sections in ELF file"
(sha1: 47ed5dd031d7d2c587e6afd386e79ccec1a1b7f7)
Our tools expect to have elf with only LOAD header.
Without this fix also PHDR, INTERP and DYNAMIC headers
are available in ELF.
Signed-off-by: Michal Simek
---
arch/arm/cpu/armv7/zynq/u-boot.lds | 99 ++++++++++++++++++++++++++++++++++++++
1 file changed, 99 insertions(+)
create mode 100644 arch/arm/cpu/armv7/zynq/u-boot.lds
(limited to 'arch/arm')
diff --git a/arch/arm/cpu/armv7/zynq/u-boot.lds b/arch/arm/cpu/armv7/zynq/u-boot.lds
new file mode 100644
index 0000000..a68b050
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/u-boot.lds
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering,
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.__image_copy_start)
+ CPUDIR/start.o (.text*)
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(4);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = ALIGN(4);
+
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
+ }
+
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ }
+
+ .rel.dyn : {
+ *(.rel*)
+ }
+
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
+ }
+
+ _end = .;
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+ .bss_start __rel_dyn_start (OVERLAY) : {
+ KEEP(*(.__bss_start));
+ __bss_base = .;
+ }
+
+ .bss __bss_base (OVERLAY) : {
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_limit = .;
+ }
+
+ .bss_end __bss_limit (OVERLAY) : {
+ KEEP(*(.__bss_end));
+ }
+
+ /*
+ * Zynq needs to discard more sections because the user
+ * is expected to pass this image on to tools for boot.bin
+ * generation that require them to be dropped.
+ */
+ /DISCARD/ : { *(.dynsym) }
+ /DISCARD/ : { *(.dynbss*) }
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+ /DISCARD/ : { *(.ARM.exidx*) }
+ /DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
+}
--
cgit v1.1
From 5e77a745b24d9b98aa635293972f04fd6f0c6b38 Mon Sep 17 00:00:00 2001
From: Stephen Warren
Date: Wed, 5 Feb 2014 20:42:25 -0700
Subject: ARM: bcm2835: fix mbox POWER_STATE_RESP_ON value
Typo: The correct value is 1 not 2.
Signed-off-by: Stephen Warren
---
arch/arm/include/asm/arch-bcm2835/mbox.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm')
diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h
index 38cb42a..dded857 100644
--- a/arch/arm/include/asm/arch-bcm2835/mbox.h
+++ b/arch/arm/include/asm/arch-bcm2835/mbox.h
@@ -143,7 +143,7 @@ struct bcm2835_mbox_tag_get_arm_mem {
#define BCM2835_MBOX_POWER_DEVID_SPI 7
#define BCM2835_MBOX_POWER_DEVID_CCP2TX 8
-#define BCM2835_MBOX_POWER_STATE_RESP_ON (1 << 1)
+#define BCM2835_MBOX_POWER_STATE_RESP_ON (1 << 0)
/* Device doesn't exist */
#define BCM2835_MBOX_POWER_STATE_RESP_NODEV (1 << 1)
--
cgit v1.1
From d7cbcc762ea88ad20e9005a85bf7d55939b5e9d2 Mon Sep 17 00:00:00 2001
From: Markus Niebel
Date: Mon, 17 Feb 2014 17:33:16 +0100
Subject: spi: spi-mxc: add defines for clk inactive state for ECSPI
Provide define for the SCLK_CTL field of the config reg of ECSPI.
While at it, oder the defines to improve readability and make
adding more defines easier.
Signed-off-by: Markus Niebel
Reviewed-by: Jagannadha Sutradharudu Teki
---
arch/arm/include/asm/arch-mx5/imx-regs.h | 7 ++++---
arch/arm/include/asm/arch-mx6/imx-regs.h | 7 ++++---
2 files changed, 8 insertions(+), 6 deletions(-)
(limited to 'arch/arm')
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 4955ccf..054c680 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -230,9 +230,10 @@
#define MXC_CSPICTRL_CHAN 18
/* Bit position inside CON register to be associated with SS */
-#define MXC_CSPICON_POL 4
-#define MXC_CSPICON_PHA 0
-#define MXC_CSPICON_SSPOL 12
+#define MXC_CSPICON_PHA 0 /* SCLK phase control */
+#define MXC_CSPICON_POL 4 /* SCLK polarity */
+#define MXC_CSPICON_SSPOL 12 /* SS polarity */
+#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
#define MXC_SPI_BASE_ADDRESSES \
CSPI1_BASE_ADDR, \
CSPI2_BASE_ADDR, \
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index f2ad6e9..3c58c01 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -405,9 +405,10 @@ struct cspi_regs {
#define MXC_CSPICTRL_CHAN 18
/* Bit position inside CON register to be associated with SS */
-#define MXC_CSPICON_POL 4
-#define MXC_CSPICON_PHA 0
-#define MXC_CSPICON_SSPOL 12
+#define MXC_CSPICON_PHA 0 /* SCLK phase control */
+#define MXC_CSPICON_POL 4 /* SCLK polarity */
+#define MXC_CSPICON_SSPOL 12 /* SS polarity */
+#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
#ifdef CONFIG_MX6SL
#define MXC_SPI_BASE_ADDRESSES \
ECSPI1_BASE_ADDR, \
--
cgit v1.1
From 060aaada06ffdcd21c01180a07779551448d13ff Mon Sep 17 00:00:00 2001
From: Markus Niebel
Date: Mon, 17 Feb 2014 17:33:18 +0100
Subject: spi: mxc_spi: i.MX6 DL/S have only 4 eCSPI controller
The dual lite and solo variant have only 4 SPI controller.
respect this in the MXC_SPI_BASE_ADRESSES macro
Signed-off-by: Markus Niebel
Reviewed-by: Jagannadha Sutradharudu Teki
---
arch/arm/include/asm/arch-mx6/imx-regs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
(limited to 'arch/arm')
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 3c58c01..26f2a88 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -409,7 +409,7 @@ struct cspi_regs {
#define MXC_CSPICON_POL 4 /* SCLK polarity */
#define MXC_CSPICON_SSPOL 12 /* SS polarity */
#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
-#ifdef CONFIG_MX6SL
+#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL)
#define MXC_SPI_BASE_ADDRESSES \
ECSPI1_BASE_ADDR, \
ECSPI2_BASE_ADDR, \
--
cgit v1.1
From b56e71e2d41f4921ba69531978d4857bbd9366fa Mon Sep 17 00:00:00 2001
From: Sourav Poddar
Date: Sat, 21 Dec 2013 12:50:12 +0530
Subject: am43xx: Add qspi support
Add QSPI definitions and clock configuration support.
Signed-off-by: Sourav Poddar
Reviewed-by: Jagannadha Sutradharudu Teki