From 0eccec4ef1431aafb8d67118c515703e6a7f7a3e Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 7 Jan 2015 15:08:43 +0100 Subject: sunxi: Move usb-controller init code out of ehci-sunxi.c for reuse for otg Most of the usb-controller init code found in ehci-sunxi.c also is necessary to init the otg usb controller, so move it to a common place. While at it also update various #ifdefs / defines for sun8i support. Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- arch/arm/cpu/armv7/sunxi/Makefile | 1 + arch/arm/cpu/armv7/sunxi/usbc.c | 229 ++++++++++++++++++++++++++ arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 2 +- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 1 + arch/arm/include/asm/arch-sunxi/cpu.h | 4 +- arch/arm/include/asm/arch-sunxi/usbc.h | 20 +++ 6 files changed, 254 insertions(+), 3 deletions(-) create mode 100644 arch/arm/cpu/armv7/sunxi/usbc.c create mode 100644 arch/arm/include/asm/arch-sunxi/usbc.h (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index 1e89937..1720f7d 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -12,6 +12,7 @@ obj-y += board.o obj-y += clock.o obj-y += cpu_info.o obj-y += pinmux.o +obj-y += usbc.o obj-$(CONFIG_MACH_SUN6I) += prcm.o obj-$(CONFIG_MACH_SUN8I) += prcm.o obj-$(CONFIG_MACH_SUN6I) += p2wi.o diff --git a/arch/arm/cpu/armv7/sunxi/usbc.c b/arch/arm/cpu/armv7/sunxi/usbc.c new file mode 100644 index 0000000..621992c --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/usbc.c @@ -0,0 +1,229 @@ +/* + * Sunxi usb-controller code shared between the ehci and musb controllers + * + * Copyright (C) 2014 Roman Byshko + * + * Roman Byshko + * + * Based on code from + * Allwinner Technology Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#define SUNXI_USB_PMU_IRQ_ENABLE 0x800 +#define SUNXI_USB_CSR 0x404 +#define SUNXI_USB_PASSBY_EN 1 + +#define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10) +#define SUNXI_EHCI_AHB_INCR4_BURST_EN (1 << 9) +#define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8) +#define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0) + +static struct sunxi_usbc_hcd { + struct usb_hcd *hcd; + int usb_rst_mask; + int ahb_clk_mask; + int gpio_vbus; + int irq; + int id; +} sunxi_usbc_hcd[] = { + { + .usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK, + .ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0, +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I + .irq = 72, +#else + .irq = 39, +#endif + .id = 1, + }, +#if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1) + { + .usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK, + .ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI1, +#ifdef CONFIG_MACH_SUN6I + .irq = 74, +#else + .irq = 40, +#endif + .id = 2, + } +#endif +}; + +static int enabled_hcd_count; + +void *sunxi_usbc_get_io_base(int index) +{ + switch (index) { + case 0: + return (void *)SUNXI_USB0_BASE; + case 1: + return (void *)SUNXI_USB1_BASE; + case 2: + return (void *)SUNXI_USB2_BASE; + default: + return NULL; + } +} + +static int get_vbus_gpio(int index) +{ + switch (index) { + case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN); + case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN); + } + return -1; +} + +static void usb_phy_write(struct sunxi_usbc_hcd *sunxi_usbc, int addr, + int data, int len) +{ + int j = 0, usbc_bit = 0; + void *dest = sunxi_usbc_get_io_base(0) + SUNXI_USB_CSR; + + usbc_bit = 1 << (sunxi_usbc->id * 2); + for (j = 0; j < len; j++) { + /* set the bit address to be written */ + clrbits_le32(dest, 0xff << 8); + setbits_le32(dest, (addr + j) << 8); + + clrbits_le32(dest, usbc_bit); + /* set data bit */ + if (data & 0x1) + setbits_le32(dest, 1 << 7); + else + clrbits_le32(dest, 1 << 7); + + setbits_le32(dest, usbc_bit); + + clrbits_le32(dest, usbc_bit); + + data >>= 1; + } +} + +static void sunxi_usb_phy_init(struct sunxi_usbc_hcd *sunxi_usbc) +{ + /* The following comments are machine + * translated from Chinese, you have been warned! + */ + + /* adjust PHY's magnitude and rate */ + usb_phy_write(sunxi_usbc, 0x20, 0x14, 5); + + /* threshold adjustment disconnect */ +#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN6I + usb_phy_write(sunxi_usbc, 0x2a, 3, 2); +#else + usb_phy_write(sunxi_usbc, 0x2a, 2, 2); +#endif + + return; +} + +static void sunxi_usb_passby(struct sunxi_usbc_hcd *sunxi_usbc, int enable) +{ + unsigned long bits = 0; + void *addr = sunxi_usbc_get_io_base(sunxi_usbc->id) + + SUNXI_USB_PMU_IRQ_ENABLE; + + bits = SUNXI_EHCI_AHB_ICHR8_EN | + SUNXI_EHCI_AHB_INCR4_BURST_EN | + SUNXI_EHCI_AHB_INCRX_ALIGN_EN | + SUNXI_EHCI_ULPI_BYPASS_EN; + + if (enable) + setbits_le32(addr, bits); + else + clrbits_le32(addr, bits); + + return; +} + +int sunxi_usbc_request_resources(int index) +{ + struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index - 1]; + + sunxi_usbc->gpio_vbus = get_vbus_gpio(index); + if (sunxi_usbc->gpio_vbus != -1) + return gpio_request(sunxi_usbc->gpio_vbus, "usbc_vbus"); + + return 0; +} + +int sunxi_usbc_free_resources(int index) +{ + struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index - 1]; + + if (sunxi_usbc->gpio_vbus != -1) + return gpio_free(sunxi_usbc->gpio_vbus); + + return 0; +} + +void sunxi_usbc_enable(int index) +{ + struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index - 1]; + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* enable common PHY only once */ + if (enabled_hcd_count == 0) + setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE); + + setbits_le32(&ccm->usb_clk_cfg, sunxi_usbc->usb_rst_mask); + setbits_le32(&ccm->ahb_gate0, sunxi_usbc->ahb_clk_mask); +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I + setbits_le32(&ccm->ahb_reset0_cfg, sunxi_usbc->ahb_clk_mask); +#endif + + sunxi_usb_phy_init(sunxi_usbc); + + sunxi_usb_passby(sunxi_usbc, SUNXI_USB_PASSBY_EN); + + enabled_hcd_count++; +} + +void sunxi_usbc_disable(int index) +{ + struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index - 1]; + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + sunxi_usb_passby(sunxi_usbc, !SUNXI_USB_PASSBY_EN); + +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I + clrbits_le32(&ccm->ahb_reset0_cfg, sunxi_usbc->ahb_clk_mask); +#endif + clrbits_le32(&ccm->ahb_gate0, sunxi_usbc->ahb_clk_mask); + clrbits_le32(&ccm->usb_clk_cfg, sunxi_usbc->usb_rst_mask); + + /* disable common PHY only once, for the last enabled hcd */ + if (enabled_hcd_count == 1) + clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE); + + enabled_hcd_count--; +} + +void sunxi_usbc_vbus_enable(int index) +{ + struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index - 1]; + + if (sunxi_usbc->gpio_vbus != -1) + gpio_direction_output(sunxi_usbc->gpio_vbus, 1); +} + +void sunxi_usbc_vbus_disable(int index) +{ + struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index - 1]; + + if (sunxi_usbc->gpio_vbus != -1) + gpio_direction_output(sunxi_usbc->gpio_vbus, 0); +} diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index 70b789e..a6d129c 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -182,7 +182,7 @@ struct sunxi_ccm_reg { #define AHB_GATE_OFFSET_USB_EHCI1 3 #define AHB_GATE_OFFSET_USB_OHCI0 2 #define AHB_GATE_OFFSET_USB_EHCI0 1 -#define AHB_GATE_OFFSET_USB 0 +#define AHB_GATE_OFFSET_USB0 0 /* ahb clock gate bit offset (second register) */ #define AHB_GATE_OFFSET_GMAC 17 diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 653f63c..f85f94d 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -204,6 +204,7 @@ struct sunxi_ccm_reg { #define AHB_GATE_OFFSET_USB_OHCI0 29 #define AHB_GATE_OFFSET_USB_EHCI1 27 #define AHB_GATE_OFFSET_USB_EHCI0 26 +#define AHB_GATE_OFFSET_USB0 24 #define AHB_GATE_OFFSET_MCTL 14 #define AHB_GATE_OFFSET_GMAC 17 #define AHB_GATE_OFFSET_MMC3 11 diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h index bcfa00d..82b3d46 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu.h +++ b/arch/arm/include/asm/arch-sunxi/cpu.h @@ -37,7 +37,7 @@ #define SUNXI_MMC1_BASE 0x01c10000 #define SUNXI_MMC2_BASE 0x01c11000 #define SUNXI_MMC3_BASE 0x01c12000 -#ifndef CONFIG_MACH_SUN6I +#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I #define SUNXI_USB0_BASE 0x01c13000 #define SUNXI_USB1_BASE 0x01c14000 #endif @@ -45,7 +45,7 @@ #define SUNXI_HDMI_BASE 0x01c16000 #define SUNXI_SPI2_BASE 0x01c17000 #define SUNXI_SATA_BASE 0x01c18000 -#ifndef CONFIG_MACH_SUN6I +#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I #define SUNXI_PATA_BASE 0x01c19000 #define SUNXI_ACE_BASE 0x01c1a000 #define SUNXI_TVE1_BASE 0x01c1b000 diff --git a/arch/arm/include/asm/arch-sunxi/usbc.h b/arch/arm/include/asm/arch-sunxi/usbc.h new file mode 100644 index 0000000..8d20973 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/usbc.h @@ -0,0 +1,20 @@ +/* + * Sunxi usb-controller code shared between the ehci and musb controllers + * + * Copyright (C) 2014 Roman Byshko + * + * Roman Byshko + * + * Based on code from + * Allwinner Technology Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +void *sunxi_usbc_get_io_base(int index); +int sunxi_usbc_request_resources(int index); +int sunxi_usbc_free_resources(int index); +void sunxi_usbc_enable(int index); +void sunxi_usbc_disable(int index); +void sunxi_usbc_vbus_enable(int index); +void sunxi_usbc_vbus_disable(int index); -- cgit v1.1