From 8497ccc4c23beae38130489d85c97ae38058f20b Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 22 Sep 2015 00:27:34 +0900 Subject: ARM: uniphier: rename CONFIG_MACH_* to CONFIG_ARCH_UNIPHIER_* I want these prefixed with CONFIG_ARCH_UNIPHIER_ to clarify they belong to UniPhier SoC family. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/include/mach/sc-regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-uniphier/include/mach/sc-regs.h') diff --git a/arch/arm/mach-uniphier/include/mach/sc-regs.h b/arch/arm/mach-uniphier/include/mach/sc-regs.h index df50294..9d697b1 100644 --- a/arch/arm/mach-uniphier/include/mach/sc-regs.h +++ b/arch/arm/mach-uniphier/include/mach/sc-regs.h @@ -9,7 +9,7 @@ #ifndef ARCH_SC_REGS_H #define ARCH_SC_REGS_H -#if defined(CONFIG_MACH_PH1_SLD3) +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) #define SC_BASE_ADDR 0xf1840000 #else #define SC_BASE_ADDR 0x61840000 -- cgit v1.1 From 28f40d4a4db2b6c701d349fd4fac286d21369de2 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 22 Sep 2015 00:27:40 +0900 Subject: ARM: uniphier: add PH1-Pro5 support The DDR SDRAM initialization code has not been mainlined yet, but U-Boot proper should work. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/include/mach/sc-regs.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm/mach-uniphier/include/mach/sc-regs.h') diff --git a/arch/arm/mach-uniphier/include/mach/sc-regs.h b/arch/arm/mach-uniphier/include/mach/sc-regs.h index 9d697b1..903e405 100644 --- a/arch/arm/mach-uniphier/include/mach/sc-regs.h +++ b/arch/arm/mach-uniphier/include/mach/sc-regs.h @@ -15,6 +15,10 @@ #define SC_BASE_ADDR 0x61840000 #endif +#define SC_DPLLOSCCTRL (SC_BASE_ADDR | 0x1110) +#define SC_DPLLOSCCTRL_DPLLST (0x1 << 1) +#define SC_DPLLOSCCTRL_DPLLEN (0x1 << 0) + #define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200) #define SC_DPLLCTRL_SSC_EN (0x1 << 31) #define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16) @@ -43,6 +47,7 @@ #define SC_RSTCTRL_NRST_ETHER (0x1 << 12) #define SC_RSTCTRL_NRST_STDMAC (0x1 << 10) #define SC_RSTCTRL_NRST_GIO (0x1 << 6) +/* Pro4 or older */ #define SC_RSTCTRL_NRST_UMC1 (0x1 << 5) #define SC_RSTCTRL_NRST_UMC0 (0x1 << 4) #define SC_RSTCTRL_NRST_NAND (0x1 << 2) @@ -53,6 +58,15 @@ #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) +/* Pro5 or newer */ +#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c) +#define SC_RSTCTRL4_NRST_UMCSB (0x1 << 12) /* UMC system bus */ +#define SC_RSTCTRL4_NRST_UMCA2 (0x1 << 10) /* UMC ch2 standby */ +#define SC_RSTCTRL4_NRST_UMCA1 (0x1 << 9) /* UMC ch1 standby */ +#define SC_RSTCTRL4_NRST_UMCA0 (0x1 << 8) /* UMC ch0 standby */ +#define SC_RSTCTRL4_NRST_UMC31 (0x1 << 5) /* UMC ch1 */ +#define SC_RSTCTRL4_NRST_UMC30 (0x1 << 4) /* UMC ch0 */ + #define SC_CLKCTRL (SC_BASE_ADDR | 0x2104) #define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */ #define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */ @@ -60,11 +74,18 @@ #define SC_CLKCTRL_CEN_MIO (0x1 << 11) #define SC_CLKCTRL_CEN_STDMAC (0x1 << 10) #define SC_CLKCTRL_CEN_GIO (0x1 << 6) +/* Pro4 or older */ #define SC_CLKCTRL_CEN_UMC (0x1 << 4) #define SC_CLKCTRL_CEN_NAND (0x1 << 2) #define SC_CLKCTRL_CEN_SBC (0x1 << 1) #define SC_CLKCTRL_CEN_PERI (0x1 << 0) +/* Pro5 or newer */ +#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c) +#define SC_CLKCTRL4_CEN_UMCSB (0x1 << 12) /* UMC system bus */ +#define SC_CLKCTRL4_CEN_UMC1 (0x1 << 1) /* UMC ch1 */ +#define SC_CLKCTRL4_CEN_UMC0 (0x1 << 0) /* UMC ch0 */ + /* System reset control register */ #define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000) #define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010) -- cgit v1.1 From 019df879a93e266ac19f5eb00e4ee605db279b14 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 22 Sep 2015 00:27:41 +0900 Subject: ARM: uniphier: add ProXstream2 and PH1-LD6b support The DDR SDRAM initialization code has not been mainlined yet, but U-Boot proper should work. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/include/mach/sc-regs.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/mach-uniphier/include/mach/sc-regs.h') diff --git a/arch/arm/mach-uniphier/include/mach/sc-regs.h b/arch/arm/mach-uniphier/include/mach/sc-regs.h index 903e405..474b82d 100644 --- a/arch/arm/mach-uniphier/include/mach/sc-regs.h +++ b/arch/arm/mach-uniphier/include/mach/sc-regs.h @@ -64,6 +64,7 @@ #define SC_RSTCTRL4_NRST_UMCA2 (0x1 << 10) /* UMC ch2 standby */ #define SC_RSTCTRL4_NRST_UMCA1 (0x1 << 9) /* UMC ch1 standby */ #define SC_RSTCTRL4_NRST_UMCA0 (0x1 << 8) /* UMC ch0 standby */ +#define SC_RSTCTRL4_NRST_UMC32 (0x1 << 6) /* UMC ch2 */ #define SC_RSTCTRL4_NRST_UMC31 (0x1 << 5) /* UMC ch1 */ #define SC_RSTCTRL4_NRST_UMC30 (0x1 << 4) /* UMC ch0 */ @@ -83,6 +84,7 @@ /* Pro5 or newer */ #define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c) #define SC_CLKCTRL4_CEN_UMCSB (0x1 << 12) /* UMC system bus */ +#define SC_CLKCTRL4_CEN_UMC2 (0x1 << 2) /* UMC ch2 */ #define SC_CLKCTRL4_CEN_UMC1 (0x1 << 1) /* UMC ch1 */ #define SC_CLKCTRL4_CEN_UMC0 (0x1 << 0) /* UMC ch0 */ -- cgit v1.1