From 784548efb2b76fdbfdb73f6a505a156f90bb1e55 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 14 Feb 2017 01:24:26 +0900 Subject: ARM: uniphier: rework spl_boot_device() and related code The current implementation has ugly switch statements here and there, and duplicates similar code. Rework it using table lookups for SoC data and reduce code duplication. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/clk/clk-ld11.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm/mach-uniphier/clk') diff --git a/arch/arm/mach-uniphier/clk/clk-ld11.c b/arch/arm/mach-uniphier/clk/clk-ld11.c index 58069cb..b1e82a1 100644 --- a/arch/arm/mach-uniphier/clk/clk-ld11.c +++ b/arch/arm/mach-uniphier/clk/clk-ld11.c @@ -9,7 +9,6 @@ #include #include -#include "../boot-mode/boot-device.h" #include "../init.h" #include "../sc64-regs.h" #include "../sg-regs.h" @@ -18,7 +17,7 @@ void uniphier_ld11_clk_init(void) { /* if booted from a device other than USB, without stand-by MPU */ if ((readl(SG_PINMON0) & BIT(27)) && - spl_boot_device_raw() != BOOT_DEVICE_USB) { + uniphier_boot_device_raw() != BOOT_DEVICE_USB) { writel(1, SG_ETPHYPSHUT); writel(1, SG_ETPHYCNT); -- cgit v1.1 From c21f58548c812032207d986ca7b5baa0bb4a5972 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 17 Feb 2017 16:17:22 +0900 Subject: ARM: uniphier: deassert RST_n of eMMC device for LD11/LD20 For LD11 and LD20 SoCs, the RST_n pin is asserted by default. If the EXT_CSD[162], bit[1:0] (RST_n_ENABLE) is fused, the eMMC device would stay in the reset state until its RST_n pin is deasserted by software. Currently, this is cared by an ad-hoc way because the eMMC hardware reset provider is not supported in U-Boot for now. This code should be re-written once the "mmc-pwrseq-emmc" binding is supported. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/clk/Makefile | 2 +- arch/arm/mach-uniphier/clk/clk-ld11.c | 5 +++++ arch/arm/mach-uniphier/clk/clk-ld20.c | 17 +++++++++++++++++ 3 files changed, 23 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-uniphier/clk/clk-ld20.c (limited to 'arch/arm/mach-uniphier/clk') diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile index 43df670..4134197 100644 --- a/arch/arm/mach-uniphier/clk/Makefile +++ b/arch/arm/mach-uniphier/clk/Makefile @@ -24,7 +24,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o pll-ld11.o -obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pll-ld20.o +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o pll-ld20.o obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += pll-pxs3.o endif diff --git a/arch/arm/mach-uniphier/clk/clk-ld11.c b/arch/arm/mach-uniphier/clk/clk-ld11.c index b1e82a1..a4dcde7 100644 --- a/arch/arm/mach-uniphier/clk/clk-ld11.c +++ b/arch/arm/mach-uniphier/clk/clk-ld11.c @@ -13,6 +13,8 @@ #include "../sc64-regs.h" #include "../sg-regs.h" +#define SDCTRL_EMMC_HW_RESET 0x59810280 + void uniphier_ld11_clk_init(void) { /* if booted from a device other than USB, without stand-by MPU */ @@ -28,6 +30,9 @@ void uniphier_ld11_clk_init(void) writel(7, SG_ETPHYCNT); } + /* TODO: use "mmc-pwrseq-emmc" */ + writel(1, SDCTRL_EMMC_HW_RESET); + #ifdef CONFIG_USB_EHCI { /* FIXME: the current clk driver can not handle parents */ diff --git a/arch/arm/mach-uniphier/clk/clk-ld20.c b/arch/arm/mach-uniphier/clk/clk-ld20.c new file mode 100644 index 0000000..5bb560c --- /dev/null +++ b/arch/arm/mach-uniphier/clk/clk-ld20.c @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2017 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#include "../init.h" + +#define SDCTRL_EMMC_HW_RESET 0x59810280 + +void uniphier_ld20_clk_init(void) +{ + /* TODO: use "mmc-pwrseq-emmc" */ + writel(1, SDCTRL_EMMC_HW_RESET); +} -- cgit v1.1 From bc647958047cd03193e19cd8c08a6771fea828b7 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 21 Feb 2017 23:00:35 +0900 Subject: ARM: uniphier: set up charge pump current for MPLL of LD11 SoC Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/clk/pll-base-ld20.c | 21 +++++++++++++++++++++ arch/arm/mach-uniphier/clk/pll-ld11.c | 2 ++ arch/arm/mach-uniphier/clk/pll.h | 1 + 3 files changed, 24 insertions(+) (limited to 'arch/arm/mach-uniphier/clk') diff --git a/arch/arm/mach-uniphier/clk/pll-base-ld20.c b/arch/arm/mach-uniphier/clk/pll-base-ld20.c index c66f083..697eb7a 100644 --- a/arch/arm/mach-uniphier/clk/pll-base-ld20.c +++ b/arch/arm/mach-uniphier/clk/pll-base-ld20.c @@ -18,6 +18,8 @@ #define SC_PLLCTRL_SSC_EN BIT(31) #define SC_PLLCTRL2_NRSTDS BIT(28) #define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0) +#define SC_PLLCTRL3_REGI_SHIFT 16 +#define SC_PLLCTRL3_REGI_MASK GENMASK(19, 16) /* PLL type: VPLL27 */ #define SC_VPLL27CTRL_WP BIT(0) @@ -77,6 +79,25 @@ int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base) return 0; } +int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) +{ + void __iomem *base; + u32 tmp; + + base = ioremap(reg_base, SZ_16); + if (!base) + return -ENOMEM; + + tmp = readl(base + 8); /* SSCPLLCTRL */ + tmp &= ~SC_PLLCTRL3_REGI_MASK; + tmp |= regi << SC_PLLCTRL3_REGI_SHIFT; + writel(tmp, base + 8); + + iounmap(base); + + return 0; +} + int uniphier_ld20_vpll27_init(unsigned long reg_base) { void __iomem *base; diff --git a/arch/arm/mach-uniphier/clk/pll-ld11.c b/arch/arm/mach-uniphier/clk/pll-ld11.c index 7746deb..02befa2 100644 --- a/arch/arm/mach-uniphier/clk/pll-ld11.c +++ b/arch/arm/mach-uniphier/clk/pll-ld11.c @@ -18,6 +18,8 @@ void uniphier_ld11_pll_init(void) uniphier_ld20_sscpll_init(SC_MPLLCTRL, 1600, 1, 2); /* 1500MHz -> 1600MHz */ uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + uniphier_ld20_sscpll_set_regi(SC_MPLLCTRL, 5); + mdelay(1); uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL); diff --git a/arch/arm/mach-uniphier/clk/pll.h b/arch/arm/mach-uniphier/clk/pll.h index d7e9303..5eefc4e 100644 --- a/arch/arm/mach-uniphier/clk/pll.h +++ b/arch/arm/mach-uniphier/clk/pll.h @@ -15,6 +15,7 @@ void uniphier_ld4_dpll_ssc_en(void); int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, unsigned int ssc_rate, unsigned int divn); int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base); +int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi); int uniphier_ld20_vpll27_init(unsigned long reg_base); int uniphier_ld20_dspll_init(unsigned long reg_base); -- cgit v1.1