From 8e1601d994e2fa8b8c7826470c3d923a684492a4 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 8 Sep 2015 11:38:04 +0200 Subject: ARM: tegra114: Clear IDDQ when enabling PLLC Enabling a PLL while IDDQ is high. The Linux kernel checks for this condition and warns about it verbosely, so while this seems to work fine, fix it up according to the programming guidelines provided in the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup Sequence"). The Tegra114 TRM doesn't contain this information, but the programming of PLLC is the same on Tegra114 and Tegra124. Signed-off-by: Thierry Reding Signed-off-by: Tom Warren --- arch/arm/mach-tegra/tegra114/clock.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/mach-tegra/tegra114/clock.c') diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c index cec843b..e6ef873 100644 --- a/arch/arm/mach-tegra/tegra114/clock.c +++ b/arch/arm/mach-tegra/tegra114/clock.c @@ -629,6 +629,11 @@ void clock_early_init(void) tegra30_set_up_pllp(); + /* clear IDDQ before accessing any other PLLC registers */ + pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; + clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); + udelay(2); + /* * PLLC output frequency set to 600Mhz * PLLD output frequency set to 925Mhz -- cgit v1.1