From c043c0259cd88f39cdca5f98af8b10f178660745 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 20 Aug 2015 11:42:19 +0200 Subject: ARM: tegra: Implement clk_m On currently supported SoCs, clk_m always runs at the same frequency as the oscillator input. However newer SoC generations such as Tegra210 no longer have that restriction. Prepare for that by separating clk_m from the oscillator clock and allow SoC code to override the clk_m rate. Signed-off-by: Thierry Reding Signed-off-by: Tom Warren --- arch/arm/mach-tegra/clock.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/mach-tegra/clock.c') diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index b85f638..f75c6c6 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -461,6 +461,11 @@ void reset_cmplx_set_enable(int cpu, int which, int reset) writel(mask, &clkrst->crc_cpu_cmplx_clr); } +unsigned int __weak clk_m_get_rate(unsigned int parent_rate) +{ + return parent_rate; +} + unsigned clock_get_rate(enum clock_id clkid) { struct clk_pll *pll; @@ -472,6 +477,9 @@ unsigned clock_get_rate(enum clock_id clkid) if (clkid == CLOCK_ID_OSC) return parent_rate; + if (clkid == CLOCK_ID_CLK_M) + return clk_m_get_rate(parent_rate); + pll = get_pll(clkid); if (!pll) return 0; @@ -622,8 +630,10 @@ void clock_init(void) pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU); pll_rate[CLOCK_ID_SFROM32KHZ] = 32768; pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC); + pll_rate[CLOCK_ID_CLK_M] = clock_get_rate(CLOCK_ID_CLK_M); debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]); + debug("CLKM = %d\n", pll_rate[CLOCK_ID_CLK_M]); debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]); debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]); debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]); -- cgit v1.1