From d5ac6eef91965b519d8f15f17febfa0ea2ee0adc Mon Sep 17 00:00:00 2001 From: Jens Kuske Date: Fri, 19 Aug 2016 13:40:46 +0200 Subject: sunxi: Tune H3 DRAM PLL to improve lock time The H3 PLL5 used for DRAM barely manages to lock to the required frequency before DRAM controller starts, sometimes leading to wrong delay-line calibration results. This patch changes the PLL tuning parameters to the same values as boot0 used, which speeds up the locking and fixes the problem. Signed-off-by: Jens Kuske Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede --- arch/arm/mach-sunxi/clock_sun6i.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/mach-sunxi') diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c index 15272c9..ed8cd9b 100644 --- a/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c @@ -148,6 +148,12 @@ void clock_set_pll5(unsigned int clk, bool sigma_delta_enable) const int max_n = 32; int k = 1, m = 2; +#ifdef CONFIG_MACH_SUN8I_H3 + clrsetbits_le32(&ccm->pll5_tuning_cfg, CCM_PLL5_TUN_LOCK_TIME_MASK | + CCM_PLL5_TUN_INIT_FREQ_MASK, + CCM_PLL5_TUN_LOCK_TIME(2) | CCM_PLL5_TUN_INIT_FREQ(16)); +#endif + if (sigma_delta_enable) writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg); -- cgit v1.1