From 581183def6ec7e7695110ee75ea866b734c5e249 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Fri, 1 Apr 2016 03:51:34 +0900 Subject: ARM: rmobile: Add support R-Car Generation 3 This adds supporting R-Car Generation 3 (Gen3) as Renesas ARM64 SoC. Signed-off-by: Hiroyuki Yokoyama Signed-off-by: Nobuhiro Iwamatsu --- .../arm/mach-rmobile/include/mach/rcar-gen3-base.h | 100 +++++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h (limited to 'arch/arm/mach-rmobile/include') diff --git a/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h b/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h new file mode 100644 index 0000000..fbd87c4 --- /dev/null +++ b/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h @@ -0,0 +1,100 @@ +/* + * ./arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h + * + * Copyright (C) 2015 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_RCAR_GEN3_BASE_H +#define __ASM_ARCH_RCAR_GEN3_BASE_H + +/* + * R-Car (R8A7750) I/O Addresses + */ +#define RWDT_BASE 0xE6020000 +#define SWDT_BASE 0xE6030000 +#define LBSC_BASE 0xEE220200 +#define TMU_BASE 0xE61E0000 +#define GPIO5_BASE 0xE6055000 + +/* SCIF */ +#define SCIF0_BASE 0xE6E60000 +#define SCIF1_BASE 0xE6E68000 +#define SCIF2_BASE 0xE6E88000 +#define SCIF3_BASE 0xE6C50000 +#define SCIF4_BASE 0xE6C40000 +#define SCIF5_BASE 0xE6F30000 + +/* Module stop status register */ +#define MSTPSR0 0xE6150030 +#define MSTPSR1 0xE6150038 +#define MSTPSR2 0xE6150040 +#define MSTPSR3 0xE6150048 +#define MSTPSR4 0xE615004C +#define MSTPSR5 0xE615003C +#define MSTPSR6 0xE61501C0 +#define MSTPSR7 0xE61501C4 +#define MSTPSR8 0xE61509A0 +#define MSTPSR9 0xE61509A4 +#define MSTPSR10 0xE61509A8 +#define MSTPSR11 0xE61509AC + +/* Realtime module stop control register */ +#define RMSTPCR0 0xE6150110 +#define RMSTPCR1 0xE6150114 +#define RMSTPCR2 0xE6150118 +#define RMSTPCR3 0xE615011C +#define RMSTPCR4 0xE6150120 +#define RMSTPCR5 0xE6150124 +#define RMSTPCR6 0xE6150128 +#define RMSTPCR7 0xE615012C +#define RMSTPCR8 0xE6150980 +#define RMSTPCR9 0xE6150984 +#define RMSTPCR10 0xE6150988 +#define RMSTPCR11 0xE615098C + +/* System module stop control register */ +#define SMSTPCR0 0xE6150130 +#define SMSTPCR1 0xE6150134 +#define SMSTPCR2 0xE6150138 +#define SMSTPCR3 0xE615013C +#define SMSTPCR4 0xE6150140 +#define SMSTPCR5 0xE6150144 +#define SMSTPCR6 0xE6150148 +#define SMSTPCR7 0xE615014C +#define SMSTPCR8 0xE6150990 +#define SMSTPCR9 0xE6150994 +#define SMSTPCR10 0xE6150998 +#define SMSTPCR11 0xE615099C + +/* SDHI */ +#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000 +#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000 +#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 +#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 + +/* PFC */ +#define PFC_PUEN6 0xE6060418 +#define PUEN_USB1_OVC (1 << 2) +#define PUEN_USB1_PWEN (1 << 1) + +#ifndef __ASSEMBLY__ +#include + +/* RWDT */ +struct rcar_rwdt { + u32 rwtcnt; + u32 rwtcsra; + u32 rwtcsrb; +}; + +/* SWDT */ +struct rcar_swdt { + u32 swtcnt; + u32 swtcsra; + u32 swtcsrb; +}; +#endif + +#endif /* __ASM_ARCH_RCAR_GEN3_BASE_H */ -- cgit v1.1