From b58385df3a448ba90e4ed0b699d275597ff73ea9 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Sun, 4 Dec 2016 18:34:13 +0200 Subject: arm64: mvebu: Add L3 cache flush functionality to A8K family Add missing L3 cache flush functionality which absence prevents Linux kernel from normal boot in case the L3 cache is enabled by ATF. The L3 cache is named the "last level" cache in order to keep the terminology similar to the ATF code. This cache should not be disabled by u-boot since the Linux kernel cannot activate it, so it is activates at ATF stage. However the cache flush is required for preventing data corruption after disabling the MMU and the data cache before passing control to the loaded Linux image. Signed-off-by: Konstantin Porotchkin Cc: Stefan Roese Cc: Nadav Haklai Cc: Neta Zur Hershkovits Cc: Omri Itach Cc: Igal Liberman Cc: Haim Boot Cc: Hanna Hawa Signed-off-by: Stefan Roese --- arch/arm/mach-mvebu/armada8k/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/mach-mvebu/armada8k/Makefile') diff --git a/arch/arm/mach-mvebu/armada8k/Makefile b/arch/arm/mach-mvebu/armada8k/Makefile index 84c69d9..0facf14 100644 --- a/arch/arm/mach-mvebu/armada8k/Makefile +++ b/arch/arm/mach-mvebu/armada8k/Makefile @@ -5,3 +5,4 @@ # obj-y = cpu.o +obj-y += cache_llc.o -- cgit v1.1