From c2ad76c4bdfb8ffbe8946c0e6627b37a11effdf7 Mon Sep 17 00:00:00 2001 From: Wenyou Yang Date: Mon, 1 Feb 2016 18:12:16 +0800 Subject: arm: at91/spl: mpddrc: add mpddrc DDR3-SDRAM initialization MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The DDR3-SDRAM initialization sequence is implemented in accordance with the DDR3-SRAM/DDR3L-SDRAM initialization section described in the SAMA5D2 datasheet. Add registers and definitions of mpddrc controller, which is used to support DDR3 devices. Signed-off-by: Wenyou Yang Reviewed-by: Andreas Bießmann --- arch/arm/mach-at91/mpddrc.c | 89 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) (limited to 'arch/arm/mach-at91/mpddrc.c') diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c index 9ba2a00..1e1ff1d 100644 --- a/arch/arm/mach-at91/mpddrc.c +++ b/arch/arm/mach-at91/mpddrc.c @@ -2,6 +2,9 @@ * Copyright (C) 2013 Atmel Corporation * Bo Shen * + * Copyright (C) 2015 Atmel Corporation + * Wenyou Yang + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -135,3 +138,89 @@ int ddr2_init(const unsigned int base, return 0; } + +int ddr3_init(const unsigned int base, + const unsigned int ram_address, + const struct atmel_mpddrc_config *mpddr_value) +{ + struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base; + u32 ba_off; + + /* Compute bank offset according to NC in configuration register */ + ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9; + if (ddr2_decodtype_is_seq(mpddr_value->cr)) + ba_off += ((mpddr_value->cr & + ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11; + + ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2; + + /* Program the memory device type */ + writel(mpddr_value->md, &mpddr->md); + + /* + * Program features of the DDR3-SDRAM device and timing parameters + */ + writel(mpddr_value->cr, &mpddr->cr); + + writel(mpddr_value->tpr0, &mpddr->tpr0); + writel(mpddr_value->tpr1, &mpddr->tpr1); + writel(mpddr_value->tpr2, &mpddr->tpr2); + + /* A NOP command is issued to the DDR3-SRAM */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); + + /* A pause of at least 500us must be observed before a single toggle. */ + udelay(500); + + /* A NOP command is issued to the DDR3-SDRAM */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); + + /* + * An Extended Mode Register Set (EMRS2) cycle is issued to choose + * between commercial or high temperature operations. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, + ram_address + (0x2 << ba_off)); + /* + * Step 7: An Extended Mode Register Set (EMRS3) cycle is issued to set + * the Extended Mode Register to 0. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, + ram_address + (0x3 << ba_off)); + /* + * An Extended Mode Register Set (EMRS1) cycle is issued to disable and + * to program O.D.S. (Output Driver Strength). + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, + ram_address + (0x1 << ba_off)); + + /* + * Write a one to the DLL bit (enable DLL reset) in the MPDDRC + * Configuration Register. + */ + + /* A Mode Register Set (MRS) cycle is issued to reset DLL. */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address); + + udelay(50); + + /* + * A Calibration command (MRS) is issued to calibrate RTT and RON + * values for the Process Voltage Temperature (PVT). + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_DEEP_CMD, ram_address); + + /* A Normal Mode command is provided. */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address); + + /* Perform a write access to any DDR3-SDRAM address. */ + writel(0, ram_address); + + /* + * Write the refresh rate into the COUNT field in the MPDDRC + * Refresh Timer Register (MPDDRC_RTR): + */ + writel(mpddr_value->rtr, &mpddr->rtr); + + return 0; +} -- cgit v1.1