From 633b6ccedf9d536fd93299b2207a5227dedd987c Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Mon, 27 Jul 2015 11:40:17 +0800 Subject: ARM: cache: implement a default weak flush_cache() function Current many cpu use the same flush_cache() function, which just call the flush_dcache_range(). So implement a weak flush_cache() for all the cpus to use. In original weak flush_cache() in arch/arm/lib/cache.c, there has some code for ARM1136 & ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache() function as well. That means the original code for ARM1136 & ARM926ejs in weak flush_cache() of arch/arm/lib/cache.c is totally useless. So in this patch remove such code in flush_cache() and only call flush_dcache_range(). Signed-off-by: Josh Wu --- arch/arm/lib/cache.c | 26 +++++--------------------- 1 file changed, 5 insertions(+), 21 deletions(-) (limited to 'arch/arm/lib/cache.c') diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index bc48f53..cd13db3 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -10,29 +10,13 @@ #include #include +/* + * Flush range from all levels of d-cache/unified-cache. + * Affects the range [start, start + size - 1]. + */ __weak void flush_cache(unsigned long start, unsigned long size) { -#if defined(CONFIG_CPU_ARM1136) - -#if !defined(CONFIG_SYS_ICACHE_OFF) - asm("mcr p15, 0, r1, c7, c5, 0"); /* invalidate I cache */ -#endif - -#if !defined(CONFIG_SYS_DCACHE_OFF) - asm("mcr p15, 0, r1, c7, c14, 0"); /* Clean+invalidate D cache */ -#endif - -#endif /* CONFIG_CPU_ARM1136 */ - -#ifdef CONFIG_CPU_ARM926EJS -#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) - /* test and clean, page 2-23 of arm926ejs manual */ - asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); - /* disable write buffer as well (page 2-22) */ - asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); -#endif -#endif /* CONFIG_CPU_ARM926EJS */ - return; + flush_dcache_range(start, start + size); } /* -- cgit v1.1