From cd20f2afe2da42a98a4071dedb86590f0d53bd21 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 22 Feb 2017 16:21:43 +0800 Subject: imx: mx7ulp: Add soc level initialization codes and functions Implement soc level functions to get cpu rev, reset cause, enable cache, etc. We will disable the wdog and init clocks in s_init at very early u-boot phase. Since the we are seeking the way to get chip id for mx7ulp, the get_cpu_rev is hard coded to a fixed value. This may change in future. Reuse some code in imx-common. Signed-off-by: Peng Fan Signed-off-by: Ye Li Cc: Stefano Babic --- arch/arm/include/asm/arch-imx/cpu.h | 2 ++ arch/arm/include/asm/arch-mx7ulp/sys_proto.h | 21 +++++++++++++++++++++ 2 files changed, 23 insertions(+) create mode 100644 arch/arm/include/asm/arch-mx7ulp/sys_proto.h (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 8bd1421..b052406 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -25,10 +25,12 @@ #define MXC_CPU_MX6QP 0x69 #define MXC_CPU_MX7S 0x71 /* dummy ID */ #define MXC_CPU_MX7D 0x72 +#define MXC_CPU_MX7ULP 0x81 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ #define MXC_SOC_MX6 0x60 #define MXC_SOC_MX7 0x70 +#define MXC_SOC_MX7ULP 0x80 /* dummy */ #define CHIP_REV_1_0 0x10 #define CHIP_REV_1_1 0x11 diff --git a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h new file mode 100644 index 0000000..d01748f --- /dev/null +++ b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SYS_PROTO_MX7ULP_H_ +#define _SYS_PROTO_MX7ULP_H_ + +#include + +#define BT0CFG_LPBOOT_MASK 0x1 +#define BT0CFG_DUALBOOT_MASK 0x2 + +enum bt_mode { + LOW_POWER_BOOT, /* LP_BT = 1 */ + DUAL_BOOT, /* LP_BT = 0, DUAL_BT = 1 */ + SINGLE_BOOT /* LP_BT = 0, DUAL_BT = 0 */ +}; + +#endif -- cgit v1.1