From 991963bce9e3a8f51499785c736ec54e527f3a2b Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Sun, 22 Mar 2015 18:07:08 +0100 Subject: sunxi: gpio: Indentation fix Signed-off-by: Paul Kocialkowski Acked-by: Hans de Goede Signed-off-by: Hans de Goede --- arch/arm/include/asm/arch-sunxi/gpio.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index f2c247d..a66e45c 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -84,7 +84,7 @@ struct sunxi_gpio_reg { #define GPIO_CFG_INDEX(pin) (((pin) & 0x1f) >> 3) #define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1f) & 0x7) << 2) -#define GPIO_DRV_INDEX(pin) (((pin) & 0x1f) >> 4) +#define GPIO_DRV_INDEX(pin) (((pin) & 0x1f) >> 4) #define GPIO_DRV_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) #define GPIO_PULL_INDEX(pin) (((pin) & 0x1f) >> 4) @@ -194,7 +194,7 @@ enum sunxi_gpio_number { #define SUN8I_GPL3_R_UART_RX 2 #define SUN9I_GPN0_R_RSB_SCK 3 -#define SUN9I_GPN1_R_RSB_SDA 3 +#define SUN9I_GPN1_R_RSB_SDA 3 /* GPIO pin pull-up/down config */ #define SUNXI_GPIO_PULL_DISABLE 0 -- cgit v1.1 From f7c7ab636ab2c81d9fb1def7256c94b998c7298f Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Sun, 22 Mar 2015 18:07:09 +0100 Subject: power: axp221: Virtual VBUS detect and enable GPIOs to replace separate logic This converts the VBUS detection and enable logic to GPIO instead of separate axp functions and checks that have to be used aside usual GPIO functions. Signed-off-by: Paul Kocialkowski Acked-by: Hans de Goede Signed-off-by: Hans de Goede --- arch/arm/include/asm/arch-sunxi/gpio.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index a66e45c..3a4b8c3 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -201,6 +201,10 @@ enum sunxi_gpio_number { #define SUNXI_GPIO_PULL_UP 1 #define SUNXI_GPIO_PULL_DOWN 2 +/* Virtual AXP0 GPIOs */ +#define SUNXI_GPIO_AXP0_VBUS_DETECT 8 +#define SUNXI_GPIO_AXP0_VBUS_ENABLE 9 + void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val); void sunxi_gpio_set_cfgpin(u32 pin, u32 val); int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset); -- cgit v1.1 From ebd468b2d26660ff7811e37cc64fa2369d4b5fff Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Sun, 22 Mar 2015 18:07:12 +0100 Subject: sunxi: common VBUS detection logic in usbc VBUS detection could be needed not only by the musb code (to prevent host mode), but also by e.g. gadget drivers to start only when a cable is connected. In addition, this allows more flexibility in vbus detection, as it could easily be extended to other USBC indexes. Eventually, this would help making musb support independent from a hardcoded USB controller index (0). Signed-off-by: Paul Kocialkowski Acked-by: Hans de Goede Signed-off-by: Hans de Goede --- arch/arm/include/asm/arch-sunxi/usbc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-sunxi/usbc.h b/arch/arm/include/asm/arch-sunxi/usbc.h index 1330733..ab0f272 100644 --- a/arch/arm/include/asm/arch-sunxi/usbc.h +++ b/arch/arm/include/asm/arch-sunxi/usbc.h @@ -20,4 +20,5 @@ void sunxi_usbc_enable(int index); void sunxi_usbc_disable(int index); void sunxi_usbc_vbus_enable(int index); void sunxi_usbc_vbus_disable(int index); +int sunxi_usbc_vbus_detect(int index); void sunxi_usbc_enable_squelch_detect(int index, int enable); -- cgit v1.1 From 487b3277d4f70bcb2e4a1930beb6438565f25910 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Sun, 22 Mar 2015 18:12:22 +0100 Subject: sunxi: GPIO pin mux hardware-feature-specific function index defines Each hardware feature exposed through the GPIO pin mux is usually using the same function index (for a given port), so there is no need to define one value per pin: one value per hardware feature per port is sufficient, avoids duplication and makes everything easier to understand. Signed-off-by: Paul Kocialkowski Acked-by: Hans de Goede Signed-off-by: Hans de Goede --- arch/arm/include/asm/arch-sunxi/gpio.h | 60 +++++++++++----------------------- 1 file changed, 19 insertions(+), 41 deletions(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 3a4b8c3..a6b15d6 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -142,59 +142,37 @@ enum sunxi_gpio_number { #define SUNXI_GPIO_INPUT 0 #define SUNXI_GPIO_OUTPUT 1 -#define SUNXI_GPA0_EMAC 2 -#define SUN6I_GPA0_GMAC 2 -#define SUN7I_GPA0_GMAC 5 +#define SUNXI_GPA_EMAC 2 +#define SUN6I_GPA_GMAC 2 +#define SUN7I_GPA_GMAC 5 -#define SUNXI_GPB0_TWI0 2 +#define SUNXI_GPB_TWI0 2 +#define SUN4I_GPB_UART0 2 +#define SUN5I_GPB_UART0 2 -#define SUN4I_GPB22_UART0_TX 2 -#define SUN4I_GPB23_UART0_RX 2 +#define SUNXI_GPC_SDC2 3 -#define SUN5I_GPB19_UART0_TX 2 -#define SUN5I_GPB20_UART0_RX 2 +#define SUNXI_GPD_LCD0 2 +#define SUNXI_GPD_LVDS0 3 -#define SUNXI_GPC6_SDC2 3 +#define SUNXI_GPF_SDC0 2 +#define SUNXI_GPF_UART0 4 +#define SUN8I_GPF_UART0 3 -#define SUNXI_GPD0_LCD0 2 -#define SUNXI_GPD0_LVDS0 3 +#define SUN5I_GPG_SDC1 2 +#define SUN5I_GPG_UART1 4 -#define SUNXI_GPF0_SDC0 2 +#define SUN6I_GPH_UART0 2 -#define SUNXI_GPF2_SDC0 2 - -#ifdef CONFIG_MACH_SUN8I -#define SUNXI_GPF2_UART0_TX 3 -#define SUNXI_GPF4_UART0_RX 3 -#else -#define SUNXI_GPF2_UART0_TX 4 -#define SUNXI_GPF4_UART0_RX 4 -#endif - -#define SUN4I_GPG0_SDC1 4 - -#define SUN5I_GPG3_SDC1 2 - -#define SUN5I_GPG3_UART1_TX 4 -#define SUN5I_GPG4_UART1_RX 4 - -#define SUN4I_GPH22_SDC1 5 - -#define SUN6I_GPH20_UART0_TX 2 -#define SUN6I_GPH21_UART0_RX 2 - -#define SUN4I_GPI4_SDC3 2 +#define SUN4I_GPI_SDC3 2 #define SUN6I_GPL0_R_P2WI_SCK 3 #define SUN6I_GPL1_R_P2WI_SDA 3 -#define SUN8I_GPL0_R_RSB_SCK 2 -#define SUN8I_GPL1_R_RSB_SDA 2 -#define SUN8I_GPL2_R_UART_TX 2 -#define SUN8I_GPL3_R_UART_RX 2 +#define SUN8I_GPL_R_RSB 2 +#define SUN8I_GPL_R_UART 2 -#define SUN9I_GPN0_R_RSB_SCK 3 -#define SUN9I_GPN1_R_RSB_SDA 3 +#define SUN9I_GPN_R_RSB 3 /* GPIO pin pull-up/down config */ #define SUNXI_GPIO_PULL_DISABLE 0 -- cgit v1.1 From 8deacca975585c11663db984002dca0c48bcc2d5 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Sun, 22 Mar 2015 18:12:23 +0100 Subject: sunxi: Complete mmc pin mux for each supported platform, configured with Kconfig Sunxi platforms have different possible mmc pin mux setups (except for mmc0), which are different across platforms. This lets users configure which is used through the CONFIG_MMC*_PINS Kconfig options. This is especially relevant when a second (in addition to mmc0) port is used and CONFIG_MMC_SUNXI_SLOT_EXTRA is enabled. Signed-off-by: Paul Kocialkowski Acked-by: Hans de Goede Signed-off-by: Hans de Goede --- arch/arm/include/asm/arch-sunxi/gpio.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index a6b15d6..f227044 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -145,26 +145,36 @@ enum sunxi_gpio_number { #define SUNXI_GPA_EMAC 2 #define SUN6I_GPA_GMAC 2 #define SUN7I_GPA_GMAC 5 +#define SUN6I_GPA_SDC2 5 +#define SUN6I_GPA_SDC3 4 #define SUNXI_GPB_TWI0 2 #define SUN4I_GPB_UART0 2 #define SUN5I_GPB_UART0 2 #define SUNXI_GPC_SDC2 3 +#define SUN6I_GPC_SDC3 4 +#define SUN8I_GPD_SDC1 3 #define SUNXI_GPD_LCD0 2 #define SUNXI_GPD_LVDS0 3 +#define SUN5I_GPE_SDC2 3 + #define SUNXI_GPF_SDC0 2 #define SUNXI_GPF_UART0 4 #define SUN8I_GPF_UART0 3 +#define SUN4I_GPG_SDC1 4 #define SUN5I_GPG_SDC1 2 +#define SUN6I_GPG_SDC1 2 +#define SUN8I_GPG_SDC1 2 #define SUN5I_GPG_UART1 4 +#define SUN4I_GPH_SDC1 5 #define SUN6I_GPH_UART0 2 -#define SUN4I_GPI_SDC3 2 +#define SUNXI_GPI_SDC3 2 #define SUN6I_GPL0_R_P2WI_SCK 3 #define SUN6I_GPL1_R_P2WI_SDA 3 @@ -189,6 +199,7 @@ int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset); int sunxi_gpio_get_cfgpin(u32 pin); int sunxi_gpio_set_drv(u32 pin, u32 val); int sunxi_gpio_set_pull(u32 pin, u32 val); +int sunxi_name_to_gpio_bank(const char *name); int sunxi_name_to_gpio(const char *name); #define name_to_gpio(name) sunxi_name_to_gpio(name) -- cgit v1.1 From dd82242b4dd7d251ef9ba43563cf9a0017d6f98e Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Fri, 10 Apr 2015 23:09:51 +0200 Subject: i2c: mvtwsi: Support for up to 4 different controllers Orion5x, Kirkwood and Armada XP platforms come with a single TWSI (I2C) MVTWSI controller. However, other platforms using MVTWSI may come with more: this is the case on Allwinner (sunxi) platforms, where up to 4 controllers can be found on the same chip. Signed-off-by: Paul Kocialkowski Acked-by: Heiko Schocher Acked-by: Hans de Goede Signed-off-by: Hans de Goede --- arch/arm/include/asm/arch-sunxi/i2c.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h index dc5406b..502e3c6 100644 --- a/arch/arm/include/asm/arch-sunxi/i2c.h +++ b/arch/arm/include/asm/arch-sunxi/i2c.h @@ -8,7 +8,7 @@ #include -#define CONFIG_I2C_MVTWSI_BASE SUNXI_TWI0_BASE +#define CONFIG_I2C_MVTWSI_BASE0 SUNXI_TWI0_BASE /* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */ #define CONFIG_SYS_TCLK 24000000 -- cgit v1.1 From 6c739c5d8a3466f8ef2f8543636484957bcca6ee Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Fri, 10 Apr 2015 23:09:52 +0200 Subject: sunxi: Complete i2c support for each supported platform Sunxi platforms come with at least 3 TWI (I2C) controllers and some platforms even have up to 5. This adds support for every controller on each supported platform, which is especially useful when using expansion ports on single-board- computers. Signed-off-by: Paul Kocialkowski Acked-by: Hans de Goede Signed-off-by: Hans de Goede --- arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 7 +++++++ arch/arm/include/asm/arch-sunxi/gpio.h | 15 ++++++++++++++- arch/arm/include/asm/arch-sunxi/i2c.h | 15 +++++++++++++++ 3 files changed, 36 insertions(+), 1 deletion(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index dae6069..f403742 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -94,6 +94,13 @@ #define SUNXI_TWI0_BASE 0x01c2ac00 #define SUNXI_TWI1_BASE 0x01c2b000 #define SUNXI_TWI2_BASE 0x01c2b400 +#ifdef CONFIG_MACH_SUN6I +#define SUNXI_TWI3_BASE 0x01c0b800 +#endif +#ifdef CONFIG_MACH_SUN7I +#define SUNXI_TWI3_BASE 0x01c2b800 +#define SUNXI_TWI4_BASE 0x01c2c000 +#endif #define SUNXI_CAN_BASE 0x01c2bc00 diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index f227044..ae7cbb7 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -148,7 +148,11 @@ enum sunxi_gpio_number { #define SUN6I_GPA_SDC2 5 #define SUN6I_GPA_SDC3 4 -#define SUNXI_GPB_TWI0 2 +#define SUN4I_GPB_TWI0 2 +#define SUN4I_GPB_TWI1 2 +#define SUN5I_GPB_TWI1 2 +#define SUN4I_GPB_TWI2 2 +#define SUN5I_GPB_TWI2 2 #define SUN4I_GPB_UART0 2 #define SUN5I_GPB_UART0 2 @@ -160,6 +164,7 @@ enum sunxi_gpio_number { #define SUNXI_GPD_LVDS0 3 #define SUN5I_GPE_SDC2 3 +#define SUN8I_GPE_TWI2 3 #define SUNXI_GPF_SDC0 2 #define SUNXI_GPF_UART0 4 @@ -169,12 +174,20 @@ enum sunxi_gpio_number { #define SUN5I_GPG_SDC1 2 #define SUN6I_GPG_SDC1 2 #define SUN8I_GPG_SDC1 2 +#define SUN6I_GPG_TWI3 2 #define SUN5I_GPG_UART1 4 #define SUN4I_GPH_SDC1 5 +#define SUN6I_GPH_TWI0 2 +#define SUN8I_GPH_TWI0 2 +#define SUN6I_GPH_TWI1 2 +#define SUN8I_GPH_TWI1 2 +#define SUN6I_GPH_TWI2 2 #define SUN6I_GPH_UART0 2 #define SUNXI_GPI_SDC3 2 +#define SUN7I_GPI_TWI3 3 +#define SUN7I_GPI_TWI4 3 #define SUN6I_GPL0_R_P2WI_SCK 3 #define SUN6I_GPL1_R_P2WI_SDA 3 diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h index 502e3c6..561cd2b 100644 --- a/arch/arm/include/asm/arch-sunxi/i2c.h +++ b/arch/arm/include/asm/arch-sunxi/i2c.h @@ -8,7 +8,22 @@ #include +#ifdef CONFIG_I2C0_ENABLE #define CONFIG_I2C_MVTWSI_BASE0 SUNXI_TWI0_BASE +#endif +#ifdef CONFIG_I2C1_ENABLE +#define CONFIG_I2C_MVTWSI_BASE1 SUNXI_TWI1_BASE +#endif +#ifdef CONFIG_I2C2_ENABLE +#define CONFIG_I2C_MVTWSI_BASE2 SUNXI_TWI2_BASE +#endif +#ifdef CONFIG_I2C3_ENABLE +#define CONFIG_I2C_MVTWSI_BASE3 SUNXI_TWI3_BASE +#endif +#ifdef CONFIG_I2C4_ENABLE +#define CONFIG_I2C_MVTWSI_BASE4 SUNXI_TWI4_BASE +#endif + /* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */ #define CONFIG_SYS_TCLK 24000000 -- cgit v1.1 From cb9f8e6a737e60f460896111b32bbebc45aa1cd1 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 20 Apr 2015 07:53:48 +0200 Subject: video, ipu: make ldb clock frequency overwritable through board code the ldb clock can be setup in board code (for example set through PLL5). Update the ldb_clock rate also through board code. This should be removed, if a clock framework is availiable. Signed-off-by: Heiko Schocher Tested-by: Eric Nelson --- arch/arm/include/asm/imx-common/video.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/imx-common/video.h b/arch/arm/include/asm/imx-common/video.h index 1a907d4..cad5f86 100644 --- a/arch/arm/include/asm/imx-common/video.h +++ b/arch/arm/include/asm/imx-common/video.h @@ -26,4 +26,5 @@ extern struct display_info_t const displays[]; extern size_t display_count; #endif +int ipu_set_ldb_clock(int rate); #endif -- cgit v1.1 From c218f85ea18d57beecc36a3460f08e929d81fcd6 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 30 Mar 2015 17:01:04 -0500 Subject: arm: socfpga: add functions to bring sdram, timer, and uart out of reset These functions will be needed for use by the SPL for enabling the console and sdram initialization. Signed-off-by: Dinh Nguyen Acked-by: Marek Vasut Acked-by: Pavel Machek --- arch/arm/include/asm/arch-socfpga/reset_manager.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h index 034135b..d63a285 100644 --- a/arch/arm/include/asm/arch-socfpga/reset_manager.h +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -15,6 +15,9 @@ void socfpga_bridges_reset(int enable); void socfpga_emac_reset(int enable); void socfpga_watchdog_reset(void); void socfpga_spim_enable(void); +void socfpga_uart0_enable(void); +void socfpga_sdram_enable(void); +void socfpga_osc1timer_enable(void); struct socfpga_reset_manager { u32 status; @@ -36,7 +39,10 @@ struct socfpga_reset_manager { #define RSTMGR_PERMODRST_EMAC0_LSB 0 #define RSTMGR_PERMODRST_EMAC1_LSB 1 #define RSTMGR_PERMODRST_L4WD0_LSB 6 +#define RSTMGR_PERMODRST_OSC1TIMER0_LSB 8 +#define RSTMGR_PERMODRST_UART0_LSB 16 #define RSTMGR_PERMODRST_SPIM0_LSB 18 #define RSTMGR_PERMODRST_SPIM1_LSB 19 +#define RSTMGR_PERMODRST_SDR_LSB 29 #endif /* _RESET_MANAGER_H_ */ -- cgit v1.1 From 08e463ee8a7a5641e191be2a8e934d8284d1ca55 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 30 Mar 2015 17:01:07 -0500 Subject: arm: socfpga: spl: allow bootrom to enable IOs after warm reset Signed-off-by: Dinh Nguyen Acked-by: Marek Vasut --- arch/arm/include/asm/arch-socfpga/system_manager.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h b/arch/arm/include/asm/arch-socfpga/system_manager.h index 071ec4f..51d9815 100644 --- a/arch/arm/include/asm/arch-socfpga/system_manager.h +++ b/arch/arm/include/asm/arch-socfpga/system_manager.h @@ -10,6 +10,7 @@ #ifndef __ASSEMBLY__ void sysmgr_pinmux_init(void); +void sysmgr_enable_warmrstcfgio(void); /* declaration for handoff table type */ extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM]; -- cgit v1.1 From b284d268aff2253b162c636bc63d8fd289159296 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 21 Apr 2015 12:30:09 +0200 Subject: arm: socfpga: spl: Add stub sdram.h Since the SoCFPGA SDRAM support is not yet applied to u-boot, we still need to be able to compile the codebase. Introduce stub functions which temporarily supplement the missing SDRAM setup functions. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Pavel Machek Cc: Stefan Roese Cc: Tom Rini Cc: Vince Bridgers --- arch/arm/include/asm/arch-socfpga/sdram.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 arch/arm/include/asm/arch-socfpga/sdram.h (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-socfpga/sdram.h b/arch/arm/include/asm/arch-socfpga/sdram.h new file mode 100644 index 0000000..4f6489d --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/sdram.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2015 Marek Vasut + * + * FIXME: This file contains temporary stub functions and is here + * only until these functions are properly merged into + * mainline. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_SDRAM_H__ +#define __ARCH_SDRAM_H__ + +/* function declaration */ +inline unsigned long sdram_calculate_size(void) { return 0; } +inline unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg) { return 0; } +inline int sdram_calibration_full(void) { return 0; } + +#endif /* __ARCH_SDRAM_H__ */ -- cgit v1.1 From 036f3f3379d56a4eb64d5154b47a8981a478fe3e Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Thu, 12 Mar 2015 11:31:44 +0800 Subject: arm/ls102xa:Add support of conditional workaround implementation as per SoC ver For LS102xA, some workarounds are only used in VER1.0, so silicon version detection are added for QDS and TWR boards. Signed-off-by: Alison Wang Reviewed-by: York Sun --- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 3a64afc..a8122c1 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -17,6 +17,9 @@ #define SOC_VER_LS1021 0x11 #define SOC_VER_LS1022 0x12 +#define SOC_MAJOR_VER_1_0 0x1 +#define SOC_MAJOR_VER_2_0 0x2 + #define CCSR_BRR_OFFSET 0xe4 #define CCSR_SCRATCHRW1_OFFSET 0x200 -- cgit v1.1 From 98cb0efde8aaed200750e6d75fa8e5fc01dcd8f4 Mon Sep 17 00:00:00 2001 From: gaurav rana Date: Tue, 10 Mar 2015 14:08:50 +0530 Subject: Add bootscript support to esbc_validate. 1. Default environment will be used for secure boot flow which can't be edited or saved. 2. Command for secure boot is predefined in the default environment which will run on autoboot (and autoboot is the only option allowed in case of secure boot) and it looks like this: #define CONFIG_SECBOOT \ "setenv bs_hdraddr 0xe8e00000;" \ "esbc_validate $bs_hdraddr;" \ "source $img_addr;" \ "esbc_halt;" #endif 3. Boot Script can contain esbc_validate commands and bootm command. Uboot source command used in default secure boot command will run the bootscript. 4. Command esbc_halt added to ensure either bootm executes after validation of images or core should just spin. Signed-off-by: Ruchika Gupta Signed-off-by: Gaurav Rana Reviewed-by: York Sun --- arch/arm/include/asm/fsl_secure_boot.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 arch/arm/include/asm/fsl_secure_boot.h (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h new file mode 100644 index 0000000..f097c81 --- /dev/null +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -0,0 +1,25 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_SECURE_BOOT_H +#define __FSL_SECURE_BOOT_H + +#ifdef CONFIG_SECURE_BOOT +#ifndef CONFIG_FIT_SIGNATURE + +#define CONFIG_EXTRA_ENV \ + "setenv fdt_high 0xcfffffff;" \ + "setenv initrd_high 0xcfffffff;" \ + "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" + +/* The address needs to be modified according to NOR memory map */ +#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x600a0000 + +#include +#endif +#endif + +#endif -- cgit v1.1 From d42bd3453af5dc81b6907be1b066b34ba0a0c979 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Thu, 12 Mar 2015 10:58:48 +0800 Subject: pci/layerscape: remove unnecessary pcie_layerscape.h The patch uses the common function name ft_pci_setup to replace ft_pcie_setup, then removes unnecessary pcie_layerscape.h because all the functions have been declared in common.h. Signed-off-by: Minghuan Lian Reviewed-by: Tom Rini Reviewed-by: York Sun --- arch/arm/include/asm/pcie_layerscape.h | 13 ------------- 1 file changed, 13 deletions(-) delete mode 100644 arch/arm/include/asm/pcie_layerscape.h (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/pcie_layerscape.h b/arch/arm/include/asm/pcie_layerscape.h deleted file mode 100644 index fb08578..0000000 --- a/arch/arm/include/asm/pcie_layerscape.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __PCIE_LAYERSCAPE_H_ -#define __PCIE_LAYERSCAPE_H_ - -void pci_init_board(void); -void ft_pcie_setup(void *blob, bd_t *bd); - -#endif -- cgit v1.1 From ae42eb035e86f2fca98adc5f5b59543a49797877 Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Wed, 25 Mar 2015 17:02:59 +0800 Subject: QE/DeepSleep: add QE deepsleep support for mpc85xx Muram will power off during deepsleep, and the microcode of qe in muram will be lost, it should be reload when resume. Signed-off-by: Zhao Qiang Reviewed-by: York Sun --- arch/arm/include/asm/arch-ls102xa/config.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 6561ce6..4dc528b 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -119,10 +119,6 @@ #define DCU_LAYER_MAX_NUM 16 -#define QE_MURAM_SIZE 0x6000UL -#define MAX_QE_RISC 1 -#define QE_NUM_OF_SNUM 28 - #define CONFIG_SYS_FSL_SRDS_1 #ifdef CONFIG_LS102XA -- cgit v1.1 From 422cb08acb1bc9a05ffa68ba68b4e196dad1af5b Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Thu, 19 Mar 2015 09:20:43 -0700 Subject: armv8/fsl-lsch3: Add Freescale Debug Server driver The Debug Server driver is responsible for loading the Debug server FW on the Service Processor (Cortex-A5 core) on LS2085A like SoCs and then polling for the successful initialization of the same. TOP MEM HIDE is adjusted to ensure the space required by Debug Server FW is accounted for. MC uses the DDR area which is calculated as: MC DDR region start = Top of DDR - area reserved by Debug Server FW Signed-off-by: Bhupesh Sharma Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-lsch3/config.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index b140c1f..59d10bf 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -30,6 +30,15 @@ #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ 0x18A0) +/* SP (Cortex-A5) related */ +#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000) +#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR) +#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR) +#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \ + (CONFIG_SYS_FSL_SP_ADDR + 0x0008) +#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \ + (CONFIG_SYS_FSL_SP_ADDR + 0x1000) + #define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL @@ -88,7 +97,6 @@ #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 - /* IFC */ #define CONFIG_SYS_FSL_IFC_LE -- cgit v1.1 From a2a55e518f81900ab1538656e5df8d2759ccb1fb Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Thu, 19 Mar 2015 09:20:45 -0700 Subject: driver/fsl-mc: Add support of MC Flibs Freescale's Layerscape Management Complex (MC) provide support various objects like DPRC, DPNI, DPBP and DPIO. Where: DPRC: Place holdes for other MC objectes like DPNI, DPBP, DPIO DPBP: Management of buffer pool DPIO: Used for used to QBMan portal DPNI: Represents standard network interface These objects are used for DPAA ethernet drivers. Signed-off-by: J. German Rivera Signed-off-by: Lijun Pan Signed-off-by: Stuart Yoder Signed-off-by: Geoff Thorpe Signed-off-by: Haiying Wang Signed-off-by: Cristian Sovaiala Signed-off-by: pankaj chauhan Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-lsch3/config.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 59d10bf..0217582 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -8,6 +8,8 @@ #define _ASM_ARMV8_FSL_LSCH3_CONFIG_ #include + +#define CONFIG_SYS_PAGE_SIZE 0x10000 #define CONFIG_MP #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ /* Link Definitions */ -- cgit v1.1 From 78c5a180871d4337d4cfd41d6739a04b271b2e4d Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 3 Apr 2015 16:52:52 -0700 Subject: arm: mx6: ddr: add pd_fast_exit flag to system information DDR3 has a special Precharge power-down mode: fast-exit vs slow-exit. In slow-exit mode the DLL is off but in some quiescent state that makes it easy to turn on again in tXPDLL cycles (about 10tCK) vs the full tDLLK (512tCK). In fast-exist mode the DLL is maintained such that it is ready again in about 3tCK. Signed-off-by: Tim Harvey --- arch/arm/include/asm/arch-mx6/mx6-ddr.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h index 8e0d7d1..c49aa62 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h @@ -250,6 +250,7 @@ struct mx6_ddr_sysinfo { u8 mif3_mode; /* Command prediction working mode */ u8 rst_to_cke; /* Time from SDE enable to CKE rise */ u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */ + u8 pd_fast_exit;/* enable precharge powerdown fast-exit */ }; /* -- cgit v1.1 From 12d8a729137ec58107236c472ddb14a819e7bd0b Mon Sep 17 00:00:00 2001 From: "rev13@wp.pl" Date: Sun, 1 Mar 2015 12:44:39 +0100 Subject: ARM: Add ARMv7-M support Signed-off-by: Kamil Lulko --- arch/arm/include/asm/armv7m.h | 60 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 arch/arm/include/asm/armv7m.h (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/armv7m.h b/arch/arm/include/asm/armv7m.h new file mode 100644 index 0000000..d2aa1c4 --- /dev/null +++ b/arch/arm/include/asm/armv7m.h @@ -0,0 +1,60 @@ +/* + * (C) Copyright 2010,2011 + * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com + * + * (C) Copyright 2015 + * Kamil Lulko, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARMV7M_H +#define ARMV7M_H + +#if defined(__ASSEMBLY__) +.syntax unified +.thumb +#endif + +#define V7M_SCB_BASE 0xE000ED00 +#define V7M_MPU_BASE 0xE000ED90 + +#define V7M_SCB_VTOR 0x08 + +#if !defined(__ASSEMBLY__) +struct v7m_scb { + uint32_t cpuid; /* CPUID Base Register */ + uint32_t icsr; /* Interrupt Control and State Register */ + uint32_t vtor; /* Vector Table Offset Register */ + uint32_t aircr; /* App Interrupt and Reset Control Register */ +}; +#define V7M_SCB ((struct v7m_scb *)V7M_SCB_BASE) + +#define V7M_AIRCR_VECTKEY 0x5fa +#define V7M_AIRCR_VECTKEY_SHIFT 16 +#define V7M_AIRCR_ENDIAN (1 << 15) +#define V7M_AIRCR_PRIGROUP_SHIFT 8 +#define V7M_AIRCR_PRIGROUP_MSK (0x7 << V7M_AIRCR_PRIGROUP_SHIFT) +#define V7M_AIRCR_SYSRESET (1 << 2) + +#define V7M_ICSR_VECTACT_MSK 0xFF + +struct v7m_mpu { + uint32_t type; /* Type Register */ + uint32_t ctrl; /* Control Register */ + uint32_t rnr; /* Region Number Register */ + uint32_t rbar; /* Region Base Address Register */ + uint32_t rasr; /* Region Attribute and Size Register */ +}; +#define V7M_MPU ((struct v7m_mpu *)V7M_MPU_BASE) + +#define V7M_MPU_CTRL_ENABLE (1 << 0) +#define V7M_MPU_CTRL_HFNMIENA (1 << 1) + +#define V7M_MPU_RASR_EN (1 << 0) +#define V7M_MPU_RASR_SIZE_BITS 1 +#define V7M_MPU_RASR_SIZE_4GB (31 << V7M_MPU_RASR_SIZE_BITS) +#define V7M_MPU_RASR_AP_RW_RW (3 << 24) + +#endif /* !defined(__ASSEMBLY__) */ +#endif /* ARMV7M_H */ -- cgit v1.1 From eaaa4f7e0e99b7bb1f5caefd96ade7c2ee891bf3 Mon Sep 17 00:00:00 2001 From: "rev13@wp.pl" Date: Sun, 1 Mar 2015 12:44:40 +0100 Subject: ARMv7M: Add STM32F4 support Signed-off-by: Kamil Lulko Reviewed-by: Tom Rini --- arch/arm/include/asm/arch-stm32f4/fmc.h | 75 +++++++++++++++++++ arch/arm/include/asm/arch-stm32f4/gpio.h | 116 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-stm32f4/stm32.h | 108 ++++++++++++++++++++++++++++ 3 files changed, 299 insertions(+) create mode 100644 arch/arm/include/asm/arch-stm32f4/fmc.h create mode 100644 arch/arm/include/asm/arch-stm32f4/gpio.h create mode 100644 arch/arm/include/asm/arch-stm32f4/stm32.h (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-stm32f4/fmc.h b/arch/arm/include/asm/arch-stm32f4/fmc.h new file mode 100644 index 0000000..4ab3031 --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f4/fmc.h @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2013 + * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com + * + * (C) Copyright 2015 + * Kamil Lulko, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MACH_FMC_H_ +#define _MACH_FMC_H_ + +struct stm32_fmc_regs { + u32 sdcr1; /* Control register 1 */ + u32 sdcr2; /* Control register 2 */ + u32 sdtr1; /* Timing register 1 */ + u32 sdtr2; /* Timing register 2 */ + u32 sdcmr; /* Mode register */ + u32 sdrtr; /* Refresh timing register */ + u32 sdsr; /* Status register */ +}; + +/* + * FMC registers base + */ +#define STM32_SDRAM_FMC_BASE 0xA0000140 +#define STM32_SDRAM_FMC ((struct stm32_fmc_regs *)STM32_SDRAM_FMC_BASE) + +/* Control register SDCR */ +#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */ +#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */ +#define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */ +#define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */ +#define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */ +#define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */ +#define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */ +#define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */ +#define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */ + +/* Timings register SDTR */ +#define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */ +#define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */ +#define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */ +#define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */ +#define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */ +#define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */ +#define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */ + + +#define FMC_SDCMR_NRFS_SHIFT 5 + +#define FMC_SDCMR_MODE_NORMAL 0 +#define FMC_SDCMR_MODE_START_CLOCK 1 +#define FMC_SDCMR_MODE_PRECHARGE 2 +#define FMC_SDCMR_MODE_AUTOREFRESH 3 +#define FMC_SDCMR_MODE_WRITE_MODE 4 +#define FMC_SDCMR_MODE_SELFREFRESH 5 +#define FMC_SDCMR_MODE_POWERDOWN 6 + +#define FMC_SDCMR_BANK_1 (1 << 4) +#define FMC_SDCMR_BANK_2 (1 << 3) + +#define FMC_SDCMR_MODE_REGISTER_SHIFT 9 + +#define FMC_SDSR_BUSY (1 << 5) + +#define FMC_BUSY_WAIT() do { \ + __asm__ __volatile__ ("dsb" : : : "memory"); \ + while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \ + ; \ + } while (0) + + +#endif /* _MACH_FMC_H_ */ diff --git a/arch/arm/include/asm/arch-stm32f4/gpio.h b/arch/arm/include/asm/arch-stm32f4/gpio.h new file mode 100644 index 0000000..7cd866e --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f4/gpio.h @@ -0,0 +1,116 @@ +/* + * (C) Copyright 2011 + * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com + * + * (C) Copyright 2015 + * Kamil Lulko, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _STM32_GPIO_H_ +#define _STM32_GPIO_H_ + +enum stm32_gpio_port { + STM32_GPIO_PORT_A = 0, + STM32_GPIO_PORT_B, + STM32_GPIO_PORT_C, + STM32_GPIO_PORT_D, + STM32_GPIO_PORT_E, + STM32_GPIO_PORT_F, + STM32_GPIO_PORT_G, + STM32_GPIO_PORT_H, + STM32_GPIO_PORT_I +}; + +enum stm32_gpio_pin { + STM32_GPIO_PIN_0 = 0, + STM32_GPIO_PIN_1, + STM32_GPIO_PIN_2, + STM32_GPIO_PIN_3, + STM32_GPIO_PIN_4, + STM32_GPIO_PIN_5, + STM32_GPIO_PIN_6, + STM32_GPIO_PIN_7, + STM32_GPIO_PIN_8, + STM32_GPIO_PIN_9, + STM32_GPIO_PIN_10, + STM32_GPIO_PIN_11, + STM32_GPIO_PIN_12, + STM32_GPIO_PIN_13, + STM32_GPIO_PIN_14, + STM32_GPIO_PIN_15 +}; + +enum stm32_gpio_mode { + STM32_GPIO_MODE_IN = 0, + STM32_GPIO_MODE_OUT, + STM32_GPIO_MODE_AF, + STM32_GPIO_MODE_AN +}; + +enum stm32_gpio_otype { + STM32_GPIO_OTYPE_PP = 0, + STM32_GPIO_OTYPE_OD +}; + +enum stm32_gpio_speed { + STM32_GPIO_SPEED_2M = 0, + STM32_GPIO_SPEED_25M, + STM32_GPIO_SPEED_50M, + STM32_GPIO_SPEED_100M +}; + +enum stm32_gpio_pupd { + STM32_GPIO_PUPD_NO = 0, + STM32_GPIO_PUPD_UP, + STM32_GPIO_PUPD_DOWN +}; + +enum stm32_gpio_af { + STM32_GPIO_AF0 = 0, + STM32_GPIO_AF1, + STM32_GPIO_AF2, + STM32_GPIO_AF3, + STM32_GPIO_AF4, + STM32_GPIO_AF5, + STM32_GPIO_AF6, + STM32_GPIO_AF7, + STM32_GPIO_AF8, + STM32_GPIO_AF9, + STM32_GPIO_AF10, + STM32_GPIO_AF11, + STM32_GPIO_AF12, + STM32_GPIO_AF13, + STM32_GPIO_AF14, + STM32_GPIO_AF15 +}; + +struct stm32_gpio_dsc { + enum stm32_gpio_port port; + enum stm32_gpio_pin pin; +}; + +struct stm32_gpio_ctl { + enum stm32_gpio_mode mode; + enum stm32_gpio_otype otype; + enum stm32_gpio_speed speed; + enum stm32_gpio_pupd pupd; + enum stm32_gpio_af af; +}; + +static inline unsigned stm32_gpio_to_port(unsigned gpio) +{ + return gpio / 16; +} + +static inline unsigned stm32_gpio_to_pin(unsigned gpio) +{ + return gpio % 16; +} + +int stm32_gpio_config(const struct stm32_gpio_dsc *gpio_dsc, + const struct stm32_gpio_ctl *gpio_ctl); +int stm32_gpout_set(const struct stm32_gpio_dsc *gpio_dsc, int state); + +#endif /* _STM32_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h new file mode 100644 index 0000000..a9f88db --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f4/stm32.h @@ -0,0 +1,108 @@ +/* + * (C) Copyright 2011 + * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com + * + * (C) Copyright 2015 + * Kamil Lulko, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MACH_STM32_H_ +#define _MACH_STM32_H_ + +/* + * Peripheral memory map + */ +#define STM32_PERIPH_BASE 0x40000000 +#define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000) +#define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000) +#define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000) +#define STM32_AHB2PERIPH_BASE (STM32_PERIPH_BASE + 0x10000000) + +#define STM32_BUS_MASK 0xFFFF0000 + +/* + * Register maps + */ +struct stm32_rcc_regs { + u32 cr; /* RCC clock control */ + u32 pllcfgr; /* RCC PLL configuration */ + u32 cfgr; /* RCC clock configuration */ + u32 cir; /* RCC clock interrupt */ + u32 ahb1rstr; /* RCC AHB1 peripheral reset */ + u32 ahb2rstr; /* RCC AHB2 peripheral reset */ + u32 ahb3rstr; /* RCC AHB3 peripheral reset */ + u32 rsv0; + u32 apb1rstr; /* RCC APB1 peripheral reset */ + u32 apb2rstr; /* RCC APB2 peripheral reset */ + u32 rsv1[2]; + u32 ahb1enr; /* RCC AHB1 peripheral clock enable */ + u32 ahb2enr; /* RCC AHB2 peripheral clock enable */ + u32 ahb3enr; /* RCC AHB3 peripheral clock enable */ + u32 rsv2; + u32 apb1enr; /* RCC APB1 peripheral clock enable */ + u32 apb2enr; /* RCC APB2 peripheral clock enable */ + u32 rsv3[2]; + u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */ + u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */ + u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */ + u32 rsv4; + u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */ + u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */ + u32 rsv5[2]; + u32 bdcr; /* RCC Backup domain control */ + u32 csr; /* RCC clock control & status */ + u32 rsv6[2]; + u32 sscgr; /* RCC spread spectrum clock generation */ + u32 plli2scfgr; /* RCC PLLI2S configuration */ + u32 pllsaicfgr; + u32 dckcfgr; +}; + +struct stm32_pwr_regs { + u32 cr; + u32 csr; +}; + +struct stm32_flash_regs { + u32 acr; + u32 key; + u32 optkeyr; + u32 sr; + u32 cr; + u32 optcr; + u32 optcr1; +}; + +/* + * Registers access macros + */ +#define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x3800) +#define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE) + +#define STM32_PWR_BASE (STM32_APB1PERIPH_BASE + 0x7000) +#define STM32_PWR ((struct stm32_pwr_regs *)STM32_PWR_BASE) + +#define STM32_FLASH_BASE (STM32_AHB1PERIPH_BASE + 0x3C00) +#define STM32_FLASH ((struct stm32_flash_regs *)STM32_FLASH_BASE) + +#define STM32_FLASH_SR_BSY (1 << 16) + +#define STM32_FLASH_CR_PG (1 << 0) +#define STM32_FLASH_CR_SER (1 << 1) +#define STM32_FLASH_CR_STRT (1 << 16) +#define STM32_FLASH_CR_LOCK (1 << 31) +#define STM32_FLASH_CR_SNB_OFFSET 3 + +enum clock { + CLOCK_CORE, + CLOCK_AHB, + CLOCK_APB1, + CLOCK_APB2 +}; + +int configure_clocks(void); +unsigned long clock_get(enum clock clck); + +#endif /* _MACH_STM32_H_ */ -- cgit v1.1 From 526fcc220360fa6acceaa06d5c3c5bb2de57b2f0 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 21 Apr 2015 21:59:35 +0900 Subject: ARM: ARM720t: remove empty asm/arch/hardware.h arch/arm/cpu/arm720t/start.S includes , but the hardware.h headers of ARM720T boards are all empty. Signed-off-by: Masahiro Yamada Cc: Linus Walleij Cc: Stephen Warren Cc: Tom Warren --- arch/arm/include/asm/arch-arm720t/hardware.h | 17 ----------------- arch/arm/include/asm/arch-tegra114/hardware.h | 22 ---------------------- arch/arm/include/asm/arch-tegra124/hardware.h | 16 ---------------- arch/arm/include/asm/arch-tegra20/hardware.h | 13 ------------- arch/arm/include/asm/arch-tegra30/hardware.h | 22 ---------------------- 5 files changed, 90 deletions(-) delete mode 100644 arch/arm/include/asm/arch-arm720t/hardware.h delete mode 100644 arch/arm/include/asm/arch-tegra114/hardware.h delete mode 100644 arch/arm/include/asm/arch-tegra124/hardware.h delete mode 100644 arch/arm/include/asm/arch-tegra20/hardware.h delete mode 100644 arch/arm/include/asm/arch-tegra30/hardware.h (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-arm720t/hardware.h b/arch/arm/include/asm/arch-arm720t/hardware.h deleted file mode 100644 index 8ca42d9..0000000 --- a/arch/arm/include/asm/arch-arm720t/hardware.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef __ARM7_HW_H -#define __ARM7_HW_H - -/* - * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) - * Curt Brune - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) -/* include IntegratorCP/CM720T specific hardware file if there was one */ -#else -#error No hardware file defined for this configuration -#endif - -#endif /* __ARM7_HW_H */ diff --git a/arch/arm/include/asm/arch-tegra114/hardware.h b/arch/arm/include/asm/arch-tegra114/hardware.h deleted file mode 100644 index c21fbb6..0000000 --- a/arch/arm/include/asm/arch-tegra114/hardware.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef _TEGRA114_HARDWARE_H_ -#define _TEGRA114_HARDWARE_H_ - -/* include tegra specific hardware definitions */ - -#endif /* _TEGRA114_HARDWARE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/hardware.h b/arch/arm/include/asm/arch-tegra124/hardware.h deleted file mode 100644 index 114fce8..0000000 --- a/arch/arm/include/asm/arch-tegra124/hardware.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2013 - * NVIDIA Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA124_HARDWARE_H_ -#define _TEGRA124_HARDWARE_H_ - -/* - * Include Tegra-specific hardware definitions - * Nothing needed currently for Tegra124 - */ - -#endif /* _TEGRA124_HARDWARE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/hardware.h b/arch/arm/include/asm/arch-tegra20/hardware.h deleted file mode 100644 index a295894..0000000 --- a/arch/arm/include/asm/arch-tegra20/hardware.h +++ /dev/null @@ -1,13 +0,0 @@ -/* -* (C) Copyright 2010-2011 -* NVIDIA Corporation -* - * SPDX-License-Identifier: GPL-2.0+ -*/ - -#ifndef __TEGRA2_HW_H -#define __TEGRA2_HW_H - -/* include tegra specific hardware definitions */ - -#endif /* __TEGRA2_HW_H */ diff --git a/arch/arm/include/asm/arch-tegra30/hardware.h b/arch/arm/include/asm/arch-tegra30/hardware.h deleted file mode 100644 index b1a5aa9..0000000 --- a/arch/arm/include/asm/arch-tegra30/hardware.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef _TEGRA30_HARDWARE_H_ -#define _TEGRA30_HARDWARE_H_ - -/* include tegra specific hardware definitions */ - -#endif /* _TEGRA30-HARDWARE_H_ */ -- cgit v1.1 From c517771ae745dbba59112b8d311e41d37c0fc032 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Thu, 19 Mar 2015 09:20:46 -0700 Subject: driver/ldpaa_eth: Add LDPAA Ethernet driver LDPAA Ethernet driver is a freescale's new ethernet driver based on Layerscape architecture. Every ethernet driver controls on DPNI object. Where all DPNIs share one common DPBP and DPIO object to support Rx and Tx flows. Signed-off-by: Prabhakar Kushwaha CC: Cristian Sovaiala CC: Bogdan Hamciuc CC: J. German Rivera [York Sun: s/NetReceive/net_process_received_packet] Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-lsch3/config.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 0217582..1d2a7fa 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -10,6 +10,12 @@ #include #define CONFIG_SYS_PAGE_SIZE 0x10000 + +#ifndef L1_CACHE_BYTES +#define L1_CACHE_SHIFT 6 +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) +#endif + #define CONFIG_MP #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ /* Link Definitions */ -- cgit v1.1 From 060ef094600373ea2b25111006edc56c072d9bd7 Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 20 Mar 2015 19:28:05 -0700 Subject: armv8/fsl-lsch3: Implement workaround for erratum A008585 Generic Timer may contain an erroneous value. The workaround is to read it twice until getting the same value. Signed-off-by: York Sun --- arch/arm/include/asm/arch-fsl-lsch3/config.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 1d2a7fa..2d461d9 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -120,6 +120,7 @@ #ifdef CONFIG_LS2085A #define CONFIG_SYS_FSL_ERRATUM_A008336 #define CONFIG_SYS_FSL_ERRATUM_A008514 +#define CONFIG_SYS_FSL_ERRATUM_A008585 #endif #endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */ -- cgit v1.1 From f3f8c564a1cb745cef41c98dd2c29e3aad37dc4c Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Fri, 20 Mar 2015 19:28:06 -0700 Subject: armv8/ls2085a: Update common header file ls2085a_common.h contains hard-coded information for NOR/NAND flash, I2C, DDR, etc. These are platform specific. Move them out of common header file and placed into respective board header files. Move TEXTBASE to 1MB offset to fit NOR flash with up to 1MB sector size. Enable command auto complete. Update prompt symbol. Set fdt_high to 0xa0000000 because Linux requires that the fdt be 8-byte aligned and below 512 MiB. Besides ensuring compliance with the 512 MiB limit, this avoids problems with the dtb being misaligned within the FIT image. Change the MC FW, MC DPL and Debug server NOR addresses in compliance with the NOR flash layouts for 128MB flash. Add PCIe macros. Enable "loadb" command. Disable debug server. Enable workaround for erratum A008511. Stop reset on panic for postmortem debugging. Signed-off-by: Prabhakar Kushwaha Signed-off-by: Scott Wood Signed-off-by: Bhupesh Sharma Signed-off-by: Minghuan Lian Signed-off-by: York Sun --- arch/arm/include/asm/arch-fsl-lsch3/config.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 2d461d9..518e59c 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -108,6 +108,16 @@ /* IFC */ #define CONFIG_SYS_FSL_IFC_LE +/* PCIe */ +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) +#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) +#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000) +#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL +#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL +#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL +#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL + #ifdef CONFIG_LS2085A #define CONFIG_MAX_CPUS 16 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 @@ -119,6 +129,7 @@ #ifdef CONFIG_LS2085A #define CONFIG_SYS_FSL_ERRATUM_A008336 +#define CONFIG_SYS_FSL_ERRATUM_A008511 #define CONFIG_SYS_FSL_ERRATUM_A008514 #define CONFIG_SYS_FSL_ERRATUM_A008585 #endif -- cgit v1.1 From 07c6600068da31d0f7c67ac3eb92dfc4270f4c07 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Fri, 20 Mar 2015 19:28:10 -0700 Subject: armv8/fsl-lsch3: Set nodes in DVM domain This is required for TLB invalidation broadcasts to work. Signed-off-by: Scott Wood Signed-off-by: York Sun --- arch/arm/include/asm/arch-fsl-lsch3/config.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 518e59c..9121452 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -118,6 +118,12 @@ #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL +/* Cache Coherent Interconnect */ +#define CCI_MN_BASE 0x04000000 +#define CCI_MN_RNF_NODEID_LIST 0x180 +#define CCI_MN_DVM_DOMAIN_CTL 0x200 +#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 + #ifdef CONFIG_LS2085A #define CONFIG_MAX_CPUS 16 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -- cgit v1.1 From b991b981e04eddb30c47fe97fbcfb05099b4fd88 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Fri, 20 Mar 2015 19:28:12 -0700 Subject: fsl-lsch3: Introduce place for common early SoC init Signed-off-by: Scott Wood Signed-off-by: York Sun --- arch/arm/include/asm/arch-fsl-lsch3/soc.h | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/soc.h (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-fsl-lsch3/soc.h b/arch/arm/include/asm/arch-fsl-lsch3/soc.h new file mode 100644 index 0000000..16b723d --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-lsch3/soc.h @@ -0,0 +1,8 @@ +/* + * Copyright 2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +void fsl_lsch3_early_init_f(void); + -- cgit v1.1 From d746fef40653d17a64ff81a8ff57c55d122d8d5e Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Fri, 20 Mar 2015 19:28:13 -0700 Subject: armv8/ls2085a: Add workaround for USB erratum A-008751 Without this "USB may not work" according to the erratum text, though I did not notice a problem without it. Signed-off-by: Scott Wood Signed-off-by: York Sun --- arch/arm/include/asm/arch-fsl-lsch3/config.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 9121452..a81e3ed 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -124,6 +124,10 @@ #define CCI_MN_DVM_DOMAIN_CTL 0x200 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 +/* Supplemental Configuration */ +#define SCFG_BASE 0x01fc0000 +#define SCFG_USB3PRM1CR 0x000 + #ifdef CONFIG_LS2085A #define CONFIG_MAX_CPUS 16 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 @@ -138,6 +142,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A008511 #define CONFIG_SYS_FSL_ERRATUM_A008514 #define CONFIG_SYS_FSL_ERRATUM_A008585 +#define CONFIG_SYS_FSL_ERRATUM_A008751 #endif #endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */ -- cgit v1.1 From 31d34c6c4b4470b4cd2094693259fb48ec51e652 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Fri, 20 Mar 2015 19:28:16 -0700 Subject: armv8: Add SerDes framework for Layerscape Architecture Add support of SerDes framework for Layerscape Architecture. - Add support of 2 SerDes block - Add SerDes protocol parsing and detection - Create table of SerDes protocol supported by LS2085A Signed-off-by: Prabhakar Kushwaha Signed-off-by: Minghuan Lian Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-lsch3/config.h | 4 ++ arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h | 67 +++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 5 ++ 3 files changed, 76 insertions(+) create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index a81e3ed..98db1ef 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -38,6 +38,8 @@ #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ 0x18A0) +#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000) + /* SP (Cortex-A5) related */ #define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000) #define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR) @@ -133,6 +135,8 @@ #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_NUM_DDR_CONTROLLERS 3 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } +#define CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_FSL_SRDS_2 #else #error SoC not defined #endif diff --git a/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h new file mode 100644 index 0000000..2810f3f --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h @@ -0,0 +1,67 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_SERDES_H +#define __FSL_SERDES_H + +#include + +#define SRDS_MAX_LANES 8 + +enum srds_prtcl { + NONE = 0, + PCIE1, + PCIE2, + PCIE3, + PCIE4, + SATA1, + SATA2, + XAUI1, + XAUI2, + XFI1, + XFI2, + XFI3, + XFI4, + XFI5, + XFI6, + XFI7, + XFI8, + SGMII1, + SGMII2, + SGMII3, + SGMII4, + SGMII5, + SGMII6, + SGMII7, + SGMII8, + SGMII9, + SGMII10, + SGMII11, + SGMII12, + SGMII13, + SGMII14, + SGMII15, + SGMII16, + QSGMII_A, /* A indicates MACs 1-4 */ + QSGMII_B, /* B indicates MACs 5-8 */ + QSGMII_C, /* C indicates MACs 9-12 */ + QSGMII_D, /* D indicates MACs 12-16 */ + SERDES_PRCTL_COUNT +}; + +enum srds { + FSL_SRDS_1 = 0, + FSL_SRDS_2 = 1, +}; + +int is_serdes_configured(enum srds_prtcl device); +void fsl_serdes_init(void); + +int serdes_get_first_lane(u32 sd, enum srds_prtcl device); +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); +int is_serdes_prtcl_valid(int serdes, u32 prtcl); + +#endif /* __FSL_SERDES_H */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h index dd11ef7..91cf68b 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h @@ -63,6 +63,11 @@ struct ccsr_gur { #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f +#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000 +#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 +#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000 +#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24 + u8 res_180[0x200-0x180]; u32 scratchrw[32]; /* Scratch Read/Write */ u8 res_280[0x300-0x280]; -- cgit v1.1 From cd348efa6c8c38cc95495a34d784f9ea159ca41d Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Fri, 20 Mar 2015 19:28:19 -0700 Subject: net/memac_phy: reuse driver for little endian SoCs The memac for PHY management on little endian SoCs is similar on big endian SoCs, so we modify the driver by using I/O accessor function to handle the endianness, so the driver can be reused on little endian SoCs, we introduce CONFIG_SYS_MEMAC_LITTLE_ENDIAN for little endian SoCs, if the CONFIG_SYS_MEMAC_LITTLE_ENDIAN is defined, the I/O access is little endian, if not, the I/O access is big endian. Move fsl_memac.h out of powerpc include. Signed-off-by: Shaohui Xie Signed-off-by: York Sun --- arch/arm/include/asm/arch-fsl-lsch3/config.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 98db1ef..684c70f 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -109,6 +109,7 @@ /* IFC */ #define CONFIG_SYS_FSL_IFC_LE +#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN /* PCIe */ #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) -- cgit v1.1 From 9cc2c4713a822cccaa1c5872720a23675045dd42 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Fri, 20 Mar 2015 19:28:22 -0700 Subject: driver/ldpaa: Add support of WRIOP static data structure Wire rate IO Processor (WRIOP) provide support of receive and transmit ethernet frames from the ethernet MAC. Here Each WRIOP block supports upto 64 DPMACs. Create a house keeping data structure to support upto 16 DPMACs and store external phy related information. Signed-off-by: Prabhakar Kushwaha Signed-off-by: York Sun --- arch/arm/include/asm/arch-fsl-lsch3/config.h | 3 +++ arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 24 +++++++++++++++++++++++ 2 files changed, 27 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 684c70f..403b2ef 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -38,6 +38,9 @@ #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ 0x18A0) +#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000) +#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000) +#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000) #define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000) /* SP (Cortex-A5) related */ diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h index 91cf68b..d6bee60 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h @@ -47,6 +47,30 @@ struct ccsr_gur { u32 devdisr5; /* Device disable control 5 */ u32 devdisr6; /* Device disable control 6 */ u32 devdisr7; /* Device disable control 7 */ +#define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x00000001 +#define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x00000002 +#define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x00000004 +#define FSL_CHASSIS3_DEVDISR2_DPMAC4 0x00000008 +#define FSL_CHASSIS3_DEVDISR2_DPMAC5 0x00000010 +#define FSL_CHASSIS3_DEVDISR2_DPMAC6 0x00000020 +#define FSL_CHASSIS3_DEVDISR2_DPMAC7 0x00000040 +#define FSL_CHASSIS3_DEVDISR2_DPMAC8 0x00000080 +#define FSL_CHASSIS3_DEVDISR2_DPMAC9 0x00000100 +#define FSL_CHASSIS3_DEVDISR2_DPMAC10 0x00000200 +#define FSL_CHASSIS3_DEVDISR2_DPMAC11 0x00000400 +#define FSL_CHASSIS3_DEVDISR2_DPMAC12 0x00000800 +#define FSL_CHASSIS3_DEVDISR2_DPMAC13 0x00001000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC14 0x00002000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC15 0x00004000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC16 0x00008000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC17 0x00010000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC18 0x00020000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC19 0x00040000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC20 0x00080000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC21 0x00100000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x00200000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x00400000 +#define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x00800000 u8 res_08c[0x90-0x8c]; u32 coredisru; /* uppper portion for support of 64 cores */ u32 coredisrl; /* lower portion for support of 64 cores */ -- cgit v1.1 From a868e44333ebac080dd6ed81e5ae580691f7fd18 Mon Sep 17 00:00:00 2001 From: Peter Howard Date: Mon, 23 Mar 2015 09:19:56 +1100 Subject: davinci: add support for omapl138-lcdk board Signed-off-by: Peter Howard [trini: Add config file, update for ..._ether_addr() -> ..._ethaddr() rename] Signed-off-by: Tom Rini --- arch/arm/include/asm/mach-types.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index c424a22..5afe791 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -1108,6 +1108,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_KZM9G 4140 #define MACH_TYPE_COLIBRI_T30 4493 #define MACH_TYPE_APALIS_T30 4513 +#define MACH_TYPE_OMAPL138_LCDK 2495 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type -- cgit v1.1 From f12467d1a5d299738c19faeae39d3f093ef67624 Mon Sep 17 00:00:00 2001 From: Dileep Katta Date: Wed, 25 Mar 2015 04:04:51 +0530 Subject: ARM: DRA7: Set serial number environment variable This patch populates serial number environment variable from die_id_0 and die_id_1 register values for DRA7xx boards. The function is added in omap common code so that this can be re-used. Serial# environment variable will be useful to show correct information in "fastboot devices" commands. Ref: http://git.omapzoom.org/?p=repo/u-boot.git;a=commit;h=a6bcaaf67f6e4bcd97808f53d0ceb4b0c04d583c Signed-off-by: Angela Stegmaier Signed-off-by: Dileep Katta Reviewed-by: Tom Rini --- arch/arm/include/asm/omap_common.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index c8c3e71..b0296fb 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -362,6 +362,10 @@ struct omap_sys_ctrl_regs { u32 control_core_control_io1; u32 control_core_control_io2; u32 control_id_code; + u32 control_std_fuse_die_id_0; + u32 control_std_fuse_die_id_1; + u32 control_std_fuse_die_id_2; + u32 control_std_fuse_die_id_3; u32 control_std_fuse_opp_bgap; u32 control_ldosram_iva_voltage_ctrl; u32 control_ldosram_mpu_voltage_ctrl; @@ -578,6 +582,7 @@ void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control, s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb); void usb_fake_mac_from_die_id(u32 *id); +void usb_set_serial_num_from_die_id(u32 *id); void omap_smc1(u32 service, u32 val); -- cgit v1.1 From 23f2f4329d95c1372a5ec18014a1c8e88c2c0251 Mon Sep 17 00:00:00 2001 From: Bryan De Faria Date: Thu, 2 Apr 2015 10:57:07 +0200 Subject: arm: am437x: mux: Update mux names Correct and complete the mux names following AM437x Technical Reference Manual. Signed-off-by: Bryan De Faria --- arch/arm/include/asm/arch-am33xx/mux_am43xx.h | 87 +++++++++++++++++---------- 1 file changed, 56 insertions(+), 31 deletions(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h index 98fc2b5..2f4a3d1 100644 --- a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h @@ -137,14 +137,62 @@ struct pad_signals { int mcasp0_fsr; int mcasp0_axr1; int mcasp0_ahclkx; - int xdma_event_intr0; - int xdma_event_intr1; + int cam0_hd; + int cam0_vd; + int cam0_field; + int cam0_wen; + int cam0_pclk; + int cam0_data8; + int cam0_data9; + int cam1_data9; + int cam1_data8; + int cam1_hd; + int cam1_vd; + int cam1_pclk; + int cam1_field; + int cam1_wen; + int cam1_data0; + int cam1_data1; + int cam1_data2; + int cam1_data3; + int cam1_data4; + int cam1_data5; + int cam1_data6; + int cam1_data7; + int cam0_data0; + int cam0_data1; + int cam0_data2; + int cam0_data3; + int cam0_data4; + int cam0_data5; + int cam0_data6; + int cam0_data7; + int uart3_rxd; + int uart3_txd; + int uart3_ctsn; + int uart3_rtsn; + int gpio5_8; + int gpio5_9; + int gpio5_10; + int gpio5_11; + int gpio5_12; + int gpio5_13; + int spi4_sclk; + int spi4_d0; + int spi4_d1; + int spi4_cs0; + int spi2_sclk; + int spi2_d0; + int spi2_d1; + int spi2_cs0; + int xdma_evt_intr0; + int xdma_evt_intr1; + int clkreq; int nresetin_out; - int porz; - int nnmi; - int osc0_in; - int osc0_out; int rsvd1; + int nnmi; + int rsvd2; + int rsvd3; int tms; int tdi; int tdo; @@ -154,34 +202,11 @@ struct pad_signals { int emu1; int osc1_in; int osc1_out; - int pmic_power_en; int rtc_porz; - int rsvd2; - int ext_wakeup; - int enz_kaldo_1p8v; - int usb0_dm; - int usb0_dp; - int usb0_ce; - int usb0_id; - int usb0_vbus; + int ext_wakeup0; + int pmic_power_en0; int usb0_drvvbus; - int usb1_dm; - int usb1_dp; - int usb1_ce; - int usb1_id; - int usb1_vbus; int usb1_drvvbus; - int ddr_resetn; - int ddr_csn0; - int ddr_cke; - int ddr_ck; - int ddr_nck; - int ddr_casn; - int ddr_rasn; - int ddr_wen; - int ddr_ba0; - int ddr_ba1; - int ddr_ba2; }; #endif /* _MUX_AM43XX_H_ */ -- cgit v1.1 From c7ea243cc095d6510e1a1e3a4969e787a9d41271 Mon Sep 17 00:00:00 2001 From: Sanchayan Maity Date: Wed, 15 Apr 2015 16:24:22 +0530 Subject: ARM: vf610: Move DDR3 initialization to imx-common In order to avoid code duplication, move the DDR3 initialization to the common place under imx-common. Currently ROW_DIFF and COL_DIFF can be chosen from the board file. The JEDEC timings are specified using a common ddr3_jedec_timings structure. Signed-off-by: Stefan Agner Signed-off-by: Sanchayan Maity --- arch/arm/include/asm/arch-vf610/ddrmc-vf610.h | 72 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-vf610/imx-regs.h | 4 +- 2 files changed, 74 insertions(+), 2 deletions(-) create mode 100644 arch/arm/include/asm/arch-vf610/ddrmc-vf610.h (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h b/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h new file mode 100644 index 0000000..6730cde --- /dev/null +++ b/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2015 + * Toradex, Inc. + * + * Authors: Stefan Agner + * Sanchayan Maity + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_VF610_DDRMC_H +#define __ASM_ARCH_VF610_DDRMC_H + +struct ddrmc_lvl_info { + u16 wrlvl_reg_en; + u16 wrlvl_dl_0; + u16 wrlvl_dl_1; + u16 rdlvl_gt_reg_en; + u16 rdlvl_gt_dl_0; + u16 rdlvl_gt_dl_1; + u16 rdlvl_reg_en; + u16 rdlvl_dl_0; + u16 rdlvl_dl_1; +}; + +struct ddr3_jedec_timings { + u8 tinit; + u32 trst_pwron; + u32 cke_inactive; + u8 wrlat; + u8 caslat_lin; + u8 trc; + u8 trrd; + u8 tccd; + u8 tfaw; + u8 trp; + u8 twtr; + u8 tras_min; + u8 tmrd; + u8 trtp; + u32 tras_max; + u8 tmod; + u8 tckesr; + u8 tcke; + u8 trcd_int; + u8 tdal; + u16 tdll; + u8 trp_ab; + u16 tref; + u8 trfc; + u8 tpdex; + u8 txpdll; + u8 txsnr; + u16 txsr; + u8 cksrx; + u8 cksre; + u16 zqcl; + u16 zqinit; + u8 zqcs; + u8 ref_per_zq; + u8 aprebit; + u8 wlmrd; + u8 wldqsen; +}; + +void ddrmc_setup_iomux(void); +void ddrmc_phy_init(void); +void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, + struct ddrmc_lvl_info *lvl, + int col_diff, int row_diff); + +#endif diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 6b10bdf..866b303 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -196,8 +196,8 @@ #define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8) #define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f) #define DDRMC_CR97_WRLVL_EN (1 << 24) -#define DDRMC_CR98_WRLVL_DL_0 (0) -#define DDRMC_CR99_WRLVL_DL_1 (0) +#define DDRMC_CR98_WRLVL_DL_0(v) ((v) & 0xffff) +#define DDRMC_CR99_WRLVL_DL_1(v) ((v) & 0xffff) #define DDRMC_CR102_RDLVL_GT_REGEN (1 << 16) #define DDRMC_CR102_RDLVL_REG_EN (1 << 8) #define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << 8) -- cgit v1.1 From 8b4f9afac0642cea73084401d07f791f2ac63104 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Wed, 15 Apr 2015 16:24:23 +0530 Subject: ARM: vf610: Enable external 32KHz oscillator Enable the SCSC (Slow Clock Source Controller) and select the external 32KHz oscillator. This improves the accuracy of the RTC. Signed-off-by: Sanchayan Maity --- arch/arm/include/asm/arch-vf610/crm_regs.h | 1 + arch/arm/include/asm/arch-vf610/imx-regs.h | 11 ++++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index 724682c..78708e2 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -199,6 +199,7 @@ struct anadig_reg { #define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24) #define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26) #define CCM_CCGR3_ANADIG_CTRL_MASK 0x3 +#define CCM_CCGR3_SCSC_CTRL_MASK (0x3 << 4) #define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20) #define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22) #define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24) diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 866b303..aa60031 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -65,7 +65,7 @@ #define QSPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000) #define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000) #define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050000) -#define SCSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000) +#define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000) #define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000) #define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000) #define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000) @@ -264,6 +264,9 @@ #define SRC_SRSR_WDOG_A5 (0x1 << 3) #define SRC_SRSR_POR_RST (0x1 << 0) +/* Slow Clock Source Controller Module (SCSC) */ +#define SCSC_SOSC_CTR_SOSC_EN 0x1 + #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include @@ -448,6 +451,12 @@ struct mscm_ir { u16 rsvd3[848]; }; +/* SCSC */ +struct scsc_reg { + u32 sirc_ctr; + u32 sosc_ctr; +}; + #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_IMX_REGS_H__ */ -- cgit v1.1 From 1db503c4b982a06741142588756fdd788474034c Mon Sep 17 00:00:00 2001 From: Sanchayan Maity Date: Wed, 15 Apr 2015 16:24:24 +0530 Subject: ARM: vf610: Add SoC and CPU type detection Vybrid product family consists of several rather similar SoC which can be determined by softare during boot time. This allows use of variable ${soc} for Linux device tree files. Detect VF5xx CPU's by reading the CPU count register. We can determine the second number of the CPU type (VF6x0) which indicates the presence of a L2 cache. Signed-off-by: Stefan Agner Signed-off-by: Sanchayan Maity --- arch/arm/include/asm/arch-vf610/imx-regs.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index aa60031..a5908ca 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -457,6 +457,18 @@ struct scsc_reg { u32 sosc_ctr; }; +/* MSCM */ +struct mscm { + u32 cpxtype; + u32 cpxnum; + u32 cpxmaster; + u32 cpxcount; + u32 cpxcfg0; + u32 cpxcfg1; + u32 cpxcfg2; + u32 cpxcfg3; +}; + #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_IMX_REGS_H__ */ -- cgit v1.1 From e7b860fa4dd4de736d887deca19ca540abea4239 Mon Sep 17 00:00:00 2001 From: Sanchayan Maity Date: Wed, 15 Apr 2015 16:24:26 +0530 Subject: ARM: vf610: Initial integration for Colibri VF50/VF61 This adds initial support for Colibri VF50/VF61 based on Freescale Vybrid SoC. - CPU clocked at 396/500 MHz - DDR3 at 396MHz - for VF50, use PLL2 as memory clock (synchronous mode) - for VF61, use PLL1 as memory clock (asynchronous mode) - Console on UART0 (Colibri UART_A) - Ethernet on FEC1 - PLL5 based RMII clocking (E.g. No external crystal) - UART_A and UART_C I/O muxing - Boot from NAND by default Tested on Colibri VF50/VF61 booting using serial loader over UART. Signed-off-by: Sanchayan Maity Acked-by: Stefan Agner --- arch/arm/include/asm/arch-vf610/imx-regs.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index a5908ca..bf41971 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -263,6 +263,11 @@ #define SRC_SRSR_WDOG_M4 (0x1 << 4) #define SRC_SRSR_WDOG_A5 (0x1 << 3) #define SRC_SRSR_POR_RST (0x1 << 0) +#define SRC_SBMR2_BMOD_MASK (0x3 << 24) +#define SRC_SBMR2_BMOD_SHIFT 24 +#define SRC_SBMR2_BMOD_FUSES 0x0 +#define SRC_SBMR2_BMOD_SERIAL 0x1 +#define SRC_SBMR2_BMOD_RCON 0x2 /* Slow Clock Source Controller Module (SCSC) */ #define SCSC_SOSC_CTR_SOSC_EN 0x1 -- cgit v1.1 From a94bb7a42c0c377bd4eecc8aec1ef454c9bad51a Mon Sep 17 00:00:00 2001 From: Sanchayan Maity Date: Wed, 15 Apr 2015 16:24:27 +0530 Subject: usb: host: Add ehci-vf USB driver for ARM Vybrid SoC's This driver adds support for the USB peripheral on Freescale Vybrid SoC's. Signed-off-by: Sanchayan Maity --- arch/arm/include/asm/arch-vf610/crm_regs.h | 10 ++++++++++ arch/arm/include/asm/arch-vf610/imx-regs.h | 4 ++++ arch/arm/include/asm/imx-common/regs-usbphy.h | 26 ++++++++++++++++++++++++++ 3 files changed, 40 insertions(+) create mode 100644 arch/arm/include/asm/imx-common/regs-usbphy.h (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index 78708e2..bc6db2a 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -189,6 +189,7 @@ struct anadig_reg { #define CCM_REG_CTRL_MASK 0xffffffff #define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14) #define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16) +#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8) #define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14) #define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28) #define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 << 8) @@ -207,14 +208,23 @@ struct anadig_reg { #define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10) #define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28) #define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4) +#define CCM_CCGR7_USBC1_CTRL_MASK (0x3 << 8) #define CCM_CCGR9_FEC0_CTRL_MASK 0x3 #define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2) #define CCM_CCGR10_NFC_CTRL_MASK 0x3 +#define ANADIG_PLL7_CTRL_BYPASS (1 << 16) +#define ANADIG_PLL7_CTRL_ENABLE (1 << 13) +#define ANADIG_PLL7_CTRL_POWERDOWN (1 << 12) +#define ANADIG_PLL7_CTRL_DIV_SELECT (1 << 1) #define ANADIG_PLL5_CTRL_BYPASS (1 << 16) #define ANADIG_PLL5_CTRL_ENABLE (1 << 13) #define ANADIG_PLL5_CTRL_POWERDOWN (1 << 12) #define ANADIG_PLL5_CTRL_DIV_SELECT 1 +#define ANADIG_PLL3_CTRL_BYPASS (1 << 16) +#define ANADIG_PLL3_CTRL_ENABLE (1 << 13) +#define ANADIG_PLL3_CTRL_POWERDOWN (1 << 12) +#define ANADIG_PLL3_CTRL_DIV_SELECT (1 << 1) #define ANADIG_PLL2_CTRL_ENABLE (1 << 13) #define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12) #define ANADIG_PLL2_CTRL_DIV_SELECT 1 diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index bf41971..a7d765a 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -52,6 +52,7 @@ #define SAI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000) #define SAI3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000) #define CRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00033000) +#define USBC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00034000) #define PDB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000) #define PIT_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000) #define FTM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000) @@ -65,6 +66,8 @@ #define QSPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000) #define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000) #define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050000) +#define USB_PHY0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050800) +#define USB_PHY1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050C00) #define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000) #define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000) #define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000) @@ -84,6 +87,7 @@ #define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000) #define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000) #define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000) +#define USBC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00034000) #define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000) #define ENET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000) #define NFC_BASE_ADDR (AIPS1_BASE_ADDR + 0x00060000) diff --git a/arch/arm/include/asm/imx-common/regs-usbphy.h b/arch/arm/include/asm/imx-common/regs-usbphy.h new file mode 100644 index 0000000..220e45f --- /dev/null +++ b/arch/arm/include/asm/imx-common/regs-usbphy.h @@ -0,0 +1,26 @@ +/* + * Freescale USB PHY Register Definitions + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __REGS_USBPHY_H__ +#define __REGS_USBPHY_H__ + +#define USBPHY_CTRL 0x00000030 +#define USBPHY_CTRL_SET 0x00000034 +#define USBPHY_CTRL_CLR 0x00000038 +#define USBPHY_CTRL_TOG 0x0000003C +#define USBPHY_PWD 0x00000000 +#define USBPHY_TX 0x00000010 +#define USBPHY_RX 0x00000020 +#define USBPHY_DEBUG 0x00000050 + +#define USBPHY_CTRL_ENUTMILEVEL2 (1 << 14) +#define USBPHY_CTRL_ENUTMILEVEL3 (1 << 15) +#define USBPHY_CTRL_OTG_ID (1 << 27) +#define USBPHY_CTRL_CLKGATE (1 << 30) +#define USBPHY_CTRL_SFTRST (1 << 31) + +#endif /* __REGS_USBPHY_H__ */ -- cgit v1.1 From b2d5ac59859fa946e47fb6ab1f4f3486d4988680 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Tue, 24 Mar 2015 13:25:02 -0700 Subject: armv8/ls2085aqds: NAND boot support This adds NAND boot support for LS2085AQDS, using SPL framework. Details of forming NAND image can be found in README. Signed-off-by: Scott Wood [York Sun: Remove +S from defconfig after commit 252ed872] Signed-off-by: York Sun --- arch/arm/include/asm/arch-fsl-lsch3/config.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 403b2ef..77c20ab 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -130,6 +130,15 @@ #define CCI_MN_DVM_DOMAIN_CTL 0x200 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 +/* Device Configuration */ +#define DCFG_BASE 0x01e00000 +#define DCFG_PORSR1 0x000 +#define DCFG_PORSR1_RCW_SRC 0xff800000 +#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 + +#define DCFG_DCSR_BASE 0X700100000ULL +#define DCFG_DCSR_PORCR1 0x000 + /* Supplemental Configuration */ #define SCFG_BASE 0x01fc0000 #define SCFG_USB3PRM1CR 0x000 -- cgit v1.1 From 8b06460e5518eeec449298c91fb1424b36c9b305 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Fri, 20 Mar 2015 19:28:31 -0700 Subject: ls2085a: esdhc: Add esdhc support for ls2085a This patch adds esdhc support for ls2085a. Signed-off-by: Yangbo Lu Signed-off-by: York Sun --- arch/arm/include/asm/arch-fsl-lsch3/config.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 77c20ab..ca8d38c 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -31,6 +31,7 @@ #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) +#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) @@ -110,6 +111,7 @@ #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 +#define CONFIG_SYS_FSL_ESDHC_LE /* IFC */ #define CONFIG_SYS_FSL_IFC_LE #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN -- cgit v1.1 From d37c6288a6715dfc2cce16954facfe0a9700c64f Mon Sep 17 00:00:00 2001 From: Andrea Scian Date: Fri, 20 Mar 2015 16:00:25 +0100 Subject: gpio: add Xilinx Zynq PS GPIO driver Most of the code is taken (and adapted) from Linux kernel driver. Just add CONFIG_ZYNQ_GPIO to you config to enable it Signed-off-by: Andrea Scian Signed-off-by: Michal Simek --- arch/arm/include/asm/arch-zynq/gpio.h | 66 +++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-zynq/gpio.h b/arch/arm/include/asm/arch-zynq/gpio.h index a26ae87..9e1e7da 100644 --- a/arch/arm/include/asm/arch-zynq/gpio.h +++ b/arch/arm/include/asm/arch-zynq/gpio.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2013 Xilinx, Inc. + * Copyright (c) 2015 DAVE Embedded Systems * * SPDX-License-Identifier: GPL-2.0+ */ @@ -7,4 +8,69 @@ #ifndef _ZYNQ_GPIO_H #define _ZYNQ_GPIO_H +#define ZYNQ_GPIO_BASE_ADDRESS 0xE000A000 + +/* Maximum banks */ +#define ZYNQ_GPIO_MAX_BANK 4 + +#define ZYNQ_GPIO_BANK0_NGPIO 32 +#define ZYNQ_GPIO_BANK1_NGPIO 22 +#define ZYNQ_GPIO_BANK2_NGPIO 32 +#define ZYNQ_GPIO_BANK3_NGPIO 32 + +#define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \ + ZYNQ_GPIO_BANK1_NGPIO + \ + ZYNQ_GPIO_BANK2_NGPIO + \ + ZYNQ_GPIO_BANK3_NGPIO) + +#define ZYNQ_GPIO_BANK0_PIN_MIN 0 +#define ZYNQ_GPIO_BANK0_PIN_MAX (ZYNQ_GPIO_BANK0_PIN_MIN + \ + ZYNQ_GPIO_BANK0_NGPIO - 1) +#define ZYNQ_GPIO_BANK1_PIN_MIN (ZYNQ_GPIO_BANK0_PIN_MAX + 1) +#define ZYNQ_GPIO_BANK1_PIN_MAX (ZYNQ_GPIO_BANK1_PIN_MIN + \ + ZYNQ_GPIO_BANK1_NGPIO - 1) +#define ZYNQ_GPIO_BANK2_PIN_MIN (ZYNQ_GPIO_BANK1_PIN_MAX + 1) +#define ZYNQ_GPIO_BANK2_PIN_MAX (ZYNQ_GPIO_BANK2_PIN_MIN + \ + ZYNQ_GPIO_BANK2_NGPIO - 1) +#define ZYNQ_GPIO_BANK3_PIN_MIN (ZYNQ_GPIO_BANK2_PIN_MAX + 1) +#define ZYNQ_GPIO_BANK3_PIN_MAX (ZYNQ_GPIO_BANK3_PIN_MIN + \ + ZYNQ_GPIO_BANK3_NGPIO - 1) + +/* Register offsets for the GPIO device */ +/* LSW Mask & Data -WO */ +#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK)) +/* MSW Mask & Data -WO */ +#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK)) +/* Data Register-RW */ +#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK)) +/* Direction mode reg-RW */ +#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK)) +/* Output enable reg-RW */ +#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK)) +/* Interrupt mask reg-RO */ +#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK)) +/* Interrupt enable reg-WO */ +#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK)) +/* Interrupt disable reg-WO */ +#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK)) +/* Interrupt status reg-RO */ +#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK)) +/* Interrupt type reg-RW */ +#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK)) +/* Interrupt polarity reg-RW */ +#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK)) +/* Interrupt on any, reg-RW */ +#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK)) + +/* Disable all interrupts mask */ +#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF + +/* Mid pin number of a bank */ +#define ZYNQ_GPIO_MID_PIN_NUM 16 + +/* GPIO upper 16 bit mask */ +#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000 + +#define BIT(x) (1< Date: Wed, 15 Apr 2015 13:36:40 +0200 Subject: zynqmp: Add support for R5 sw loading Add support for loading sw for R5 with enabling for zynqmp. Signed-off-by: Michal Simek Signed-off-by: Siva Durga Prasad Paladugu --- arch/arm/include/asm/arch-zynqmp/hardware.h | 43 +++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 3 deletions(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index 97fb49a..3df3147 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -18,11 +18,15 @@ #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 struct crlapb_regs { - u32 reserved0[74]; + u32 reserved0[36]; + u32 cpu_r5_ctrl; /* 0x90 */ + u32 reserved1[37]; u32 timestamp_ref_ctrl; /* 0x128 */ - u32 reserved0_1[53]; + u32 reserved2[53]; u32 boot_mode; /* 0x200 */ - u32 reserved1[26]; + u32 reserved3[14]; + u32 rst_lpd_top; /* 0x23C */ + u32 reserved4[26]; }; #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) @@ -44,6 +48,39 @@ struct iou_scntr { #define SD_MODE 0x00000005 #define JTAG_MODE 0x00000000 +#define ZYNQMP_RPU_BASEADDR 0xFF9A0000 + +struct rpu_regs { + u32 rpu_glbl_ctrl; + u32 reserved0[63]; + u32 rpu0_cfg; /* 0x100 */ + u32 reserved1[63]; + u32 rpu1_cfg; /* 0x200 */ +}; + +#define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR) + +#define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000 + +struct crfapb_regs { + u32 reserved0[65]; + u32 rst_fpd_apu; /* 0x104 */ + u32 reserved1; +}; + +#define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR) + +#define ZYNQMP_APU_BASEADDR 0xFD5C0000 + +struct apu_regs { + u32 reserved0[16]; + u32 rvbar_addr0_l; /* 0x40 */ + u32 rvbar_addr0_h; /* 0x44 */ + u32 reserved1[20]; +}; + +#define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR) + /* Board version value */ #define ZYNQMP_CSU_VERSION_SILICON 0x0 #define ZYNQMP_CSU_VERSION_EP108 0x1 -- cgit v1.1 From 16247d28d5e50fca8b2e11b5e1804524bca83361 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 15 Apr 2015 14:59:19 +0200 Subject: zynqmp: Add support for emulation platform - Veloce Add support for Veloce - zynqmp emulation platform. Platform doesn't support SDHCI. Signed-off-by: Michal Simek --- arch/arm/include/asm/arch-zynqmp/hardware.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index 3df3147..188b5c2 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -84,6 +84,7 @@ struct apu_regs { /* Board version value */ #define ZYNQMP_CSU_VERSION_SILICON 0x0 #define ZYNQMP_CSU_VERSION_EP108 0x1 +#define ZYNQMP_CSU_VERSION_VELOCE 0x2 #define ZYNQMP_CSU_VERSION_QEMU 0x3 #endif /* _ASM_ARCH_HARDWARE_H */ -- cgit v1.1 From 39c56f55becad2d26f10bafa1e852eb2d396b2b4 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 15 Apr 2015 15:02:28 +0200 Subject: zynqmp: Add support for EMMC bootmode Add support for EMMC bootmode. Signed-off-by: Michal Simek --- arch/arm/include/asm/arch-zynqmp/hardware.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index 188b5c2..87792c2 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -45,7 +45,8 @@ struct iou_scntr { /* Bootmode setting values */ #define BOOT_MODES_MASK 0x0000000F -#define SD_MODE 0x00000005 +#define SD_MODE 0x00000003 +#define EMMC_MODE 0x00000006 #define JTAG_MODE 0x00000000 #define ZYNQMP_RPU_BASEADDR 0xFF9A0000 -- cgit v1.1 From 2594e03c64782e858e2e2d11beebd7e4685620dc Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Tue, 3 Mar 2015 15:01:44 +0530 Subject: zynqmp: i2c: Enable i2c driver for zynqMP Enable the i2c driver for ZynqMP Also enable the eeprom for read and writes to eeprom on ZynqMP ZynqMP uses the same i2c controller as in Zynq Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- arch/arm/include/asm/arch-zynqmp/hardware.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index 87792c2..1fedb1b 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -11,6 +11,9 @@ #define ZYNQ_SERIAL_BASEADDR0 0xFF000000 #define ZYNQ_SERIAL_BASEADDR1 0xFF001000 +#define ZYNQ_I2C_BASEADDR0 0xFF020000 +#define ZYNQ_I2C_BASEADDR1 0xFF030000 + #define ZYNQ_SDHCI_BASEADDR0 0xFF160000 #define ZYNQ_SDHCI_BASEADDR1 0xFF170000 -- cgit v1.1 From 48d7260d19d7b256f6404fe56e71754a18f88ceb Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Wed, 15 Apr 2015 11:48:48 +0530 Subject: zynqmp: Add SPI driver support for ZynqMP Added the SPI driver support for ZynqMP The controller is same as zynq SPI controller Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek Reviewed-by: Jagannadha Sutradharudu Teki --- arch/arm/include/asm/arch-zynqmp/hardware.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index 1fedb1b..c9dc49d 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -11,6 +11,9 @@ #define ZYNQ_SERIAL_BASEADDR0 0xFF000000 #define ZYNQ_SERIAL_BASEADDR1 0xFF001000 +#define ZYNQ_SPI_BASEADDR0 0xFF040000 +#define ZYNQ_SPI_BASEADDR1 0xFF050000 + #define ZYNQ_I2C_BASEADDR0 0xFF020000 #define ZYNQ_I2C_BASEADDR1 0xFF030000 -- cgit v1.1 From 31137acb27edc4e7d37bcae8f489740f5ea53a41 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 15 Apr 2015 15:21:37 +0200 Subject: zynqmp: Enable SDHCI0 options Enable SDHCI0 for zynqmp. Add empty gpio.h because of sdhci requirement. Signed-off-by: Michal Simek --- arch/arm/include/asm/arch-zynqmp/gpio.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 arch/arm/include/asm/arch-zynqmp/gpio.h (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-zynqmp/gpio.h b/arch/arm/include/asm/arch-zynqmp/gpio.h new file mode 100644 index 0000000..098bbde --- /dev/null +++ b/arch/arm/include/asm/arch-zynqmp/gpio.h @@ -0,0 +1,12 @@ +/* + * Copyright 2015 Xilinx, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_ZYNQMP_GPIO_H +#define __ARCH_ZYNQMP_GPIO_H + +/* Empty file - sdhci requires this. */ + +#endif -- cgit v1.1 From 9b9c6516b0119a4abe71b1598b2258c591f955f5 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 16 Mar 2015 16:43:23 +0900 Subject: ARM: zynq: move SoC headers to mach-zynq/include/mach Move arch/arm/include/asm/arch-zynq/* -> arch/arm/mach-zynq/include/mach/* Signed-off-by: Masahiro Yamada Signed-off-by: Michal Simek --- arch/arm/include/asm/arch-zynq/clk.h | 29 ------ arch/arm/include/asm/arch-zynq/gpio.h | 76 --------------- arch/arm/include/asm/arch-zynq/hardware.h | 149 ----------------------------- arch/arm/include/asm/arch-zynq/sys_proto.h | 28 ------ 4 files changed, 282 deletions(-) delete mode 100644 arch/arm/include/asm/arch-zynq/clk.h delete mode 100644 arch/arm/include/asm/arch-zynq/gpio.h delete mode 100644 arch/arm/include/asm/arch-zynq/hardware.h delete mode 100644 arch/arm/include/asm/arch-zynq/sys_proto.h (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/arch-zynq/clk.h b/arch/arm/include/asm/arch-zynq/clk.h deleted file mode 100644 index 250c5bc..0000000 --- a/arch/arm/include/asm/arch-zynq/clk.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2013 Xilinx Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ZYNQ_CLK_H_ -#define _ZYNQ_CLK_H_ - -enum zynq_clk { - armpll_clk, ddrpll_clk, iopll_clk, - cpu_6or4x_clk, cpu_3or2x_clk, cpu_2x_clk, cpu_1x_clk, - ddr2x_clk, ddr3x_clk, dci_clk, - lqspi_clk, smc_clk, pcap_clk, gem0_clk, gem1_clk, - fclk0_clk, fclk1_clk, fclk2_clk, fclk3_clk, can0_clk, can1_clk, - sdio0_clk, sdio1_clk, uart0_clk, uart1_clk, spi0_clk, spi1_clk, dma_clk, - usb0_aper_clk, usb1_aper_clk, gem0_aper_clk, gem1_aper_clk, - sdio0_aper_clk, sdio1_aper_clk, spi0_aper_clk, spi1_aper_clk, - can0_aper_clk, can1_aper_clk, i2c0_aper_clk, i2c1_aper_clk, - uart0_aper_clk, uart1_aper_clk, gpio_aper_clk, lqspi_aper_clk, - smc_aper_clk, swdt_clk, dbg_trc_clk, dbg_apb_clk, clk_max}; - -void zynq_clk_early_init(void); -int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate); -unsigned long zynq_clk_get_rate(enum zynq_clk clk); -const char *zynq_clk_get_name(enum zynq_clk clk); -unsigned long get_uart_clk(int dev_id); - -#endif diff --git a/arch/arm/include/asm/arch-zynq/gpio.h b/arch/arm/include/asm/arch-zynq/gpio.h deleted file mode 100644 index 9e1e7da..0000000 --- a/arch/arm/include/asm/arch-zynq/gpio.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (c) 2013 Xilinx, Inc. - * Copyright (c) 2015 DAVE Embedded Systems - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ZYNQ_GPIO_H -#define _ZYNQ_GPIO_H - -#define ZYNQ_GPIO_BASE_ADDRESS 0xE000A000 - -/* Maximum banks */ -#define ZYNQ_GPIO_MAX_BANK 4 - -#define ZYNQ_GPIO_BANK0_NGPIO 32 -#define ZYNQ_GPIO_BANK1_NGPIO 22 -#define ZYNQ_GPIO_BANK2_NGPIO 32 -#define ZYNQ_GPIO_BANK3_NGPIO 32 - -#define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \ - ZYNQ_GPIO_BANK1_NGPIO + \ - ZYNQ_GPIO_BANK2_NGPIO + \ - ZYNQ_GPIO_BANK3_NGPIO) - -#define ZYNQ_GPIO_BANK0_PIN_MIN 0 -#define ZYNQ_GPIO_BANK0_PIN_MAX (ZYNQ_GPIO_BANK0_PIN_MIN + \ - ZYNQ_GPIO_BANK0_NGPIO - 1) -#define ZYNQ_GPIO_BANK1_PIN_MIN (ZYNQ_GPIO_BANK0_PIN_MAX + 1) -#define ZYNQ_GPIO_BANK1_PIN_MAX (ZYNQ_GPIO_BANK1_PIN_MIN + \ - ZYNQ_GPIO_BANK1_NGPIO - 1) -#define ZYNQ_GPIO_BANK2_PIN_MIN (ZYNQ_GPIO_BANK1_PIN_MAX + 1) -#define ZYNQ_GPIO_BANK2_PIN_MAX (ZYNQ_GPIO_BANK2_PIN_MIN + \ - ZYNQ_GPIO_BANK2_NGPIO - 1) -#define ZYNQ_GPIO_BANK3_PIN_MIN (ZYNQ_GPIO_BANK2_PIN_MAX + 1) -#define ZYNQ_GPIO_BANK3_PIN_MAX (ZYNQ_GPIO_BANK3_PIN_MIN + \ - ZYNQ_GPIO_BANK3_NGPIO - 1) - -/* Register offsets for the GPIO device */ -/* LSW Mask & Data -WO */ -#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK)) -/* MSW Mask & Data -WO */ -#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK)) -/* Data Register-RW */ -#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK)) -/* Direction mode reg-RW */ -#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK)) -/* Output enable reg-RW */ -#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK)) -/* Interrupt mask reg-RO */ -#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK)) -/* Interrupt enable reg-WO */ -#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK)) -/* Interrupt disable reg-WO */ -#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK)) -/* Interrupt status reg-RO */ -#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK)) -/* Interrupt type reg-RW */ -#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK)) -/* Interrupt polarity reg-RW */ -#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK)) -/* Interrupt on any, reg-RW */ -#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK)) - -/* Disable all interrupts mask */ -#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF - -/* Mid pin number of a bank */ -#define ZYNQ_GPIO_MID_PIN_NUM 16 - -/* GPIO upper 16 bit mask */ -#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000 - -#define BIT(x) (1<