From 802bb57a584db2202a47d41ac730fe76ddeb4f33 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Mon, 16 Feb 2015 10:15:56 +0530 Subject: ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value The value in SDRAM_REF_CTRL controls the delay time between the initial rising edge of DDR_RESETn to rising edge of DDR_CKE (JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL should be written with a value corresponding to 500us delay before starting DDR initialization sequence, and configure proper value at the end of sequence. Signed-off-by: Lokesh Vutla --- arch/arm/include/asm/emif.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 342f045..7a545ea 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -1149,6 +1149,7 @@ struct emif_regs { u32 sdram_config; u32 sdram_config2; u32 ref_ctrl; + u32 ref_ctrl_final; u32 sdram_tim1; u32 sdram_tim2; u32 sdram_tim3; -- cgit v1.1