From 3599774eec9d06812c6124bcd0b34cebd7ec5e1c Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Mon, 23 May 2016 17:37:49 +0300 Subject: dra7xx: Enable USB_PHY3 32KHz clock DRA7xx has a 32KHz PHY clock for USB_PHY3 that must be enabled for USB1 instance in Super-Speed. Signed-off-by: Roger Quadros --- arch/arm/include/asm/omap_common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index ac34b0e..07f3848 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -145,6 +145,7 @@ struct prcm_regs { u32 cm_ssc_modfreqdiv_dpll_unipro; u32 cm_coreaon_usb_phy1_core_clkctrl; u32 cm_coreaon_usb_phy2_core_clkctrl; + u32 cm_coreaon_usb_phy3_core_clkctrl; u32 cm_coreaon_l3init_60m_gfclk_clkctrl; /* cm2.core */ -- cgit v1.1