From 101eec50f021a354487a511dc1f72691404b2b48 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 9 Jul 2014 19:48:41 +0300 Subject: keystone2: ddr: add DDR3 PHY configs updated for PG 2.0 Add DDR3 PHY configs updated for PG 2.0 Also add DDR3A PHY reset before init for PG2.0 SoCs. Acked-by: Murali Karicheri Signed-off-by: Hao Zhang Signed-off-by: Ivan Khoronzhuk --- arch/arm/include/asm/arch-keystone/ddr3.h | 1 + arch/arm/include/asm/arch-keystone/hardware.h | 2 ++ 2 files changed, 3 insertions(+) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h b/arch/arm/include/asm/arch-keystone/ddr3.h index 05b7e29..4d229a2 100644 --- a/arch/arm/include/asm/arch-keystone/ddr3.h +++ b/arch/arm/include/asm/arch-keystone/ddr3.h @@ -49,6 +49,7 @@ struct ddr3_emif_config { }; void ddr3_init(void); +void ddr3_reset_ddrphy(void); void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg); void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg); diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index f8f986c..db2d36b 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -80,6 +80,8 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_DDR3_PMCTL_OFFSET 0x38 #define KS2_DDR3_ZQCFG_OFFSET 0xC8 +#define KS2_DDR3_PLLCTRL_PHY_RESET 0x80000000 + #define KS2_UART0_BASE 0x02530c00 #define KS2_UART1_BASE 0x02531000 -- cgit v1.1