From d6bc30af524463b8020329b80150e773bbc77d27 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 7 Jan 2015 19:41:38 +0900 Subject: ARM: UniPhier: remove __packed that causes a problem on GCC 4.9 The DDR PHY training function, ddrphy_prepare_training() would not work if compiled with GCC 4.9. The struct ddrphy (arch/arm/include/asm/arch-uniphier/ddrphy-regs.h) is specified with __packed because it represents a hardware register mapping, but it turned out to cause a problem on GCC 4.9. If -mno-unaligned-access is specified (yes, it is in arch/arm/cpu/armv7/config.mk), GCC 4.9 is aware of the __attribute__((packed)) and generates extra instructions to perform the memory access in a way that does not cause unaligned access. (Actually it is not need here because the register base, the first argument of the ddrphy_prepare_training(), is always given with a 4-byte aligned address.) Anyway, as a result, readl() / writel() is divided into byte-wise accesses. The problem is that this hardware only accepts 4-byte register access. Byte-wise accesses lead to unexpected behavior. There are some options to avoid this problem. [1] Remove -mno-unaligned-access [2] Add __aligned(4) along with __packed to struct ddrphy [3] Remove __packed from struct ddrphy [1] solves the problem for ARMv7, but it does not for pre-ARMv6 and ARMv6-M architectures where -mno-unaligned-access is default. So, [1] does not seem reasonable in terms of code portability. Both [2] and [3] work well, but [2] seems too much. All the members of struct ddrphy have the u32 type. No padding would be inserted even if __packed is dropped. Signed-off-by: Masahiro Yamada Reviewed-by: Tom Rini --- arch/arm/include/asm/arch-uniphier/ddrphy-regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h b/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h index 484559c..6b7d600 100644 --- a/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h +++ b/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h @@ -72,7 +72,7 @@ struct ddrphy { u32 gtr; /* General Timing Register */ u32 rsv[3]; /* Reserved */ } dx[9]; -} __packed; +}; #endif /* __ASSEMBLY__ */ -- cgit v1.1 From 4a35d6071809178062afcd6872ce4502217d9f4a Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 21 Jan 2015 15:27:46 +0900 Subject: ARM: UniPhier: use for readability Signed-off-by: Masahiro Yamada --- arch/arm/include/asm/arch-uniphier/sg-regs.h | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-uniphier/sg-regs.h b/arch/arm/include/asm/arch-uniphier/sg-regs.h index fa5e6ae..7bf45c5 100644 --- a/arch/arm/include/asm/arch-uniphier/sg-regs.h +++ b/arch/arm/include/asm/arch-uniphier/sg-regs.h @@ -101,6 +101,7 @@ #else #include +#include #include static inline void sg_set_pinsel(int n, int value) @@ -111,23 +112,23 @@ static inline void sg_set_pinsel(int n, int value) static inline u32 sg_memconf_val_ch0(unsigned long size, int num) { - int size_mb = (size >> 20) / num; + int size_mb = size / num; u32 ret; switch (size_mb) { - case 64: + case SZ_64M: ret = SG_MEMCONF_CH0_SIZE_64MB; break; - case 128: + case SZ_128M: ret = SG_MEMCONF_CH0_SIZE_128MB; break; - case 256: + case SZ_256M: ret = SG_MEMCONF_CH0_SIZE_256MB; break; - case 512: + case SZ_512M: ret = SG_MEMCONF_CH0_SIZE_512MB; break; - case 1024: + case SZ_1G: ret = SG_MEMCONF_CH0_SIZE_1024MB; break; default: @@ -151,23 +152,23 @@ static inline u32 sg_memconf_val_ch0(unsigned long size, int num) static inline u32 sg_memconf_val_ch1(unsigned long size, int num) { - int size_mb = (size >> 20) / num; + int size_mb = size / num; u32 ret; switch (size_mb) { - case 64: + case SZ_64M: ret = SG_MEMCONF_CH1_SIZE_64MB; break; - case 128: + case SZ_128M: ret = SG_MEMCONF_CH1_SIZE_128MB; break; - case 256: + case SZ_256M: ret = SG_MEMCONF_CH1_SIZE_256MB; break; - case 512: + case SZ_512M: ret = SG_MEMCONF_CH1_SIZE_512MB; break; - case 1024: + case SZ_1G: ret = SG_MEMCONF_CH1_SIZE_1024MB; break; default: -- cgit v1.1 From 367a0d51dbb18983f047ca43b9233a121e39b024 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 21 Jan 2015 15:27:47 +0900 Subject: ARM: UniPhier: rename SG_MEMCONF_* macros for readability Match the suffixes of SG_MEMCONF_* macros with SZ_* macros defined by for readability. Signed-off-by: Masahiro Yamada --- arch/arm/include/asm/arch-uniphier/sg-regs.h | 40 ++++++++++++++-------------- 1 file changed, 20 insertions(+), 20 deletions(-) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-uniphier/sg-regs.h b/arch/arm/include/asm/arch-uniphier/sg-regs.h index 7bf45c5..9b468d4 100644 --- a/arch/arm/include/asm/arch-uniphier/sg-regs.h +++ b/arch/arm/include/asm/arch-uniphier/sg-regs.h @@ -25,19 +25,19 @@ /* Memory Configuration */ #define SG_MEMCONF (SG_CTRL_BASE | 0x0400) -#define SG_MEMCONF_CH0_SIZE_64MB ((0x0 << 10) | (0x01 << 0)) -#define SG_MEMCONF_CH0_SIZE_128MB ((0x0 << 10) | (0x02 << 0)) -#define SG_MEMCONF_CH0_SIZE_256MB ((0x0 << 10) | (0x03 << 0)) -#define SG_MEMCONF_CH0_SIZE_512MB ((0x1 << 10) | (0x00 << 0)) -#define SG_MEMCONF_CH0_SIZE_1024MB ((0x1 << 10) | (0x01 << 0)) +#define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0)) +#define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0)) +#define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0)) +#define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0)) +#define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0)) #define SG_MEMCONF_CH0_NUM_1 (0x1 << 8) #define SG_MEMCONF_CH0_NUM_2 (0x0 << 8) -#define SG_MEMCONF_CH1_SIZE_64MB ((0x0 << 11) | (0x01 << 2)) -#define SG_MEMCONF_CH1_SIZE_128MB ((0x0 << 11) | (0x02 << 2)) -#define SG_MEMCONF_CH1_SIZE_256MB ((0x0 << 11) | (0x03 << 2)) -#define SG_MEMCONF_CH1_SIZE_512MB ((0x1 << 11) | (0x00 << 2)) -#define SG_MEMCONF_CH1_SIZE_1024MB ((0x1 << 11) | (0x01 << 2)) +#define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2)) +#define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2)) +#define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2)) +#define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2)) +#define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2)) #define SG_MEMCONF_CH1_NUM_1 (0x1 << 9) #define SG_MEMCONF_CH1_NUM_2 (0x0 << 9) @@ -117,19 +117,19 @@ static inline u32 sg_memconf_val_ch0(unsigned long size, int num) switch (size_mb) { case SZ_64M: - ret = SG_MEMCONF_CH0_SIZE_64MB; + ret = SG_MEMCONF_CH0_SZ_64M; break; case SZ_128M: - ret = SG_MEMCONF_CH0_SIZE_128MB; + ret = SG_MEMCONF_CH0_SZ_128M; break; case SZ_256M: - ret = SG_MEMCONF_CH0_SIZE_256MB; + ret = SG_MEMCONF_CH0_SZ_256M; break; case SZ_512M: - ret = SG_MEMCONF_CH0_SIZE_512MB; + ret = SG_MEMCONF_CH0_SZ_512M; break; case SZ_1G: - ret = SG_MEMCONF_CH0_SIZE_1024MB; + ret = SG_MEMCONF_CH0_SZ_1G; break; default: BUG(); @@ -157,19 +157,19 @@ static inline u32 sg_memconf_val_ch1(unsigned long size, int num) switch (size_mb) { case SZ_64M: - ret = SG_MEMCONF_CH1_SIZE_64MB; + ret = SG_MEMCONF_CH1_SZ_64M; break; case SZ_128M: - ret = SG_MEMCONF_CH1_SIZE_128MB; + ret = SG_MEMCONF_CH1_SZ_128M; break; case SZ_256M: - ret = SG_MEMCONF_CH1_SIZE_256MB; + ret = SG_MEMCONF_CH1_SZ_256M; break; case SZ_512M: - ret = SG_MEMCONF_CH1_SIZE_512MB; + ret = SG_MEMCONF_CH1_SZ_512M; break; case SZ_1G: - ret = SG_MEMCONF_CH1_SIZE_1024MB; + ret = SG_MEMCONF_CH1_SZ_1G; break; default: BUG(); -- cgit v1.1 From 0ba924a4ecfe056ab637bfa207fc26cd0248e9ac Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 21 Jan 2015 15:27:48 +0900 Subject: ARM: UniPhier: add SG_MEMCONF macros for DDR channel 2 PH1-sLD3, PH1-LD6b have DDR channel 2. Signed-off-by: Masahiro Yamada --- arch/arm/include/asm/arch-uniphier/sg-regs.h | 44 ++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-uniphier/sg-regs.h b/arch/arm/include/asm/arch-uniphier/sg-regs.h index 9b468d4..4ae67c8 100644 --- a/arch/arm/include/asm/arch-uniphier/sg-regs.h +++ b/arch/arm/include/asm/arch-uniphier/sg-regs.h @@ -41,6 +41,13 @@ #define SG_MEMCONF_CH1_NUM_1 (0x1 << 9) #define SG_MEMCONF_CH1_NUM_2 (0x0 << 9) +#define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16)) +#define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16)) +#define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16)) +#define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16)) +#define SG_MEMCONF_CH2_NUM_1 (0x1 << 24) +#define SG_MEMCONF_CH2_NUM_2 (0x0 << 24) + #define SG_MEMCONF_SPARSEMEM (0x1 << 4) /* Pin Control */ @@ -189,6 +196,43 @@ static inline u32 sg_memconf_val_ch1(unsigned long size, int num) } return ret; } + +static inline u32 sg_memconf_val_ch2(unsigned long size, int num) +{ + int size_mb = size / num; + u32 ret; + + switch (size_mb) { + case SZ_64M: + ret = SG_MEMCONF_CH2_SZ_64M; + break; + case SZ_128M: + ret = SG_MEMCONF_CH2_SZ_128M; + break; + case SZ_256M: + ret = SG_MEMCONF_CH2_SZ_256M; + break; + case SZ_512M: + ret = SG_MEMCONF_CH2_SZ_512M; + break; + default: + BUG(); + break; + } + + switch (num) { + case 1: + ret |= SG_MEMCONF_CH2_NUM_1; + break; + case 2: + ret |= SG_MEMCONF_CH2_NUM_2; + break; + default: + BUG(); + break; + } + return ret; +} #endif /* __ASSEMBLY__ */ #endif /* ARCH_SG_REGS_H */ -- cgit v1.1