From 3c1d218a1d3048fb576677c47eab43049d0b7778 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 4 Apr 2016 11:41:26 -0700 Subject: armv8: LS2080A: Consolidate LS2080A and LS2085A LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun CC: Prabhakar Kushwaha Reviewed-by: Prabhakar Kushwaha --- arch/arm/include/asm/fsl_secure_boot.h | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) (limited to 'arch/arm/include/asm/fsl_secure_boot.h') diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index d576f2e..53cd755 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -44,15 +44,14 @@ #endif -#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) ||\ - defined(CONFIG_LS2085A) +#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) /* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit - * Similiarly for LS2080 and LS2085 + * Similiarly for LS2080 */ #define CONFIG_ESBC_ADDR_64BIT #endif -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A #define CONFIG_EXTRA_ENV \ "setenv fdt_high 0xa0000000;" \ "setenv initrd_high 0xcfffffff;" \ @@ -66,12 +65,11 @@ /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from * Non-XIP Memory (Nand/SD)*/ -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) ||\ - defined(CONFIG_LS2085A) +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) #define CONFIG_BOOTSCRIPT_COPY_RAM #endif /* The address needs to be modified according to NOR and DDR memory map */ -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A #define CONFIG_BS_HDR_ADDR_FLASH 0x583920000 #define CONFIG_BS_ADDR_FLASH 0x583900000 #define CONFIG_BS_HDR_ADDR_RAM 0xa3920000 -- cgit v1.1