From 56d83d1c046c693b65ab09c0e960d922ec639c2b Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Wed, 23 Apr 2014 18:17:51 +0200 Subject: arm: vf610: add DDR_SEL_PAD_CONTR register Set DDR_SEL_PAD_CONTR register explicitly to DDR3 which solves RAM issues with newer silicon (1.1). This register was added in revision 4 of the Vybrid Reference Manual. Signed-off-by: Stefan Agner --- arch/arm/include/asm/arch-vf610/imx-regs.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include/asm/arch-vf610/imx-regs.h') diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index c2f9761..0c28e1b 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -215,6 +215,7 @@ #define DDRMC_CR139_PHY_WRLV_EN(v) ((v) & 0xff) #define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v) (((v) & 0x1f) << 27) #define DDRMC_CR154_PAD_ZQ_MODE(v) (((v) & 0x3) << 21) +#define DDRMC_CR154_DDR_SEL_PAD_CONTR(v) (((v) & 0x3) << 18) #define DDRMC_CR155_AXI0_AWCACHE (1 << 10) #define DDRMC_CR155_PAD_ODT_BYTE1(v) ((v) & 0x7) #define DDRMC_CR158_TWR(v) ((v) & 0x3f) -- cgit v1.1