From 76cff2b10857c86211ef60024e672ce178cb6d69 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 13 Aug 2015 09:51:00 -0500 Subject: ARM: DRA74-evm: Use SMA_1 spare register to workaround DP83865 phy on SR2.0 DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet provided IODELAY values for standard RGMII phys do not work. Silicon Revision(SR) 2.0 provides an alternative bit configuration that allows us to do a "gross adjustment" to launch the data off a different internal clock edge. Manual IO Delay overrides are still necessary to fine tune the clock-to-data delays. This is a necessary workaround for the quirky ethernet Phy we have on the platform. NOTE: SMA registers are spare "kitchen sink" registers that does contain bits for other workaround as necessary as well. Hence the control for the same is introduced in a generic SoC specific, board generic location. Signed-off-by: Nishanth Menon Reviewed-by: Tom Rini --- arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h') diff --git a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h index 2f53d85..4cd0a3c 100644 --- a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h +++ b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h @@ -49,6 +49,10 @@ #define ISOLATE_IO 1 #define DEISOLATE_IO 0 +/* CTRL_CORE_SMA_SW_1 */ +#define RGMII2_ID_MODE_N_MASK (1 << 26) +#define RGMII1_ID_MODE_N_MASK (1 << 25) + /* PRM_IO_PMCTRL */ #define PMCTRL_ISOCLK_OVERRIDE_SHIFT 0 #define PMCTRL_ISOCLK_OVERRIDE_MASK (1 << 0) -- cgit v1.1