From 9ba18ff8efcc471635fb2768509fed025fa7db3c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 6 Jan 2016 11:06:31 +0800 Subject: imx: mx6ul/sx: fix mmdc_ch0 clk calculation Check "Figure 19-5. BUS clock generation" of i.MX 6SoloX Applications Processor Reference Manual and "Figure 18-5. BUS clock generation" of i.MX 6UltraLite Applications Processor Reference Manual. If mmdc clk sources from pll4_main_clk(pll_audio), the calculation is wrong. Fix mmdc_ch0 clk calculation. Also add PLL_AUDIO/VIDEO support for decode_pll. Signed-off-by: Peng Fan Cc: Stefano Babic --- arch/arm/include/asm/arch-mx6/crm_regs.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm/include/asm/arch-mx6') diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index f6ec09d..22212c2 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -1227,4 +1227,16 @@ struct mxc_ccm_reg { #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008 +#define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23) +#define BP_PMU_MISC2_AUDIO_DIV_MSB 23 + +#define BM_PMU_MISC2_AUDIO_DIV_LSB (1 << 15) +#define BP_PMU_MISC2_AUDIO_DIV_LSB 15 + +#define PMU_MISC2_AUDIO_DIV(v) \ + (((v & BM_PMU_MISC2_AUDIO_DIV_MSB) >> \ + (BP_PMU_MISC2_AUDIO_DIV_MSB - 1)) | \ + ((v & BM_PMU_MISC2_AUDIO_DIV_LSB) >> \ + BP_PMU_MISC2_AUDIO_DIV_LSB)) + #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ -- cgit v1.1