From d7cbcc762ea88ad20e9005a85bf7d55939b5e9d2 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Mon, 17 Feb 2014 17:33:16 +0100 Subject: spi: spi-mxc: add defines for clk inactive state for ECSPI Provide define for the SCLK_CTL field of the config reg of ECSPI. While at it, oder the defines to improve readability and make adding more defines easier. Signed-off-by: Markus Niebel Reviewed-by: Jagannadha Sutradharudu Teki --- arch/arm/include/asm/arch-mx6/imx-regs.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'arch/arm/include/asm/arch-mx6') diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index f2ad6e9..3c58c01 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -405,9 +405,10 @@ struct cspi_regs { #define MXC_CSPICTRL_CHAN 18 /* Bit position inside CON register to be associated with SS */ -#define MXC_CSPICON_POL 4 -#define MXC_CSPICON_PHA 0 -#define MXC_CSPICON_SSPOL 12 +#define MXC_CSPICON_PHA 0 /* SCLK phase control */ +#define MXC_CSPICON_POL 4 /* SCLK polarity */ +#define MXC_CSPICON_SSPOL 12 /* SS polarity */ +#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ #ifdef CONFIG_MX6SL #define MXC_SPI_BASE_ADDRESSES \ ECSPI1_BASE_ADDR, \ -- cgit v1.1 From 060aaada06ffdcd21c01180a07779551448d13ff Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Mon, 17 Feb 2014 17:33:18 +0100 Subject: spi: mxc_spi: i.MX6 DL/S have only 4 eCSPI controller The dual lite and solo variant have only 4 SPI controller. respect this in the MXC_SPI_BASE_ADRESSES macro Signed-off-by: Markus Niebel Reviewed-by: Jagannadha Sutradharudu Teki --- arch/arm/include/asm/arch-mx6/imx-regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/include/asm/arch-mx6') diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 3c58c01..26f2a88 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -409,7 +409,7 @@ struct cspi_regs { #define MXC_CSPICON_POL 4 /* SCLK polarity */ #define MXC_CSPICON_SSPOL 12 /* SS polarity */ #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ -#ifdef CONFIG_MX6SL +#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) #define MXC_SPI_BASE_ADDRESSES \ ECSPI1_BASE_ADDR, \ ECSPI2_BASE_ADDR, \ -- cgit v1.1