From 070c01291e25f4f16cd0df971ddb6c67a0a57152 Mon Sep 17 00:00:00 2001 From: "Ye.Li" Date: Tue, 10 Jun 2014 15:21:42 +0800 Subject: ENGR00315894-48 iMX6SX: Add iMX6SX SoC support Adding clks, pinmux, memory map, etc for iMX6SoloX. Signed-off-by: Fugang Duan Signed-off-by: Huang Shijie Signed-off-by: Jason Liu Signed-off-by: Frank Li Signed-off-by: Nitin Garg Signed-off-by: Ye.Li --- arch/arm/include/asm/arch-mx6/imx-regs.h | 120 +++++++++++++++++++++++++++++-- 1 file changed, 115 insertions(+), 5 deletions(-) (limited to 'arch/arm/include/asm/arch-mx6/imx-regs.h') diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 4cdf736..39df1fd 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -19,6 +19,19 @@ #define GPU_2D_ARB_END_ADDR 0x02203FFF #define OPENVG_ARB_BASE_ADDR 0x02204000 #define OPENVG_ARB_END_ADDR 0x02207FFF + +#elif CONFIG_MX6SX +#define CAAM_ARB_BASE_ADDR 0x00100000 +#define CAAM_ARB_END_ADDR 0x00107FFF +#define GPU_ARB_BASE_ADDR 0x01800000 +#define GPU_ARB_END_ADDR 0x01803FFF +#define APBH_DMA_ARB_BASE_ADDR 0x01804000 +#define APBH_DMA_ARB_END_ADDR 0x0180BFFF + +#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR +#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) +#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) + #else #define CAAM_ARB_BASE_ADDR 0x00100000 #define CAAM_ARB_END_ADDR 0x00103FFF @@ -32,21 +45,35 @@ #define GPU_2D_ARB_END_ADDR 0x00137FFF #define DTCP_ARB_BASE_ADDR 0x00138000 #define DTCP_ARB_END_ADDR 0x0013BFFF -#endif /* CONFIG_MX6SL */ #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) +#endif /* CONFIG_MX6SL */ + /* GPV - PL301 configuration ports */ -#ifdef CONFIG_MX6SL +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) #define GPV2_BASE_ADDR 0x00D00000 #else #define GPV2_BASE_ADDR 0x00200000 #endif +#ifdef CONFIG_MX6SX +#define GPV3_BASE_ADDR 0x00E00000 +#define GPV4_BASE_ADDR 0x00F00000 +#define GPV5_BASE_ADDR 0x01000000 +#define GPV6_BASE_ADDR 0x01100000 +#define PCIE_ARB_BASE_ADDR 0x08000000 +#define PCIE_ARB_END_ADDR 0x08FFFFFF + +#else #define GPV3_BASE_ADDR 0x00300000 #define GPV4_BASE_ADDR 0x00800000 +#define PCIE_ARB_BASE_ADDR 0x01000000 +#define PCIE_ARB_END_ADDR 0x01FFFFFF +#endif + #define IRAM_BASE_ADDR 0x00900000 #define SCU_BASE_ADDR 0x00A00000 #define IC_INTERFACES_BASE_ADDR 0x00A00100 @@ -56,13 +83,21 @@ #define L2_PL310_BASE 0x00A02000 #define GPV0_BASE_ADDR 0x00B00000 #define GPV1_BASE_ADDR 0x00C00000 -#define PCIE_ARB_BASE_ADDR 0x01000000 -#define PCIE_ARB_END_ADDR 0x01FFFFFF #define AIPS1_ARB_BASE_ADDR 0x02000000 #define AIPS1_ARB_END_ADDR 0x020FFFFF #define AIPS2_ARB_BASE_ADDR 0x02100000 #define AIPS2_ARB_END_ADDR 0x021FFFFF +#ifdef CONFIG_MX6SX +#define AIPS3_ARB_BASE_ADDR 0x02200000 +#define AIPS3_ARB_END_ADDR 0x022FFFFF +#define WEIM_ARB_BASE_ADDR 0x50000000 +#define WEIM_ARB_END_ADDR 0x57FFFFFF +#define QSPI1_ARB_BASE_ADDR 0x60000000 +#define QSPI1_ARB_END_ADDR 0x6FFFFFFF +#define QSPI2_ARB_BASE_ADDR 0x70000000 +#define QSPI2_ARB_END_ADDR 0x7FFFFFFF +#else #define SATA_ARB_BASE_ADDR 0x02200000 #define SATA_ARB_END_ADDR 0x02203FFF #define OPENVG_ARB_BASE_ADDR 0x02204000 @@ -75,8 +110,9 @@ #define IPU2_ARB_END_ADDR 0x02BFFFFF #define WEIM_ARB_BASE_ADDR 0x08000000 #define WEIM_ARB_END_ADDR 0x0FFFFFFF +#endif -#ifdef CONFIG_MX6SL +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) #define MMDC0_ARB_BASE_ADDR 0x80000000 #define MMDC0_ARB_END_ADDR 0xFFFFFFFF #define MMDC1_ARB_BASE_ADDR 0xC0000000 @@ -88,8 +124,10 @@ #define MMDC1_ARB_END_ADDR 0xFFFFFFFF #endif +#ifndef CONFIG_MX6SX #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR #define IPU_SOC_OFFSET 0x00200000 +#endif /* Defines for Blocks connected via AIPS (SkyBlue) */ #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR @@ -112,7 +150,11 @@ #define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) #define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000) #else + +#ifndef CONFIG_MX6SX #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) +#endif + #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) @@ -121,8 +163,10 @@ #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) #endif +#ifndef CONFIG_MX6SX #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) +#endif #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000) #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) @@ -153,10 +197,20 @@ #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) +#define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) #ifdef CONFIG_MX6SL #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) + +#elif CONFIG_MX6SX +#define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) +#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) +#define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) +#define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) +#define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) +#define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) + #else #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) @@ -189,6 +243,9 @@ #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) #ifdef CONFIG_MX6SL #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) + +#elif CONFIG_MX6SX +#define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) #else #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) #endif @@ -200,27 +257,74 @@ #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) +#ifdef CONFIG_MX6SX +#define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) +#else #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) +#endif #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) +#ifdef CONFIG_MX6SX +#define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) +#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) +#define QSPI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) +#else #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) +#endif #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000) #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) +#ifdef CONFIG_MX6SX +#define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) +#define QOSC_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) +#else #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) +#endif #define OTG_BASE_ADDR USB_BASE_ADDR +#ifdef CONFIG_MX6SX +#define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000) +#define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000) +#define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000) +#define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000) +#define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000) +#define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000) +#define LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) +#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) +#define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000) +#define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000) +#define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000) +#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) +#define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) +#define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) +#define WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) +#define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) +#define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) +#define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) +#define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000) +#define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000) +#define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000) +#define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000) +#define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000) +#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) +#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000) +#endif + #define CHIP_REV_1_0 0x10 #define CHIP_REV_1_1 0x11 #define CHIP_REV_1_2 0x12 #define CHIP_REV_1_3 0x13 #define CHIP_REV_1_4 0x14 #define CHIP_REV_1_5 0x15 +#ifndef CONFIG_MX6SX #define IRAM_SIZE 0x00040000 +#else +#define IRAM_SIZE 0x00020000 +#endif #define FEC_QUIRK_ENET_MAC #define SNVS_LPGPR 0x68 @@ -664,8 +768,14 @@ struct anatop_regs { #define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8)) #define ANATOP_PFD_CLKGATE_MASK(n) (1<