From 9955b4ab0187e0e9faac57acc01ebe7714d0ec23 Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 6 Jan 2015 13:18:47 -0800 Subject: driver/ddr/fsl: Add workaround for A008336 Erratum A008336 requires setting EDDRTQCR1[2] in DDRC DCSR space for 64-bit DDR controllers. Signed-off-by: York Sun --- arch/arm/include/asm/arch-fsl-lsch3/config.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/include/asm/arch-fsl-lsch3') diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index d4f688b..256adb0 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -30,6 +30,11 @@ #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ 0x18A0) +#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL +#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL +#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL +#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL + #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) -- cgit v1.1