From ca7fb12cc18e80d14cca9570aec1d544f5d8c169 Mon Sep 17 00:00:00 2001 From: Nikhil Badola Date: Fri, 26 Jun 2015 16:59:21 +0530 Subject: armv8/lsch3/config: Define CONFIG_SYS_CACHELINE_SIZE for LS2085A Define CONFIG_SYS_CACHELINE_SIZE for LS2085A which is required by USB XHCI stack for alignment Signed-off-by: Nikhil Badola Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-lsch3/config.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/include/asm/arch-fsl-lsch3/config.h') diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 8675e91..032cfd8 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -10,6 +10,7 @@ #include #define CONFIG_SYS_PAGE_SIZE 0x10000 +#define CONFIG_SYS_CACHELINE_SIZE 64 #ifndef L1_CACHE_BYTES #define L1_CACHE_SHIFT 6 -- cgit v1.1 From f7ff0e5e96d6741e93f97cbd1906669269b3b69e Mon Sep 17 00:00:00 2001 From: Nikhil Badola Date: Fri, 26 Jun 2015 17:01:50 +0530 Subject: armv8/lsch3/config: Define USB XHCI controller base address for LS2085A Define base address of both usb xhci controllers in lsch3 config in the format (IMMR + offset) for LS2085A Signed-off-by: Nikhil Badola Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-lsch3/config.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/include/asm/arch-fsl-lsch3/config.h') diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index 032cfd8..a4576dd 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -64,6 +64,9 @@ #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) +#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) + /* TZ Protection Controller Definitions */ #define TZPC_BASE 0x02200000 #define TZPCR0SIZE_BASE (TZPC_BASE) -- cgit v1.1